diff options
| author | hanahuang <hanahuang@google.com> | 2023-07-07 14:13:10 +0000 |
|---|---|---|
| committer | Ken Sun <kensun@google.com> | 2023-07-31 06:02:56 +0000 |
| commit | 430d88b5ae52e28ad0d990234af560a7f9d058d1 (patch) | |
| tree | cfb59c15b0a1fbbc8be1952899785c8e62f8a06f | |
| parent | c43d953baba2621e87339e3bd3687e2ef7833e41 (diff) | |
| download | bcm4398-430d88b5ae52e28ad0d990234af560a7f9d058d1.tar.gz | |
Avoid IRQ Affinity stuck issueandroid-14.0.0_r0.8android-14.0.0_r0.18main-16k-gs-shusky-5.15android-gs-shusky-udc-d1android-gs-shusky-5.15-android14-d1
Remove is_irq_on_big_core = true in dhd_plat_pcie_resume,
Because it didn't corretly reflect whether big core was used or not.
Bug: 285506721
Test: Pass Regression Test
Change-Id: Id8113890283210781ee42fb904fe8930c86636a5
Signed-off-by: kensun <kensun@google.com>
| -rw-r--r-- | dhd_custom_google.c | 11 |
1 files changed, 7 insertions, 4 deletions
diff --git a/dhd_custom_google.c b/dhd_custom_google.c index 8b7b1f7..3e0438c 100644 --- a/dhd_custom_google.c +++ b/dhd_custom_google.c @@ -80,6 +80,7 @@ static uint64 last_affinity_update_time_ns = 0; static uint hw_stage_val = 0; /* force to switch to small core at beginning */ static bool is_irq_on_big_core = TRUE; +static bool is_plat_pcie_resume = FALSE; static int pcie_ch_num = EXYNOS_PCIE_CH_NUM; #if defined(CONFIG_SOC_GOOGLE) @@ -784,11 +785,13 @@ irq_affinity_hysteresis_control(struct pci_dev *pdev, int resched_streak_max, DHD_ERROR(("%s switches to big core unsuccessfully!\n", __FUNCTION__)); } } - if (is_irq_on_big_core && (resched_streak_max <= RESCHED_STREAK_MAX_LOW) && - !has_recent_affinity_update) { + if (is_plat_pcie_resume || + (is_irq_on_big_core && (resched_streak_max <= RESCHED_STREAK_MAX_LOW) && + !has_recent_affinity_update)) { err = set_affinity(pdev->irq, cpumask_of(IRQ_AFFINITY_SMALL_CORE)); if (!err) { is_irq_on_big_core = FALSE; + is_plat_pcie_resume = FALSE; last_affinity_update_time_ns = curr_time_ns; DHD_INFO(("%s switches to all cores successfully\n", __FUNCTION__)); } else { @@ -979,8 +982,8 @@ int dhd_plat_pcie_resume(void *plat_info) { int ret = 0; ret = exynos_pcie_pm_resume(pcie_ch_num); - is_irq_on_big_core = true; - return ret; + is_plat_pcie_resume = TRUE; + return ret; } void dhd_plat_pin_dbg_show(void *plat_info) |