tests: Update MPU configuration for non-shared memory

Making the code/data memory shareable makes the memory non-cacheable and
performance is affected.
Modified MPU configuration, so that only the shared region is marked as
shareable and other regions used for code/data are mareked as non-
shareable.
This results in better performance.

Signed-off-by: Sam Nelson <sam.nelson@ti.com>

1 files changed, 18 insertions, 1 deletions

diff --git a/packages/ti/ipc/tests/R5fmpu_am65xx.cfg b/packages/ti/ipc/tests/R5fmpu_am65xx.cfg
index 9256a1f..00b2446 100644
--- a/packages/ti/ipc/tests/R5fmpu_am65xx.cfg
+++ b/packages/ti/ipc/tests/R5fmpu_am65xx.cfg
@@ -133,7 +133,7 @@ attrs.enable = true;
    Outer and Inner write-back, write-allocate & shareable       */
 attrs.bufferable = true;
 attrs.cacheable = true;
-attrs.shareable = true; /* NOTE: Setting it true will make it non-cacheable */
+attrs.shareable = false; /* NOTE: Setting it true will make it non-cacheable */
 attrs.tex = 1;
 
 /*--------------------------------------------------------------*/
@@ -143,3 +143,20 @@ attrs.accPerm = 0x3;          /* RW at PL1 & 2 */
 attrs.tex = 1;
 attrs.subregionDisableMask = 0;
 MPU.setRegionMeta(6, 0x9C000000, MPU.RegionSize_8M, attrs);
+
+/* This entry covers DDR memory */
+attrs.enable = true;
+/* The following 4 lines set the memory to be
+   Outer and Inner write-back, write-allocate & shareable       */
+attrs.bufferable = true;
+attrs.cacheable = true;
+attrs.shareable = true; /* NOTE: Setting it true will make it non-cacheable */
+attrs.tex = 1;
+
+/*--------------------------------------------------------------*/
+attrs.noExecute = false;
+//attrs.accPerm = 1;          /* RW at PL1 */
+attrs.accPerm = 0x3;          /* RW at PL1 & 2 */
+attrs.tex = 1;
+attrs.subregionDisableMask = 0;
+MPU.setRegionMeta(7, 0x9C000000, MPU.RegionSize_1M, attrs);