Merge "simpleperf: Run event_table_generator.py when building" into main am: 1cfe9faa25 am: 1438dac916 am: d1a69dd1e0

Original change: https://android-review.googlesource.com/c/platform/system/extras/+/2866495

Change-Id: I1a1c5789918c6d89d921c1b228fec9b94df7d939
Signed-off-by: Automerger Merge Worker <android-build-automerger-merge-worker@system.gserviceaccount.com>

5 files changed, 347 insertions, 807 deletions

diff --git a/simpleperf/Android.bp b/simpleperf/Android.bp
index bf33df45..c975fd60 100644
--- a/simpleperf/Android.bp
+++ b/simpleperf/Android.bp
@@ -207,6 +207,18 @@ cc_defaults {
     use_version_lib: true,
 }
 
+python_binary_host {
+    name: "event_table_generator",
+    srcs: ["event_table_generator.py"],
+}
+
+genrule {
+    name: "simpleperf_event_table",
+    out: ["event_table.cpp"],
+    tools: ["event_table_generator"],
+    cmd: "$(location event_table_generator) $(out)",
+}
+
 cc_defaults {
     name: "libsimpleperf_srcs",
     srcs: [
@@ -238,6 +250,7 @@ cc_defaults {
         "thread_tree.cpp",
         "tracing.cpp",
         "utils.cpp",
+        ":simpleperf_event_table",
     ],
     target: {
         android: {
diff --git a/simpleperf/event_table_generator.py b/simpleperf/event_table_generator.py
new file mode 100755
index 00000000..bbe955c0
--- /dev/null
+++ b/simpleperf/event_table_generator.py
@@ -0,0 +1,333 @@
+#!/usr/bin/env python3
+#
+# Copyright (C) 2015 The Android Open Source Project
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+import sys
+
+
+def gen_event_type_entry_str(event_type_name, event_type, event_config, description='',
+                             limited_arch=''):
+    """
+    return string as below:
+    EVENT_TYPE_TABLE_ENTRY(event_type_name, event_type, event_config, description, limited_arch)
+    """
+    return 'EVENT_TYPE_TABLE_ENTRY("%s", %s, %s, "%s", "%s")\n' % (
+        event_type_name, event_type, event_config, description, limited_arch)
+
+
+def gen_arm_event_type_entry_str(event_type_name, event_type, event_config, description):
+    return gen_event_type_entry_str(event_type_name, event_type, event_config, description,
+                                    "arm")
+
+
+def gen_hardware_events():
+    hardware_configs = ["cpu-cycles",
+                        "instructions",
+                        "cache-references",
+                        "cache-misses",
+                        "branch-instructions",
+                        "branch-misses",
+                        "bus-cycles",
+                        "stalled-cycles-frontend",
+                        "stalled-cycles-backend",
+                        ]
+    generated_str = ""
+    for config in hardware_configs:
+        event_type_name = config
+        event_config = "PERF_COUNT_HW_" + config.replace('-', '_').upper()
+
+        generated_str += gen_event_type_entry_str(
+            event_type_name, "PERF_TYPE_HARDWARE", event_config)
+
+    return generated_str
+
+
+def gen_software_events():
+    software_configs = ["cpu-clock",
+                        "task-clock",
+                        "page-faults",
+                        "context-switches",
+                        "cpu-migrations",
+                        ["minor-faults", "PERF_COUNT_SW_PAGE_FAULTS_MIN"],
+                        ["major-faults", "PERF_COUNT_SW_PAGE_FAULTS_MAJ"],
+                        "alignment-faults",
+                        "emulation-faults",
+                        ]
+    generated_str = ""
+    for config in software_configs:
+        if isinstance(config, list):
+            event_type_name = config[0]
+            event_config = config[1]
+        else:
+            event_type_name = config
+            event_config = "PERF_COUNT_SW_" + config.replace('-', '_').upper()
+
+        generated_str += gen_event_type_entry_str(
+            event_type_name, "PERF_TYPE_SOFTWARE", event_config)
+
+    return generated_str
+
+
+def gen_hw_cache_events():
+    hw_cache_types = [["L1-dcache", "PERF_COUNT_HW_CACHE_L1D"],
+                      ["L1-icache", "PERF_COUNT_HW_CACHE_L1I"],
+                      ["LLC", "PERF_COUNT_HW_CACHE_LL"],
+                      ["dTLB", "PERF_COUNT_HW_CACHE_DTLB"],
+                      ["iTLB", "PERF_COUNT_HW_CACHE_ITLB"],
+                      ["branch", "PERF_COUNT_HW_CACHE_BPU"],
+                      ["node", "PERF_COUNT_HW_CACHE_NODE"],
+                      ]
+    hw_cache_ops = [["loads", "load", "PERF_COUNT_HW_CACHE_OP_READ"],
+                    ["stores", "store", "PERF_COUNT_HW_CACHE_OP_WRITE"],
+                    ["prefetches", "prefetch",
+                     "PERF_COUNT_HW_CACHE_OP_PREFETCH"],
+                    ]
+    hw_cache_op_results = [["accesses", "PERF_COUNT_HW_CACHE_RESULT_ACCESS"],
+                           ["misses", "PERF_COUNT_HW_CACHE_RESULT_MISS"],
+                           ]
+    generated_str = ""
+    for (type_name, type_config) in hw_cache_types:
+        for (op_name_access, op_name_miss, op_config) in hw_cache_ops:
+            for (result_name, result_config) in hw_cache_op_results:
+                if result_name == "accesses":
+                    event_type_name = type_name + '-' + op_name_access
+                else:
+                    event_type_name = type_name + '-' + \
+                        op_name_miss + '-' + result_name
+                event_config = "((%s) | (%s << 8) | (%s << 16))" % (
+                    type_config, op_config, result_config)
+                generated_str += gen_event_type_entry_str(
+                    event_type_name, "PERF_TYPE_HW_CACHE", event_config)
+
+    return generated_str
+
+
+def gen_arm_raw_events():
+    raw_types = [
+        # Refer to "Table D6-7 PMU common architectural and microarchitectural event numbers" in ARMv8 specification.
+        [0x0000, "sw-incr", "Instruction architecturally executed, Condition code check pass, software increment"],
+        [0x0001, "l1i-cache-refill", "Level 1 instruction cache refill"],
+        [0x0002, "l1i-tlb-refill", "Attributable Level 1 instruction TLB refill"],
+        [0x0003, "l1d-cache-refill", "Level 1 data cache refill"],
+        [0x0004, "l1d-cache", "Level 1 data cache access"],
+        [0x0005, "l1d-tlb-refill", "Attributable Level 1 data TLB refill"],
+        [0x0006, "ld-retired", "Instruction architecturally executed, Condition code check pass, load"],
+        [0x0007, "st-retired", "Instruction architecturally executed, Condition code check pass, store"],
+        [0x0008, "inst-retired", "Instruction architecturally executed"],
+        [0x0009, "exc-taken", "Exception taken"],
+        [0x000A, "exc-return", "Instruction architecturally executed, Condition code check pass, exception return"],
+        [0x000B, "cid-write-retired",
+         "Instruction architecturally executed, Condition code check pass, write to CONTEXTIDR"],
+        [0x000C, "pc-write-retired",
+            "Instruction architecturally executed, Condition code check pass, software change of the PC"],
+        [0x000D, "br-immed-retired", "Instruction architecturally executed, immediate branch"],
+        [0x000E, "br-return-retired",
+         "Instruction architecturally executed, Condition code check pass, procedure return"],
+        [0x000F, "unaligned-ldst-retired",
+            "Instruction architecturally executed, Condition code check pass, unaligned load or store"],
+        [0x0010, "br-mis-pred", "Mispredicted or not predicted branch Speculatively executed"],
+        [0x0011, "cpu-cycles", "Cycle"],
+        [0x0012, "br-pred", "Predictable branch Speculatively executed"],
+        [0x0013, "mem-access", "Data memory access"],
+        [0x0014, "l1i-cache", "Attributable Level 1 instruction cache access"],
+        [0x0015, "l1d-cache-wb", "Attributable Level 1 data cache write-back"],
+        [0x0016, "l2d-cache", "Level 2 data cache access"],
+        [0x0017, "l2d-cache-refill", "Level 2 data cache refill"],
+        [0x0018, "l2d-cache-wb", "Attributable Level 2 data cache write-back"],
+        [0x0019, "bus-access", "Bus access"],
+        [0x001A, "memory-error", "Local memory error"],
+        [0x001B, "inst-spec", "Operation Speculatively executed"],
+        [0x001C, "ttbr-write-retired",
+         "Instruction architecturally executed, Condition code check pass, write to TTBR"],
+        [0x001D, "bus-cycles", "Bus cycle"],
+        [0x001E, "chain", "For odd-numbered counters, increments the count by one for each overflow of the preceding even-numbered counter. For even-numbered counters, there is no increment."],
+        [0x001F, "l1d-cache-allocate", "Attributable Level 1 data cache allocation without refill"],
+        [0x0020, "l2d-cache-allocate", "Attributable Level 2 data cache allocation without refill"],
+        [0x0021, "br-retired", "Instruction architecturally executed, branch"],
+        [0x0022, "br-mis-pred-retired", "Instruction architecturally executed, mispredicted branch"],
+        [0x0023, "stall-frontend", "No operation issued due to the frontend"],
+        [0x0024, "stall-backend", "No operation issued due to backend"],
+        [0x0025, "l1d-tlb", "Attributable Level 1 data or unified TLB access"],
+        [0x0026, "l1i-tlb", "Attributable Level 1 instruction TLB access"],
+        [0x0027, "l2i-cache", "Attributable Level 2 instruction cache access"],
+        [0x0028, "l2i-cache-refill", "Attributable Level 2 instruction cache refill"],
+        [0x0029, "l3d-cache-allocate", "Attributable Level 3 data or unified cache allocation without refill"],
+        [0x002A, "l3d-cache-refill", "Attributable Level 3 data cache refill"],
+        [0x002B, "l3d-cache", "Attributable Level 3 data cache access"],
+        [0x002C, "l3d-cache-wb", "Attributable Level 3 data or unified cache write-back"],
+        [0x002D, "l2d-tlb-refill", "Attributable Level 2 data or unified TLB refill"],
+        [0x002E, "l2i-tlb-refill", "Attributable Level 2 instruction TLB refill"],
+        [0x002F, "l2d-tlb", "Attributable Level 2 data or unified TLB access"],
+        [0x0030, "l2i-tlb", "Attributable Level 2 instruction TLB access"],
+        [0x0031, "remote-access", "Attributable access to another socket in a multi-socket system"],
+        [0x0032, "ll-cache", "Attributable Last Level data cache access"],
+        [0x0033, "ll-cache-miss", "Attributable Last level data or unified cache miss"],
+        [0x0034, "dtlb-walk", "Attributable data or unified TLB access with at least one translation table walk"],
+        [0x0035, "itlb-walk", "Attributable instruction TLB access with at least one translation table walk"],
+        [0x0036, "ll-cache-rd", "Attributable Last Level cache memory read"],
+        [0x0037, "ll-cache-miss-rd", "Attributable Last Level cache memory read miss"],
+        [0x0038, "remote-access-rd", "Attributable memory read access to another socket in a multi-socket system"],
+        [0x0039, "l1d-cache-lmiss-rd", "Level 1 data cache long-latency read miss"],
+        [0x003A, "op-retired", "Micro-operation architecturally executed"],
+        [0x003B, "op-spec", "Micro-operation Speculatively executed"],
+        [0x003C, "stall", "No operation sent for execution"],
+        [0x003D, "stall-slot-backend", "No operation sent for execution on a Slot due to the backend"],
+        [0x003E, "stall-slot-frontend", "No operation send for execution on a Slot due to the frontend"],
+        [0x003F, "stall-slot", "No operation sent for execution on a Slot"],
+        [0x0040, "l1d-cache-rd", "Level 1 data cache read"],
+        [0x4000, "sample-pop", "Sample Population"],
+        [0x4001, "sample-feed", "Sample Taken"],
+        [0x4002, "sample-filtrate", "Sample Taken and not removed by filtering"],
+        [0x4003, "sample-collision", "Sample collided with previous sample"],
+        [0x4004, "cnt-cycles", "Constant frequency cycles"],
+        [0x4005, "stall-backend-mem", "Memory stall cycles"],
+        [0x4006, "l1i-cache-lmiss", "Level 1 instruction cache long-latency miss"],
+        [0x4009, "l2d-cache-lmiss-rd", "Level 2 data cache long-latency read miss"],
+        [0x400A, "l2i-cache-lmiss", "Level 2 instruction cache long-latency miss"],
+        [0x400B, "l3d-cache-lmiss-rd", "Level 3 data cache long-latency read miss"],
+        [0x8002, "sve-inst-retired", "SVE Instructions architecturally executed"],
+        [0x8006, "sve-inst-spec", "SVE Instructions speculatively executed"],
+
+        # Refer to "Table K3.1 ARM recommendations for IMPLEMENTATION DEFINED event numbers" in ARMv8 specification.
+        # [0x0040, "l1d-cache-rd", "Attributable Level 1 data cache access, read"],
+        [0x0041, "l1d-cache-wr", "Attributable Level 1 data cache access, write"],
+        [0x0042, "l1d-cache-refill-rd", "Attributable Level 1 data cache refill, read"],
+        [0x0043, "l1d-cache-refill-wr", "Attributable Level 1 data cache refill, write"],
+        [0x0044, "l1d-cache-refill-inner", "Attributable Level 1 data cache refill, inner"],
+        [0x0045, "l1d-cache-refill-outer", "Attributable Level 1 data cache refill, outer"],
+        [0x0046, "l1d-cache-wb-victim", "Attributable Level 1 data cache Write-Back, victim"],
+        [0x0047, "l1d-cache-wb-clean", "Level 1 data cache Write-Back, cleaning and coherency"],
+        [0x0048, "l1d-cache-inval", "Attributable Level 1 data cache invalidate"],
+        # 0x0049-0x004B - Reserved
+        [0x004C, "l1d-tlb-refill-rd", "Attributable Level 1 data TLB refill, read"],
+        [0x004D, "l1d-tlb-refill-wr", "Attributable Level 1 data TLB refill, write"],
+        [0x004E, "l1d-tlb-rd", "Attributable Level 1 data or unified TLB access, read"],
+        [0x004F, "l1d-tlb-wr", "Attributable Level 1 data or unified TLB access, write"],
+        [0x0050, "l2d-cache-rd", "Attributable Level 2 data cache access, read"],
+        [0x0051, "l2d-cache-wr", "Attributable Level 2 data cache access, write"],
+        [0x0052, "l2d-cache-refill-rd", "Attributable Level 2 data cache refill, read"],
+        [0x0053, "l2d-cache-refill-wr", "Attributable Level 2 data cache refill, write"],
+        # 0x0054-0x0055 - Reserved
+        [0x0056, "l2d-cache-wb-victim", "Attributable Level 2 data cache Write-Back, victim"],
+        [0x0057, "l2d-cache-wb-clean", "Level 2 data cache Write-Back, cleaning and coherency"],
+        [0x0058, "l2d-cache-inval", "Attributable Level 2 data cache invalidate"],
+        # 0x0059-0x005B - Reserved
+        [0x005C, "l2d-tlb-refill-rd", "Attributable Level 2 data or unified TLB refill, read"],
+        [0x005D, "l2d-tlb-refill-wr", "Attributable Level 2 data or unified TLB refill, write"],
+        [0x005E, "l2d-tlb-rd", "Attributable Level 2 data or unified TLB access, read"],
+        [0x005F, "l2d-tlb-wr", "Attributable Level 2 data or unified TLB access, write"],
+        [0x0060, "bus-access-rd", "Bus access, read"],
+        [0x0061, "bus-access-wr", "Bus access, write"],
+        [0x0062, "bus-access-shared", "Bus access, Normal, Cacheable, Shareable"],
+        [0x0063, "bus-access-not-shared", "Bus access, not Normal, Cacheable, Shareable"],
+        [0x0064, "bus-access-normal", "Bus access, normal"],
+        [0x0065, "bus-access-periph", "Bus access, peripheral"],
+        [0x0066, "mem-access-rd", "Data memory access, read"],
+        [0x0067, "mem-access-wr", "Data memory access, write"],
+        [0x0068, "unaligned-ld-spec", "Unaligned access, read"],
+        [0x0069, "unaligned-st-spec", "Unaligned access, write"],
+        [0x006A, "unaligned-ldst-spec", "Unaligned access"],
+        # 0x006B - Reserved
+        [0x006C, "ldrex-spec", "Exclusive operation speculatively executed, LDREX or LDX"],
+        [0x006D, "strex-pass-spec", "Exclusive operation speculatively executed, STREX or STX pass"],
+        [0x006E, "strex-fail-spec", "Exclusive operation speculatively executed, STREX or STX fail"],
+        [0x006F, "strex-spec", "Exclusive operation speculatively executed, STREX or STX"],
+        [0x0070, "ld-spec", "Operation speculatively executed, load"],
+        [0x0071, "st-spec", "Operation speculatively executed, store"],
+        [0x0072, "ldst-spec", "Operation speculatively executed, load or store"],
+        [0x0073, "dp-spec", "Operation speculatively executed, integer data processing"],
+        [0x0074, "ase-spec", "Operation speculatively executed, Advanced SIMD instruction"],
+        [0x0075, "vfp-spec", "Operation speculatively executed, floating-point instruction"],
+        [0x0076, "pc-write-spec", "Operation speculatively executed, software change of the PC"],
+        [0x0077, "crypto-spec", "Operation speculatively executed, Cryptographic instruction"],
+        [0x0078, "br-immed-spec", "Branch speculatively executed, immediate branch"],
+        [0x0079, "br-return-spec", "Branch speculatively executed, procedure return"],
+        [0x007A, "br-indirect-spec", "Branch speculatively executed, indirect branch"],
+        # 0x007B - Reserved
+        [0x007C, "isb-spec", "Barrier speculatively executed, ISB"],
+        [0x007D, "dsb-spec", "Barrier speculatively executed, DSB"],
+        [0x007E, "dmb-spec", "Barrier speculatively executed, DMB"],
+        # 0x007F-0x0080 - Reserved
+        [0x0081, "exc-undef", "Exception taken, Other synchronous"],
+        [0x0082, "exc-svc", "Exception taken, Supervisor Call"],
+        [0x0083, "exc-pabort", "Exception taken, Instruction Abort"],
+        [0x0084, "exc-dabort", "Exception taken, Data Abort and SError"],
+        # 0x0085 - Reserved
+        [0x0086, "exc-irq", "Exception taken, IRQ"],
+        [0x0087, "exc-fiq", "Exception taken, FIQ"],
+        [0x0088, "exc-smc", "Exception taken, Secure Monitor Call"],
+        # 0x0089 - Reserved
+        [0x008A, "exc-hvc", "Exception taken, Hypervisor Call"],
+        [0x008B, "exc-trap-pabort", "Exception taken, Instruction Abort not Taken locallyb"],
+        [0x008C, "exc-trap-dabort", "Exception taken, Data Abort or SError not Taken locallyb"],
+        [0x008D, "exc-trap-other", "Exception taken, Other traps not Taken locallyb"],
+        [0x008E, "exc-trap-irq", "Exception taken, IRQ not Taken locallyb"],
+        [0x008F, "exc-trap-fiq", "Exception taken, FIQ not Taken locallyb"],
+        [0x0090, "rc-ld-spec", "Release consistency operation speculatively executed, Load-Acquire"],
+        [0x0091, "rc-st-spec", "Release consistency operation speculatively executed, Store-Release"],
+        # 0x0092-0x009F - Reserved
+        [0x00A0, "l3d-cache-rd", "Attributable Level 3 data or unified cache access, read"],
+        [0x00A1, "l3d-cache-wr", "Attributable Level 3 data or unified cache access, write"],
+        [0x00A2, "l3d-cache-refill-rd", "Attributable Level 3 data or unified cache refill, read"],
+        [0x00A3, "l3d-cache-refill-wr", "Attributable Level 3 data or unified cache refill, write"],
+        # 0x00A4-0x00A5 - Reserved
+        [0x00A6, "l3d-cache-wb-victim", "Attributable Level 3 data or unified cache Write-Back, victim"],
+        [0x00A7, "l3d-cache-wb-clean", "Attributable Level 3 data or unified cache Write-Back, cache clean"],
+        [0x00A8, "l3d-cache-inval", "Attributable Level 3 data or unified cache access, invalidate"],
+    ]
+    generated_str = ""
+    for item in raw_types:
+        event_type = 'PERF_TYPE_RAW'
+        event_type_name = "raw-" + item[1]
+        event_config = '0x%x' % item[0]
+        description = item[2]
+        generated_str += gen_arm_event_type_entry_str(event_type_name, event_type, event_config,
+                                                      description)
+    return generated_str
+
+
+def gen_events():
+    generated_str = """
+        #include "event_type.h"
+
+        namespace simpleperf {
+
+        #define EVENT_TYPE_TABLE_ENTRY(name, type, config, description, limited_arch) \
+            {name, type, config, description, limited_arch},
+
+        std::set<EventType> builtin_event_types = {
+    """
+    generated_str += gen_hardware_events() + '\n'
+    generated_str += gen_software_events() + '\n'
+    generated_str += gen_hw_cache_events() + '\n'
+    generated_str += gen_arm_raw_events() + '\n'
+    generated_str += """
+        };
+        }  // namespace simpleperf
+    """
+    return generated_str
+
+
+def main():
+    out_filename = sys.argv[1]
+    generated_str = gen_events()
+    fh = open(out_filename, 'w')
+    fh.write(generated_str)
+    fh.close()
+
+
+if __name__ == '__main__':
+    main()
diff --git a/simpleperf/event_type.cpp b/simpleperf/event_type.cpp
index 135e69da..0d10d12d 100644
--- a/simpleperf/event_type.cpp
+++ b/simpleperf/event_type.cpp
@@ -44,12 +44,7 @@ struct EventFormat {
   int shift;
 };
 
-#define EVENT_TYPE_TABLE_ENTRY(name, type, config, description, limited_arch) \
-  {name, type, config, description, limited_arch},
-
-static const std::set<EventType> builtin_event_types = {
-#include "event_type_table.h"
-};
+extern std::set<EventType> builtin_event_types;
 
 enum class EventFinderType {
   BUILTIN,
diff --git a/simpleperf/event_type_table.h b/simpleperf/event_type_table.h
deleted file mode 100644
index d209f0b7..00000000
--- a/simpleperf/event_type_table.h
+++ /dev/null
@@ -1,496 +0,0 @@
-// This file is auto-generated by generate-event_table.py.
-
-EVENT_TYPE_TABLE_ENTRY("cpu-cycles", PERF_TYPE_HARDWARE, PERF_COUNT_HW_CPU_CYCLES, "", "")
-EVENT_TYPE_TABLE_ENTRY("instructions", PERF_TYPE_HARDWARE, PERF_COUNT_HW_INSTRUCTIONS, "", "")
-EVENT_TYPE_TABLE_ENTRY("cache-references", PERF_TYPE_HARDWARE, PERF_COUNT_HW_CACHE_REFERENCES, "",
-                       "")
-EVENT_TYPE_TABLE_ENTRY("cache-misses", PERF_TYPE_HARDWARE, PERF_COUNT_HW_CACHE_MISSES, "", "")
-EVENT_TYPE_TABLE_ENTRY("branch-instructions", PERF_TYPE_HARDWARE, PERF_COUNT_HW_BRANCH_INSTRUCTIONS,
-                       "", "")
-EVENT_TYPE_TABLE_ENTRY("branch-misses", PERF_TYPE_HARDWARE, PERF_COUNT_HW_BRANCH_MISSES, "", "")
-EVENT_TYPE_TABLE_ENTRY("bus-cycles", PERF_TYPE_HARDWARE, PERF_COUNT_HW_BUS_CYCLES, "", "")
-EVENT_TYPE_TABLE_ENTRY("stalled-cycles-frontend", PERF_TYPE_HARDWARE,
-                       PERF_COUNT_HW_STALLED_CYCLES_FRONTEND, "", "")
-EVENT_TYPE_TABLE_ENTRY("stalled-cycles-backend", PERF_TYPE_HARDWARE,
-                       PERF_COUNT_HW_STALLED_CYCLES_BACKEND, "", "")
-
-EVENT_TYPE_TABLE_ENTRY("cpu-clock", PERF_TYPE_SOFTWARE, PERF_COUNT_SW_CPU_CLOCK, "", "")
-EVENT_TYPE_TABLE_ENTRY("task-clock", PERF_TYPE_SOFTWARE, PERF_COUNT_SW_TASK_CLOCK, "", "")
-EVENT_TYPE_TABLE_ENTRY("page-faults", PERF_TYPE_SOFTWARE, PERF_COUNT_SW_PAGE_FAULTS, "", "")
-EVENT_TYPE_TABLE_ENTRY("context-switches", PERF_TYPE_SOFTWARE, PERF_COUNT_SW_CONTEXT_SWITCHES, "",
-                       "")
-EVENT_TYPE_TABLE_ENTRY("cpu-migrations", PERF_TYPE_SOFTWARE, PERF_COUNT_SW_CPU_MIGRATIONS, "", "")
-EVENT_TYPE_TABLE_ENTRY("minor-faults", PERF_TYPE_SOFTWARE, PERF_COUNT_SW_PAGE_FAULTS_MIN, "", "")
-EVENT_TYPE_TABLE_ENTRY("major-faults", PERF_TYPE_SOFTWARE, PERF_COUNT_SW_PAGE_FAULTS_MAJ, "", "")
-EVENT_TYPE_TABLE_ENTRY("alignment-faults", PERF_TYPE_SOFTWARE, PERF_COUNT_SW_ALIGNMENT_FAULTS, "",
-                       "")
-EVENT_TYPE_TABLE_ENTRY("emulation-faults", PERF_TYPE_SOFTWARE, PERF_COUNT_SW_EMULATION_FAULTS, "",
-                       "")
-
-EVENT_TYPE_TABLE_ENTRY("L1-dcache-loads", PERF_TYPE_HW_CACHE,
-                       ((PERF_COUNT_HW_CACHE_L1D) | (PERF_COUNT_HW_CACHE_OP_READ << 8) |
-                        (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16)),
-                       "", "")
-EVENT_TYPE_TABLE_ENTRY("L1-dcache-load-misses", PERF_TYPE_HW_CACHE,
-                       ((PERF_COUNT_HW_CACHE_L1D) | (PERF_COUNT_HW_CACHE_OP_READ << 8) |
-                        (PERF_COUNT_HW_CACHE_RESULT_MISS << 16)),
-                       "", "")
-EVENT_TYPE_TABLE_ENTRY("L1-dcache-stores", PERF_TYPE_HW_CACHE,
-                       ((PERF_COUNT_HW_CACHE_L1D) | (PERF_COUNT_HW_CACHE_OP_WRITE << 8) |
-                        (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16)),
-                       "", "")
-EVENT_TYPE_TABLE_ENTRY("L1-dcache-store-misses", PERF_TYPE_HW_CACHE,
-                       ((PERF_COUNT_HW_CACHE_L1D) | (PERF_COUNT_HW_CACHE_OP_WRITE << 8) |
-                        (PERF_COUNT_HW_CACHE_RESULT_MISS << 16)),
-                       "", "")
-EVENT_TYPE_TABLE_ENTRY("L1-dcache-prefetches", PERF_TYPE_HW_CACHE,
-                       ((PERF_COUNT_HW_CACHE_L1D) | (PERF_COUNT_HW_CACHE_OP_PREFETCH << 8) |
-                        (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16)),
-                       "", "")
-EVENT_TYPE_TABLE_ENTRY("L1-dcache-prefetch-misses", PERF_TYPE_HW_CACHE,
-                       ((PERF_COUNT_HW_CACHE_L1D) | (PERF_COUNT_HW_CACHE_OP_PREFETCH << 8) |
-                        (PERF_COUNT_HW_CACHE_RESULT_MISS << 16)),
-                       "", "")
-EVENT_TYPE_TABLE_ENTRY("L1-icache-loads", PERF_TYPE_HW_CACHE,
-                       ((PERF_COUNT_HW_CACHE_L1I) | (PERF_COUNT_HW_CACHE_OP_READ << 8) |
-                        (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16)),
-                       "", "")
-EVENT_TYPE_TABLE_ENTRY("L1-icache-load-misses", PERF_TYPE_HW_CACHE,
-                       ((PERF_COUNT_HW_CACHE_L1I) | (PERF_COUNT_HW_CACHE_OP_READ << 8) |
-                        (PERF_COUNT_HW_CACHE_RESULT_MISS << 16)),
-                       "", "")
-EVENT_TYPE_TABLE_ENTRY("L1-icache-stores", PERF_TYPE_HW_CACHE,
-                       ((PERF_COUNT_HW_CACHE_L1I) | (PERF_COUNT_HW_CACHE_OP_WRITE << 8) |
-                        (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16)),
-                       "", "")
-EVENT_TYPE_TABLE_ENTRY("L1-icache-store-misses", PERF_TYPE_HW_CACHE,
-                       ((PERF_COUNT_HW_CACHE_L1I) | (PERF_COUNT_HW_CACHE_OP_WRITE << 8) |
-                        (PERF_COUNT_HW_CACHE_RESULT_MISS << 16)),
-                       "", "")
-EVENT_TYPE_TABLE_ENTRY("L1-icache-prefetches", PERF_TYPE_HW_CACHE,
-                       ((PERF_COUNT_HW_CACHE_L1I) | (PERF_COUNT_HW_CACHE_OP_PREFETCH << 8) |
-                        (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16)),
-                       "", "")
-EVENT_TYPE_TABLE_ENTRY("L1-icache-prefetch-misses", PERF_TYPE_HW_CACHE,
-                       ((PERF_COUNT_HW_CACHE_L1I) | (PERF_COUNT_HW_CACHE_OP_PREFETCH << 8) |
-                        (PERF_COUNT_HW_CACHE_RESULT_MISS << 16)),
-                       "", "")
-EVENT_TYPE_TABLE_ENTRY("LLC-loads", PERF_TYPE_HW_CACHE,
-                       ((PERF_COUNT_HW_CACHE_LL) | (PERF_COUNT_HW_CACHE_OP_READ << 8) |
-                        (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16)),
-                       "", "")
-EVENT_TYPE_TABLE_ENTRY("LLC-load-misses", PERF_TYPE_HW_CACHE,
-                       ((PERF_COUNT_HW_CACHE_LL) | (PERF_COUNT_HW_CACHE_OP_READ << 8) |
-                        (PERF_COUNT_HW_CACHE_RESULT_MISS << 16)),
-                       "", "")
-EVENT_TYPE_TABLE_ENTRY("LLC-stores", PERF_TYPE_HW_CACHE,
-                       ((PERF_COUNT_HW_CACHE_LL) | (PERF_COUNT_HW_CACHE_OP_WRITE << 8) |
-                        (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16)),
-                       "", "")
-EVENT_TYPE_TABLE_ENTRY("LLC-store-misses", PERF_TYPE_HW_CACHE,
-                       ((PERF_COUNT_HW_CACHE_LL) | (PERF_COUNT_HW_CACHE_OP_WRITE << 8) |
-                        (PERF_COUNT_HW_CACHE_RESULT_MISS << 16)),
-                       "", "")
-EVENT_TYPE_TABLE_ENTRY("LLC-prefetches", PERF_TYPE_HW_CACHE,
-                       ((PERF_COUNT_HW_CACHE_LL) | (PERF_COUNT_HW_CACHE_OP_PREFETCH << 8) |
-                        (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16)),
-                       "", "")
-EVENT_TYPE_TABLE_ENTRY("LLC-prefetch-misses", PERF_TYPE_HW_CACHE,
-                       ((PERF_COUNT_HW_CACHE_LL) | (PERF_COUNT_HW_CACHE_OP_PREFETCH << 8) |
-                        (PERF_COUNT_HW_CACHE_RESULT_MISS << 16)),
-                       "", "")
-EVENT_TYPE_TABLE_ENTRY("dTLB-loads", PERF_TYPE_HW_CACHE,
-                       ((PERF_COUNT_HW_CACHE_DTLB) | (PERF_COUNT_HW_CACHE_OP_READ << 8) |
-                        (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16)),
-                       "", "")
-EVENT_TYPE_TABLE_ENTRY("dTLB-load-misses", PERF_TYPE_HW_CACHE,
-                       ((PERF_COUNT_HW_CACHE_DTLB) | (PERF_COUNT_HW_CACHE_OP_READ << 8) |
-                        (PERF_COUNT_HW_CACHE_RESULT_MISS << 16)),
-                       "", "")
-EVENT_TYPE_TABLE_ENTRY("dTLB-stores", PERF_TYPE_HW_CACHE,
-                       ((PERF_COUNT_HW_CACHE_DTLB) | (PERF_COUNT_HW_CACHE_OP_WRITE << 8) |
-                        (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16)),
-                       "", "")
-EVENT_TYPE_TABLE_ENTRY("dTLB-store-misses", PERF_TYPE_HW_CACHE,
-                       ((PERF_COUNT_HW_CACHE_DTLB) | (PERF_COUNT_HW_CACHE_OP_WRITE << 8) |
-                        (PERF_COUNT_HW_CACHE_RESULT_MISS << 16)),
-                       "", "")
-EVENT_TYPE_TABLE_ENTRY("dTLB-prefetches", PERF_TYPE_HW_CACHE,
-                       ((PERF_COUNT_HW_CACHE_DTLB) | (PERF_COUNT_HW_CACHE_OP_PREFETCH << 8) |
-                        (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16)),
-                       "", "")
-EVENT_TYPE_TABLE_ENTRY("dTLB-prefetch-misses", PERF_TYPE_HW_CACHE,
-                       ((PERF_COUNT_HW_CACHE_DTLB) | (PERF_COUNT_HW_CACHE_OP_PREFETCH << 8) |
-                        (PERF_COUNT_HW_CACHE_RESULT_MISS << 16)),
-                       "", "")
-EVENT_TYPE_TABLE_ENTRY("iTLB-loads", PERF_TYPE_HW_CACHE,
-                       ((PERF_COUNT_HW_CACHE_ITLB) | (PERF_COUNT_HW_CACHE_OP_READ << 8) |
-                        (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16)),
-                       "", "")
-EVENT_TYPE_TABLE_ENTRY("iTLB-load-misses", PERF_TYPE_HW_CACHE,
-                       ((PERF_COUNT_HW_CACHE_ITLB) | (PERF_COUNT_HW_CACHE_OP_READ << 8) |
-                        (PERF_COUNT_HW_CACHE_RESULT_MISS << 16)),
-                       "", "")
-EVENT_TYPE_TABLE_ENTRY("iTLB-stores", PERF_TYPE_HW_CACHE,
-                       ((PERF_COUNT_HW_CACHE_ITLB) | (PERF_COUNT_HW_CACHE_OP_WRITE << 8) |
-                        (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16)),
-                       "", "")
-EVENT_TYPE_TABLE_ENTRY("iTLB-store-misses", PERF_TYPE_HW_CACHE,
-                       ((PERF_COUNT_HW_CACHE_ITLB) | (PERF_COUNT_HW_CACHE_OP_WRITE << 8) |
-                        (PERF_COUNT_HW_CACHE_RESULT_MISS << 16)),
-                       "", "")
-EVENT_TYPE_TABLE_ENTRY("iTLB-prefetches", PERF_TYPE_HW_CACHE,
-                       ((PERF_COUNT_HW_CACHE_ITLB) | (PERF_COUNT_HW_CACHE_OP_PREFETCH << 8) |
-                        (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16)),
-                       "", "")
-EVENT_TYPE_TABLE_ENTRY("iTLB-prefetch-misses", PERF_TYPE_HW_CACHE,
-                       ((PERF_COUNT_HW_CACHE_ITLB) | (PERF_COUNT_HW_CACHE_OP_PREFETCH << 8) |
-                        (PERF_COUNT_HW_CACHE_RESULT_MISS << 16)),
-                       "", "")
-EVENT_TYPE_TABLE_ENTRY("branch-loads", PERF_TYPE_HW_CACHE,
-                       ((PERF_COUNT_HW_CACHE_BPU) | (PERF_COUNT_HW_CACHE_OP_READ << 8) |
-                        (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16)),
-                       "", "")
-EVENT_TYPE_TABLE_ENTRY("branch-load-misses", PERF_TYPE_HW_CACHE,
-                       ((PERF_COUNT_HW_CACHE_BPU) | (PERF_COUNT_HW_CACHE_OP_READ << 8) |
-                        (PERF_COUNT_HW_CACHE_RESULT_MISS << 16)),
-                       "", "")
-EVENT_TYPE_TABLE_ENTRY("branch-stores", PERF_TYPE_HW_CACHE,
-                       ((PERF_COUNT_HW_CACHE_BPU) | (PERF_COUNT_HW_CACHE_OP_WRITE << 8) |
-                        (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16)),
-                       "", "")
-EVENT_TYPE_TABLE_ENTRY("branch-store-misses", PERF_TYPE_HW_CACHE,
-                       ((PERF_COUNT_HW_CACHE_BPU) | (PERF_COUNT_HW_CACHE_OP_WRITE << 8) |
-                        (PERF_COUNT_HW_CACHE_RESULT_MISS << 16)),
-                       "", "")
-EVENT_TYPE_TABLE_ENTRY("branch-prefetches", PERF_TYPE_HW_CACHE,
-                       ((PERF_COUNT_HW_CACHE_BPU) | (PERF_COUNT_HW_CACHE_OP_PREFETCH << 8) |
-                        (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16)),
-                       "", "")
-EVENT_TYPE_TABLE_ENTRY("branch-prefetch-misses", PERF_TYPE_HW_CACHE,
-                       ((PERF_COUNT_HW_CACHE_BPU) | (PERF_COUNT_HW_CACHE_OP_PREFETCH << 8) |
-                        (PERF_COUNT_HW_CACHE_RESULT_MISS << 16)),
-                       "", "")
-EVENT_TYPE_TABLE_ENTRY("node-loads", PERF_TYPE_HW_CACHE,
-                       ((PERF_COUNT_HW_CACHE_NODE) | (PERF_COUNT_HW_CACHE_OP_READ << 8) |
-                        (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16)),
-                       "", "")
-EVENT_TYPE_TABLE_ENTRY("node-load-misses", PERF_TYPE_HW_CACHE,
-                       ((PERF_COUNT_HW_CACHE_NODE) | (PERF_COUNT_HW_CACHE_OP_READ << 8) |
-                        (PERF_COUNT_HW_CACHE_RESULT_MISS << 16)),
-                       "", "")
-EVENT_TYPE_TABLE_ENTRY("node-stores", PERF_TYPE_HW_CACHE,
-                       ((PERF_COUNT_HW_CACHE_NODE) | (PERF_COUNT_HW_CACHE_OP_WRITE << 8) |
-                        (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16)),
-                       "", "")
-EVENT_TYPE_TABLE_ENTRY("node-store-misses", PERF_TYPE_HW_CACHE,
-                       ((PERF_COUNT_HW_CACHE_NODE) | (PERF_COUNT_HW_CACHE_OP_WRITE << 8) |
-                        (PERF_COUNT_HW_CACHE_RESULT_MISS << 16)),
-                       "", "")
-EVENT_TYPE_TABLE_ENTRY("node-prefetches", PERF_TYPE_HW_CACHE,
-                       ((PERF_COUNT_HW_CACHE_NODE) | (PERF_COUNT_HW_CACHE_OP_PREFETCH << 8) |
-                        (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16)),
-                       "", "")
-EVENT_TYPE_TABLE_ENTRY("node-prefetch-misses", PERF_TYPE_HW_CACHE,
-                       ((PERF_COUNT_HW_CACHE_NODE) | (PERF_COUNT_HW_CACHE_OP_PREFETCH << 8) |
-                        (PERF_COUNT_HW_CACHE_RESULT_MISS << 16)),
-                       "", "")
-
-EVENT_TYPE_TABLE_ENTRY(
-    "raw-sw-incr", PERF_TYPE_RAW, 0x0,
-    "Instruction architecturally executed, Condition code check pass, software increment", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l1i-cache-refill", PERF_TYPE_RAW, 0x1,
-                       "Level 1 instruction cache refill", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l1i-tlb-refill", PERF_TYPE_RAW, 0x2,
-                       "Attributable Level 1 instruction TLB refill", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l1d-cache-refill", PERF_TYPE_RAW, 0x3, "Level 1 data cache refill",
-                       "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l1d-cache", PERF_TYPE_RAW, 0x4, "Level 1 data cache access", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l1d-tlb-refill", PERF_TYPE_RAW, 0x5,
-                       "Attributable Level 1 data TLB refill", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-ld-retired", PERF_TYPE_RAW, 0x6,
-                       "Instruction architecturally executed, Condition code check pass, load",
-                       "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-st-retired", PERF_TYPE_RAW, 0x7,
-                       "Instruction architecturally executed, Condition code check pass, store",
-                       "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-inst-retired", PERF_TYPE_RAW, 0x8,
-                       "Instruction architecturally executed", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-exc-taken", PERF_TYPE_RAW, 0x9, "Exception taken", "arm")
-EVENT_TYPE_TABLE_ENTRY(
-    "raw-exc-return", PERF_TYPE_RAW, 0xa,
-    "Instruction architecturally executed, Condition code check pass, exception return", "arm")
-EVENT_TYPE_TABLE_ENTRY(
-    "raw-cid-write-retired", PERF_TYPE_RAW, 0xb,
-    "Instruction architecturally executed, Condition code check pass, write to CONTEXTIDR", "arm")
-EVENT_TYPE_TABLE_ENTRY(
-    "raw-pc-write-retired", PERF_TYPE_RAW, 0xc,
-    "Instruction architecturally executed, Condition code check pass, software change of the PC",
-    "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-br-immed-retired", PERF_TYPE_RAW, 0xd,
-                       "Instruction architecturally executed, immediate branch", "arm")
-EVENT_TYPE_TABLE_ENTRY(
-    "raw-br-return-retired", PERF_TYPE_RAW, 0xe,
-    "Instruction architecturally executed, Condition code check pass, procedure return", "arm")
-EVENT_TYPE_TABLE_ENTRY(
-    "raw-unaligned-ldst-retired", PERF_TYPE_RAW, 0xf,
-    "Instruction architecturally executed, Condition code check pass, unaligned load or store",
-    "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-br-mis-pred", PERF_TYPE_RAW, 0x10,
-                       "Mispredicted or not predicted branch Speculatively executed", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-cpu-cycles", PERF_TYPE_RAW, 0x11, "Cycle", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-br-pred", PERF_TYPE_RAW, 0x12,
-                       "Predictable branch Speculatively executed", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-mem-access", PERF_TYPE_RAW, 0x13, "Data memory access", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l1i-cache", PERF_TYPE_RAW, 0x14,
-                       "Attributable Level 1 instruction cache access", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l1d-cache-wb", PERF_TYPE_RAW, 0x15,
-                       "Attributable Level 1 data cache write-back", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l2d-cache", PERF_TYPE_RAW, 0x16, "Level 2 data cache access", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l2d-cache-refill", PERF_TYPE_RAW, 0x17, "Level 2 data cache refill",
-                       "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l2d-cache-wb", PERF_TYPE_RAW, 0x18,
-                       "Attributable Level 2 data cache write-back", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-bus-access", PERF_TYPE_RAW, 0x19, "Bus access", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-memory-error", PERF_TYPE_RAW, 0x1a, "Local memory error", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-inst-spec", PERF_TYPE_RAW, 0x1b, "Operation Speculatively executed",
-                       "arm")
-EVENT_TYPE_TABLE_ENTRY(
-    "raw-ttbr-write-retired", PERF_TYPE_RAW, 0x1c,
-    "Instruction architecturally executed, Condition code check pass, write to TTBR", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-bus-cycles", PERF_TYPE_RAW, 0x1d, "Bus cycle", "arm")
-EVENT_TYPE_TABLE_ENTRY(
-    "raw-chain", PERF_TYPE_RAW, 0x1e,
-    "For odd-numbered counters, increments the count by one for each overflow of the preceding "
-    "even-numbered counter. For even-numbered counters, there is no increment.",
-    "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l1d-cache-allocate", PERF_TYPE_RAW, 0x1f,
-                       "Attributable Level 1 data cache allocation without refill", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l2d-cache-allocate", PERF_TYPE_RAW, 0x20,
-                       "Attributable Level 2 data cache allocation without refill", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-br-retired", PERF_TYPE_RAW, 0x21,
-                       "Instruction architecturally executed, branch", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-br-mis-pred-retired", PERF_TYPE_RAW, 0x22,
-                       "Instruction architecturally executed, mispredicted branch", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-stall-frontend", PERF_TYPE_RAW, 0x23,
-                       "No operation issued due to the frontend", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-stall-backend", PERF_TYPE_RAW, 0x24,
-                       "No operation issued due to backend", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l1d-tlb", PERF_TYPE_RAW, 0x25,
-                       "Attributable Level 1 data or unified TLB access", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l1i-tlb", PERF_TYPE_RAW, 0x26,
-                       "Attributable Level 1 instruction TLB access", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l2i-cache", PERF_TYPE_RAW, 0x27,
-                       "Attributable Level 2 instruction cache access", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l2i-cache-refill", PERF_TYPE_RAW, 0x28,
-                       "Attributable Level 2 instruction cache refill", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l3d-cache-allocate", PERF_TYPE_RAW, 0x29,
-                       "Attributable Level 3 data or unified cache allocation without refill",
-                       "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l3d-cache-refill", PERF_TYPE_RAW, 0x2a,
-                       "Attributable Level 3 data cache refill", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l3d-cache", PERF_TYPE_RAW, 0x2b,
-                       "Attributable Level 3 data cache access", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l3d-cache-wb", PERF_TYPE_RAW, 0x2c,
-                       "Attributable Level 3 data or unified cache write-back", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l2d-tlb-refill", PERF_TYPE_RAW, 0x2d,
-                       "Attributable Level 2 data or unified TLB refill", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l2i-tlb-refill", PERF_TYPE_RAW, 0x2e,
-                       "Attributable Level 2 instruction TLB refill", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l2d-tlb", PERF_TYPE_RAW, 0x2f,
-                       "Attributable Level 2 data or unified TLB access", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l2i-tlb", PERF_TYPE_RAW, 0x30,
-                       "Attributable Level 2 instruction TLB access", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-remote-access", PERF_TYPE_RAW, 0x31,
-                       "Attributable access to another socket in a multi-socket system", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-ll-cache", PERF_TYPE_RAW, 0x32,
-                       "Attributable Last Level data cache access", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-ll-cache-miss", PERF_TYPE_RAW, 0x33,
-                       "Attributable Last level data or unified cache miss", "arm")
-EVENT_TYPE_TABLE_ENTRY(
-    "raw-dtlb-walk", PERF_TYPE_RAW, 0x34,
-    "Attributable data or unified TLB access with at least one translation table walk", "arm")
-EVENT_TYPE_TABLE_ENTRY(
-    "raw-itlb-walk", PERF_TYPE_RAW, 0x35,
-    "Attributable instruction TLB access with at least one translation table walk", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-ll-cache-rd", PERF_TYPE_RAW, 0x36,
-                       "Attributable Last Level cache memory read", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-ll-cache-miss-rd", PERF_TYPE_RAW, 0x37,
-                       "Attributable Last Level cache memory read miss", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-remote-access-rd", PERF_TYPE_RAW, 0x38,
-                       "Attributable memory read access to another socket in a multi-socket system",
-                       "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l1d-cache-lmiss-rd", PERF_TYPE_RAW, 0x39,
-                       "Level 1 data cache long-latency read miss", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-op-retired", PERF_TYPE_RAW, 0x3a,
-                       "Micro-operation architecturally executed", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-op-spec", PERF_TYPE_RAW, 0x3b, "Micro-operation Speculatively executed",
-                       "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-stall", PERF_TYPE_RAW, 0x3c, "No operation sent for execution", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-stall-slot-backend", PERF_TYPE_RAW, 0x3d,
-                       "No operation sent for execution on a Slot due to the backend", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-stall-slot-frontend", PERF_TYPE_RAW, 0x3e,
-                       "No operation send for execution on a Slot due to the frontend", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-stall-slot", PERF_TYPE_RAW, 0x3f,
-                       "No operation sent for execution on a Slot", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l1d-cache-rd", PERF_TYPE_RAW, 0x40, "Level 1 data cache read", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-sample-pop", PERF_TYPE_RAW, 0x4000, "Sample Population", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-sample-feed", PERF_TYPE_RAW, 0x4001, "Sample Taken", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-sample-filtrate", PERF_TYPE_RAW, 0x4002,
-                       "Sample Taken and not removed by filtering", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-sample-collision", PERF_TYPE_RAW, 0x4003,
-                       "Sample collided with previous sample", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-cnt-cycles", PERF_TYPE_RAW, 0x4004, "Constant frequency cycles", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-stall-backend-mem", PERF_TYPE_RAW, 0x4005, "Memory stall cycles", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l1i-cache-lmiss", PERF_TYPE_RAW, 0x4006,
-                       "Level 1 instruction cache long-latency miss", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l2d-cache-lmiss-rd", PERF_TYPE_RAW, 0x4009,
-                       "Level 2 data cache long-latency read miss", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l2i-cache-lmiss", PERF_TYPE_RAW, 0x400a,
-                       "Level 2 instruction cache long-latency miss", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l3d-cache-lmiss-rd", PERF_TYPE_RAW, 0x400b,
-                       "Level 3 data cache long-latency read miss", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-sve-inst-retired", PERF_TYPE_RAW, 0x8002,
-                       "SVE Instructions architecturally executed", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-sve-inst-spec", PERF_TYPE_RAW, 0x8006,
-                       "SVE Instructions speculatively executed", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l1d-cache-wr", PERF_TYPE_RAW, 0x41,
-                       "Attributable Level 1 data cache access, write", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l1d-cache-refill-rd", PERF_TYPE_RAW, 0x42,
-                       "Attributable Level 1 data cache refill, read", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l1d-cache-refill-wr", PERF_TYPE_RAW, 0x43,
-                       "Attributable Level 1 data cache refill, write", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l1d-cache-refill-inner", PERF_TYPE_RAW, 0x44,
-                       "Attributable Level 1 data cache refill, inner", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l1d-cache-refill-outer", PERF_TYPE_RAW, 0x45,
-                       "Attributable Level 1 data cache refill, outer", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l1d-cache-wb-victim", PERF_TYPE_RAW, 0x46,
-                       "Attributable Level 1 data cache Write-Back, victim", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l1d-cache-wb-clean", PERF_TYPE_RAW, 0x47,
-                       "Level 1 data cache Write-Back, cleaning and coherency", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l1d-cache-inval", PERF_TYPE_RAW, 0x48,
-                       "Attributable Level 1 data cache invalidate", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l1d-tlb-refill-rd", PERF_TYPE_RAW, 0x4c,
-                       "Attributable Level 1 data TLB refill, read", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l1d-tlb-refill-wr", PERF_TYPE_RAW, 0x4d,
-                       "Attributable Level 1 data TLB refill, write", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l1d-tlb-rd", PERF_TYPE_RAW, 0x4e,
-                       "Attributable Level 1 data or unified TLB access, read", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l1d-tlb-wr", PERF_TYPE_RAW, 0x4f,
-                       "Attributable Level 1 data or unified TLB access, write", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l2d-cache-rd", PERF_TYPE_RAW, 0x50,
-                       "Attributable Level 2 data cache access, read", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l2d-cache-wr", PERF_TYPE_RAW, 0x51,
-                       "Attributable Level 2 data cache access, write", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l2d-cache-refill-rd", PERF_TYPE_RAW, 0x52,
-                       "Attributable Level 2 data cache refill, read", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l2d-cache-refill-wr", PERF_TYPE_RAW, 0x53,
-                       "Attributable Level 2 data cache refill, write", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l2d-cache-wb-victim", PERF_TYPE_RAW, 0x56,
-                       "Attributable Level 2 data cache Write-Back, victim", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l2d-cache-wb-clean", PERF_TYPE_RAW, 0x57,
-                       "Level 2 data cache Write-Back, cleaning and coherency", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l2d-cache-inval", PERF_TYPE_RAW, 0x58,
-                       "Attributable Level 2 data cache invalidate", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l2d-tlb-refill-rd", PERF_TYPE_RAW, 0x5c,
-                       "Attributable Level 2 data or unified TLB refill, read", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l2d-tlb-refill-wr", PERF_TYPE_RAW, 0x5d,
-                       "Attributable Level 2 data or unified TLB refill, write", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l2d-tlb-rd", PERF_TYPE_RAW, 0x5e,
-                       "Attributable Level 2 data or unified TLB access, read", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l2d-tlb-wr", PERF_TYPE_RAW, 0x5f,
-                       "Attributable Level 2 data or unified TLB access, write", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-bus-access-rd", PERF_TYPE_RAW, 0x60, "Bus access, read", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-bus-access-wr", PERF_TYPE_RAW, 0x61, "Bus access, write", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-bus-access-shared", PERF_TYPE_RAW, 0x62,
-                       "Bus access, Normal, Cacheable, Shareable", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-bus-access-not-shared", PERF_TYPE_RAW, 0x63,
-                       "Bus access, not Normal, Cacheable, Shareable", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-bus-access-normal", PERF_TYPE_RAW, 0x64, "Bus access, normal", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-bus-access-periph", PERF_TYPE_RAW, 0x65, "Bus access, peripheral",
-                       "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-mem-access-rd", PERF_TYPE_RAW, 0x66, "Data memory access, read", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-mem-access-wr", PERF_TYPE_RAW, 0x67, "Data memory access, write", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-unaligned-ld-spec", PERF_TYPE_RAW, 0x68, "Unaligned access, read",
-                       "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-unaligned-st-spec", PERF_TYPE_RAW, 0x69, "Unaligned access, write",
-                       "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-unaligned-ldst-spec", PERF_TYPE_RAW, 0x6a, "Unaligned access", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-ldrex-spec", PERF_TYPE_RAW, 0x6c,
-                       "Exclusive operation speculatively executed, LDREX or LDX", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-strex-pass-spec", PERF_TYPE_RAW, 0x6d,
-                       "Exclusive operation speculatively executed, STREX or STX pass", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-strex-fail-spec", PERF_TYPE_RAW, 0x6e,
-                       "Exclusive operation speculatively executed, STREX or STX fail", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-strex-spec", PERF_TYPE_RAW, 0x6f,
-                       "Exclusive operation speculatively executed, STREX or STX", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-ld-spec", PERF_TYPE_RAW, 0x70, "Operation speculatively executed, load",
-                       "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-st-spec", PERF_TYPE_RAW, 0x71,
-                       "Operation speculatively executed, store", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-ldst-spec", PERF_TYPE_RAW, 0x72,
-                       "Operation speculatively executed, load or store", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-dp-spec", PERF_TYPE_RAW, 0x73,
-                       "Operation speculatively executed, integer data processing", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-ase-spec", PERF_TYPE_RAW, 0x74,
-                       "Operation speculatively executed, Advanced SIMD instruction", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-vfp-spec", PERF_TYPE_RAW, 0x75,
-                       "Operation speculatively executed, floating-point instruction", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-pc-write-spec", PERF_TYPE_RAW, 0x76,
-                       "Operation speculatively executed, software change of the PC", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-crypto-spec", PERF_TYPE_RAW, 0x77,
-                       "Operation speculatively executed, Cryptographic instruction", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-br-immed-spec", PERF_TYPE_RAW, 0x78,
-                       "Branch speculatively executed, immediate branch", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-br-return-spec", PERF_TYPE_RAW, 0x79,
-                       "Branch speculatively executed, procedure return", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-br-indirect-spec", PERF_TYPE_RAW, 0x7a,
-                       "Branch speculatively executed, indirect branch", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-isb-spec", PERF_TYPE_RAW, 0x7c, "Barrier speculatively executed, ISB",
-                       "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-dsb-spec", PERF_TYPE_RAW, 0x7d, "Barrier speculatively executed, DSB",
-                       "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-dmb-spec", PERF_TYPE_RAW, 0x7e, "Barrier speculatively executed, DMB",
-                       "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-exc-undef", PERF_TYPE_RAW, 0x81, "Exception taken, Other synchronous",
-                       "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-exc-svc", PERF_TYPE_RAW, 0x82, "Exception taken, Supervisor Call",
-                       "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-exc-pabort", PERF_TYPE_RAW, 0x83, "Exception taken, Instruction Abort",
-                       "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-exc-dabort", PERF_TYPE_RAW, 0x84,
-                       "Exception taken, Data Abort and SError", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-exc-irq", PERF_TYPE_RAW, 0x86, "Exception taken, IRQ", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-exc-fiq", PERF_TYPE_RAW, 0x87, "Exception taken, FIQ", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-exc-smc", PERF_TYPE_RAW, 0x88, "Exception taken, Secure Monitor Call",
-                       "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-exc-hvc", PERF_TYPE_RAW, 0x8a, "Exception taken, Hypervisor Call",
-                       "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-exc-trap-pabort", PERF_TYPE_RAW, 0x8b,
-                       "Exception taken, Instruction Abort not Taken locallyb", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-exc-trap-dabort", PERF_TYPE_RAW, 0x8c,
-                       "Exception taken, Data Abort or SError not Taken locallyb", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-exc-trap-other", PERF_TYPE_RAW, 0x8d,
-                       "Exception taken, Other traps not Taken locallyb", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-exc-trap-irq", PERF_TYPE_RAW, 0x8e,
-                       "Exception taken, IRQ not Taken locallyb", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-exc-trap-fiq", PERF_TYPE_RAW, 0x8f,
-                       "Exception taken, FIQ not Taken locallyb", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-rc-ld-spec", PERF_TYPE_RAW, 0x90,
-                       "Release consistency operation speculatively executed, Load-Acquire", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-rc-st-spec", PERF_TYPE_RAW, 0x91,
-                       "Release consistency operation speculatively executed, Store-Release", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l3d-cache-rd", PERF_TYPE_RAW, 0xa0,
-                       "Attributable Level 3 data or unified cache access, read", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l3d-cache-wr", PERF_TYPE_RAW, 0xa1,
-                       "Attributable Level 3 data or unified cache access, write", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l3d-cache-refill-rd", PERF_TYPE_RAW, 0xa2,
-                       "Attributable Level 3 data or unified cache refill, read", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l3d-cache-refill-wr", PERF_TYPE_RAW, 0xa3,
-                       "Attributable Level 3 data or unified cache refill, write", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l3d-cache-wb-victim", PERF_TYPE_RAW, 0xa6,
-                       "Attributable Level 3 data or unified cache Write-Back, victim", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l3d-cache-wb-clean", PERF_TYPE_RAW, 0xa7,
-                       "Attributable Level 3 data or unified cache Write-Back, cache clean", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l3d-cache-inval", PERF_TYPE_RAW, 0xa8,
-                       "Attributable Level 3 data or unified cache access, invalidate", "arm")
diff --git a/simpleperf/generate_event_type_table.py b/simpleperf/generate_event_type_table.py
deleted file mode 100755
index 8588e317..00000000
--- a/simpleperf/generate_event_type_table.py
+++ /dev/null
@@ -1,305 +0,0 @@
-#!/usr/bin/python
-#
-# Copyright (C) 2015 The Android Open Source Project
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#      http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-
-
-def gen_event_type_entry_str(event_type_name, event_type, event_config, description='',
-                             limited_arch=''):
-  """
-  return string as below:
-  EVENT_TYPE_TABLE_ENTRY(event_type_name, event_type, event_config, description, limited_arch)
-  """
-  return 'EVENT_TYPE_TABLE_ENTRY("%s", %s, %s, "%s", "%s")\n' % (
-            event_type_name, event_type, event_config, description, limited_arch)
-
-def gen_arm_event_type_entry_str(event_type_name, event_type, event_config, description):
-  return gen_event_type_entry_str(event_type_name, event_type, event_config, description,
-                                  "arm")
-
-
-def gen_hardware_events():
-  hardware_configs = ["cpu-cycles",
-                      "instructions",
-                      "cache-references",
-                      "cache-misses",
-                      "branch-instructions",
-                      "branch-misses",
-                      "bus-cycles",
-                      "stalled-cycles-frontend",
-                      "stalled-cycles-backend",
-                      ]
-  generated_str = ""
-  for config in hardware_configs:
-    event_type_name = config
-    event_config = "PERF_COUNT_HW_" + config.replace('-', '_').upper()
-
-    generated_str += gen_event_type_entry_str(
-        event_type_name, "PERF_TYPE_HARDWARE", event_config)
-
-  return generated_str
-
-
-def gen_software_events():
-  software_configs = ["cpu-clock",
-                      "task-clock",
-                      "page-faults",
-                      "context-switches",
-                      "cpu-migrations",
-                      ["minor-faults", "PERF_COUNT_SW_PAGE_FAULTS_MIN"],
-                      ["major-faults", "PERF_COUNT_SW_PAGE_FAULTS_MAJ"],
-                      "alignment-faults",
-                      "emulation-faults",
-                      ]
-  generated_str = ""
-  for config in software_configs:
-    if isinstance(config, list):
-      event_type_name = config[0]
-      event_config = config[1]
-    else:
-      event_type_name = config
-      event_config = "PERF_COUNT_SW_" + config.replace('-', '_').upper()
-
-    generated_str += gen_event_type_entry_str(
-        event_type_name, "PERF_TYPE_SOFTWARE", event_config)
-
-  return generated_str
-
-
-def gen_hw_cache_events():
-  hw_cache_types = [["L1-dcache", "PERF_COUNT_HW_CACHE_L1D"],
-                    ["L1-icache", "PERF_COUNT_HW_CACHE_L1I"],
-                    ["LLC", "PERF_COUNT_HW_CACHE_LL"],
-                    ["dTLB", "PERF_COUNT_HW_CACHE_DTLB"],
-                    ["iTLB", "PERF_COUNT_HW_CACHE_ITLB"],
-                    ["branch", "PERF_COUNT_HW_CACHE_BPU"],
-                    ["node", "PERF_COUNT_HW_CACHE_NODE"],
-                    ]
-  hw_cache_ops = [["loads", "load", "PERF_COUNT_HW_CACHE_OP_READ"],
-                  ["stores", "store", "PERF_COUNT_HW_CACHE_OP_WRITE"],
-                  ["prefetches", "prefetch",
-                   "PERF_COUNT_HW_CACHE_OP_PREFETCH"],
-                  ]
-  hw_cache_op_results = [["accesses", "PERF_COUNT_HW_CACHE_RESULT_ACCESS"],
-                         ["misses", "PERF_COUNT_HW_CACHE_RESULT_MISS"],
-                         ]
-  generated_str = ""
-  for (type_name, type_config) in hw_cache_types:
-    for (op_name_access, op_name_miss, op_config) in hw_cache_ops:
-      for (result_name, result_config) in hw_cache_op_results:
-        if result_name == "accesses":
-          event_type_name = type_name + '-' + op_name_access
-        else:
-          event_type_name = type_name + '-' + \
-              op_name_miss + '-' + result_name
-        event_config = "((%s) | (%s << 8) | (%s << 16))" % (
-            type_config, op_config, result_config)
-        generated_str += gen_event_type_entry_str(
-            event_type_name, "PERF_TYPE_HW_CACHE", event_config)
-
-  return generated_str
-
-
-def gen_arm_raw_events():
-  raw_types = [
-               # Refer to "Table D6-7 PMU common architectural and microarchitectural event numbers" in ARMv8 specification.
-               [0x0000, "sw-incr", "Instruction architecturally executed, Condition code check pass, software increment"],
-               [0x0001, "l1i-cache-refill", "Level 1 instruction cache refill"],
-               [0x0002, "l1i-tlb-refill", "Attributable Level 1 instruction TLB refill"],
-               [0x0003, "l1d-cache-refill", "Level 1 data cache refill"],
-               [0x0004, "l1d-cache", "Level 1 data cache access"],
-               [0x0005, "l1d-tlb-refill", "Attributable Level 1 data TLB refill"],
-               [0x0006, "ld-retired", "Instruction architecturally executed, Condition code check pass, load"],
-               [0x0007, "st-retired", "Instruction architecturally executed, Condition code check pass, store"],
-               [0x0008, "inst-retired", "Instruction architecturally executed"],
-               [0x0009, "exc-taken", "Exception taken"],
-               [0x000A, "exc-return", "Instruction architecturally executed, Condition code check pass, exception return"],
-               [0x000B, "cid-write-retired", "Instruction architecturally executed, Condition code check pass, write to CONTEXTIDR"],
-               [0x000C, "pc-write-retired", "Instruction architecturally executed, Condition code check pass, software change of the PC"],
-               [0x000D, "br-immed-retired", "Instruction architecturally executed, immediate branch"],
-               [0x000E, "br-return-retired", "Instruction architecturally executed, Condition code check pass, procedure return"],
-               [0x000F, "unaligned-ldst-retired", "Instruction architecturally executed, Condition code check pass, unaligned load or store"],
-               [0x0010, "br-mis-pred", "Mispredicted or not predicted branch Speculatively executed"],
-               [0x0011, "cpu-cycles", "Cycle"],
-               [0x0012, "br-pred", "Predictable branch Speculatively executed"],
-               [0x0013, "mem-access", "Data memory access"],
-               [0x0014, "l1i-cache", "Attributable Level 1 instruction cache access"],
-               [0x0015, "l1d-cache-wb", "Attributable Level 1 data cache write-back"],
-               [0x0016, "l2d-cache", "Level 2 data cache access"],
-               [0x0017, "l2d-cache-refill", "Level 2 data cache refill"],
-               [0x0018, "l2d-cache-wb", "Attributable Level 2 data cache write-back"],
-               [0x0019, "bus-access", "Bus access"],
-               [0x001A, "memory-error", "Local memory error"],
-               [0x001B, "inst-spec", "Operation Speculatively executed"],
-               [0x001C, "ttbr-write-retired", "Instruction architecturally executed, Condition code check pass, write to TTBR"],
-               [0x001D, "bus-cycles", "Bus cycle"],
-               [0x001E, "chain", "For odd-numbered counters, increments the count by one for each overflow of the preceding even-numbered counter. For even-numbered counters, there is no increment."],
-               [0x001F, "l1d-cache-allocate", "Attributable Level 1 data cache allocation without refill"],
-               [0x0020, "l2d-cache-allocate", "Attributable Level 2 data cache allocation without refill"],
-               [0x0021, "br-retired", "Instruction architecturally executed, branch"],
-               [0x0022, "br-mis-pred-retired", "Instruction architecturally executed, mispredicted branch"],
-               [0x0023, "stall-frontend", "No operation issued due to the frontend"],
-               [0x0024, "stall-backend", "No operation issued due to backend"],
-               [0x0025, "l1d-tlb", "Attributable Level 1 data or unified TLB access"],
-               [0x0026, "l1i-tlb", "Attributable Level 1 instruction TLB access"],
-               [0x0027, "l2i-cache", "Attributable Level 2 instruction cache access"],
-               [0x0028, "l2i-cache-refill", "Attributable Level 2 instruction cache refill"],
-               [0x0029, "l3d-cache-allocate", "Attributable Level 3 data or unified cache allocation without refill"],
-               [0x002A, "l3d-cache-refill", "Attributable Level 3 data cache refill"],
-               [0x002B, "l3d-cache", "Attributable Level 3 data cache access"],
-               [0x002C, "l3d-cache-wb", "Attributable Level 3 data or unified cache write-back"],
-               [0x002D, "l2d-tlb-refill", "Attributable Level 2 data or unified TLB refill"],
-               [0x002E, "l2i-tlb-refill", "Attributable Level 2 instruction TLB refill"],
-               [0x002F, "l2d-tlb", "Attributable Level 2 data or unified TLB access"],
-               [0x0030, "l2i-tlb", "Attributable Level 2 instruction TLB access"],
-               [0x0031, "remote-access", "Attributable access to another socket in a multi-socket system"],
-               [0x0032, "ll-cache", "Attributable Last Level data cache access"],
-               [0x0033, "ll-cache-miss", "Attributable Last level data or unified cache miss"],
-               [0x0034, "dtlb-walk", "Attributable data or unified TLB access with at least one translation table walk"],
-               [0x0035, "itlb-walk", "Attributable instruction TLB access with at least one translation table walk"],
-               [0x0036, "ll-cache-rd", "Attributable Last Level cache memory read"],
-               [0x0037, "ll-cache-miss-rd", "Attributable Last Level cache memory read miss"],
-               [0x0038, "remote-access-rd", "Attributable memory read access to another socket in a multi-socket system"],
-               [0x0039, "l1d-cache-lmiss-rd", "Level 1 data cache long-latency read miss"],
-               [0x003A, "op-retired", "Micro-operation architecturally executed"],
-               [0x003B, "op-spec", "Micro-operation Speculatively executed"],
-               [0x003C, "stall", "No operation sent for execution"],
-               [0x003D, "stall-slot-backend", "No operation sent for execution on a Slot due to the backend"],
-               [0x003E, "stall-slot-frontend", "No operation send for execution on a Slot due to the frontend"],
-               [0x003F, "stall-slot", "No operation sent for execution on a Slot"],
-               [0x0040, "l1d-cache-rd", "Level 1 data cache read"],
-               [0x4000, "sample-pop", "Sample Population"],
-               [0x4001, "sample-feed", "Sample Taken"],
-               [0x4002, "sample-filtrate", "Sample Taken and not removed by filtering"],
-               [0x4003, "sample-collision", "Sample collided with previous sample"],
-               [0x4004, "cnt-cycles", "Constant frequency cycles"],
-               [0x4005, "stall-backend-mem", "Memory stall cycles"],
-               [0x4006, "l1i-cache-lmiss", "Level 1 instruction cache long-latency miss"],
-               [0x4009, "l2d-cache-lmiss-rd", "Level 2 data cache long-latency read miss"],
-               [0x400A, "l2i-cache-lmiss", "Level 2 instruction cache long-latency miss"],
-               [0x400B, "l3d-cache-lmiss-rd", "Level 3 data cache long-latency read miss"],
-               [0x8002, "sve-inst-retired", "SVE Instructions architecturally executed"],
-               [0x8006, "sve-inst-spec", "SVE Instructions speculatively executed"],
-
-               # Refer to "Table K3.1 ARM recommendations for IMPLEMENTATION DEFINED event numbers" in ARMv8 specification.
-               #[0x0040, "l1d-cache-rd", "Attributable Level 1 data cache access, read"],
-               [0x0041, "l1d-cache-wr", "Attributable Level 1 data cache access, write"],
-               [0x0042, "l1d-cache-refill-rd", "Attributable Level 1 data cache refill, read"],
-               [0x0043, "l1d-cache-refill-wr", "Attributable Level 1 data cache refill, write"],
-               [0x0044, "l1d-cache-refill-inner", "Attributable Level 1 data cache refill, inner"],
-               [0x0045, "l1d-cache-refill-outer", "Attributable Level 1 data cache refill, outer"],
-               [0x0046, "l1d-cache-wb-victim", "Attributable Level 1 data cache Write-Back, victim"],
-               [0x0047, "l1d-cache-wb-clean", "Level 1 data cache Write-Back, cleaning and coherency"],
-               [0x0048, "l1d-cache-inval", "Attributable Level 1 data cache invalidate"],
-               # 0x0049-0x004B - Reserved
-               [0x004C, "l1d-tlb-refill-rd", "Attributable Level 1 data TLB refill, read"],
-               [0x004D, "l1d-tlb-refill-wr", "Attributable Level 1 data TLB refill, write"],
-               [0x004E, "l1d-tlb-rd", "Attributable Level 1 data or unified TLB access, read"],
-               [0x004F, "l1d-tlb-wr", "Attributable Level 1 data or unified TLB access, write"],
-               [0x0050, "l2d-cache-rd", "Attributable Level 2 data cache access, read"],
-               [0x0051, "l2d-cache-wr", "Attributable Level 2 data cache access, write"],
-               [0x0052, "l2d-cache-refill-rd", "Attributable Level 2 data cache refill, read"],
-               [0x0053, "l2d-cache-refill-wr", "Attributable Level 2 data cache refill, write"],
-               # 0x0054-0x0055 - Reserved
-               [0x0056, "l2d-cache-wb-victim", "Attributable Level 2 data cache Write-Back, victim"],
-               [0x0057, "l2d-cache-wb-clean", "Level 2 data cache Write-Back, cleaning and coherency"],
-               [0x0058, "l2d-cache-inval", "Attributable Level 2 data cache invalidate"],
-               # 0x0059-0x005B - Reserved
-               [0x005C, "l2d-tlb-refill-rd", "Attributable Level 2 data or unified TLB refill, read"],
-               [0x005D, "l2d-tlb-refill-wr", "Attributable Level 2 data or unified TLB refill, write"],
-               [0x005E, "l2d-tlb-rd", "Attributable Level 2 data or unified TLB access, read"],
-               [0x005F, "l2d-tlb-wr", "Attributable Level 2 data or unified TLB access, write"],
-               [0x0060, "bus-access-rd", "Bus access, read"],
-               [0x0061, "bus-access-wr", "Bus access, write"],
-               [0x0062, "bus-access-shared", "Bus access, Normal, Cacheable, Shareable"],
-               [0x0063, "bus-access-not-shared", "Bus access, not Normal, Cacheable, Shareable"],
-               [0x0064, "bus-access-normal", "Bus access, normal"],
-               [0x0065, "bus-access-periph", "Bus access, peripheral"],
-               [0x0066, "mem-access-rd", "Data memory access, read"],
-               [0x0067, "mem-access-wr", "Data memory access, write"],
-               [0x0068, "unaligned-ld-spec", "Unaligned access, read"],
-               [0x0069, "unaligned-st-spec", "Unaligned access, write"],
-               [0x006A, "unaligned-ldst-spec", "Unaligned access"],
-               # 0x006B - Reserved
-               [0x006C, "ldrex-spec", "Exclusive operation speculatively executed, LDREX or LDX"],
-               [0x006D, "strex-pass-spec", "Exclusive operation speculatively executed, STREX or STX pass"],
-               [0x006E, "strex-fail-spec", "Exclusive operation speculatively executed, STREX or STX fail"],
-               [0x006F, "strex-spec", "Exclusive operation speculatively executed, STREX or STX"],
-               [0x0070, "ld-spec", "Operation speculatively executed, load"],
-               [0x0071, "st-spec", "Operation speculatively executed, store"],
-               [0x0072, "ldst-spec", "Operation speculatively executed, load or store"],
-               [0x0073, "dp-spec", "Operation speculatively executed, integer data processing"],
-               [0x0074, "ase-spec", "Operation speculatively executed, Advanced SIMD instruction"],
-               [0x0075, "vfp-spec", "Operation speculatively executed, floating-point instruction"],
-               [0x0076, "pc-write-spec", "Operation speculatively executed, software change of the PC"],
-               [0x0077, "crypto-spec", "Operation speculatively executed, Cryptographic instruction"],
-               [0x0078, "br-immed-spec", "Branch speculatively executed, immediate branch"],
-               [0x0079, "br-return-spec", "Branch speculatively executed, procedure return"],
-               [0x007A, "br-indirect-spec", "Branch speculatively executed, indirect branch"],
-               # 0x007B - Reserved
-               [0x007C, "isb-spec", "Barrier speculatively executed, ISB"],
-               [0x007D, "dsb-spec", "Barrier speculatively executed, DSB"],
-               [0x007E, "dmb-spec", "Barrier speculatively executed, DMB"],
-               # 0x007F-0x0080 - Reserved
-               [0x0081, "exc-undef", "Exception taken, Other synchronous"],
-               [0x0082, "exc-svc", "Exception taken, Supervisor Call"],
-               [0x0083, "exc-pabort", "Exception taken, Instruction Abort"],
-               [0x0084, "exc-dabort", "Exception taken, Data Abort and SError"],
-               # 0x0085 - Reserved
-               [0x0086, "exc-irq", "Exception taken, IRQ"],
-               [0x0087, "exc-fiq", "Exception taken, FIQ"],
-               [0x0088, "exc-smc", "Exception taken, Secure Monitor Call"],
-               # 0x0089 - Reserved
-               [0x008A, "exc-hvc", "Exception taken, Hypervisor Call"],
-               [0x008B, "exc-trap-pabort", "Exception taken, Instruction Abort not Taken locallyb"],
-               [0x008C, "exc-trap-dabort", "Exception taken, Data Abort or SError not Taken locallyb"],
-               [0x008D, "exc-trap-other", "Exception taken, Other traps not Taken locallyb"],
-               [0x008E, "exc-trap-irq", "Exception taken, IRQ not Taken locallyb"],
-               [0x008F, "exc-trap-fiq", "Exception taken, FIQ not Taken locallyb"],
-               [0x0090, "rc-ld-spec", "Release consistency operation speculatively executed, Load-Acquire"],
-               [0x0091, "rc-st-spec", "Release consistency operation speculatively executed, Store-Release"],
-               # 0x0092-0x009F - Reserved
-               [0x00A0, "l3d-cache-rd", "Attributable Level 3 data or unified cache access, read"],
-               [0x00A1, "l3d-cache-wr", "Attributable Level 3 data or unified cache access, write"],
-               [0x00A2, "l3d-cache-refill-rd", "Attributable Level 3 data or unified cache refill, read"],
-               [0x00A3, "l3d-cache-refill-wr", "Attributable Level 3 data or unified cache refill, write"],
-               # 0x00A4-0x00A5 - Reserved
-               [0x00A6, "l3d-cache-wb-victim", "Attributable Level 3 data or unified cache Write-Back, victim"],
-               [0x00A7, "l3d-cache-wb-clean", "Attributable Level 3 data or unified cache Write-Back, cache clean"],
-               [0x00A8, "l3d-cache-inval", "Attributable Level 3 data or unified cache access, invalidate"],
-               ]
-  generated_str = ""
-  for item in raw_types:
-    event_type = 'PERF_TYPE_RAW'
-    event_type_name = "raw-" + item[1]
-    event_config = '0x%x' % item[0]
-    description = item[2]
-    generated_str += gen_arm_event_type_entry_str(event_type_name, event_type, event_config,
-                                              description)
-  return generated_str
-
-
-def gen_events():
-  generated_str = "// This file is auto-generated by generate-event_table.py.\n\n"
-  generated_str += gen_hardware_events() + '\n'
-  generated_str += gen_software_events() + '\n'
-  generated_str += gen_hw_cache_events() + '\n'
-  generated_str += gen_arm_raw_events() + '\n'
-  return generated_str
-
-generated_str = gen_events()
-fh = open('event_type_table.h', 'w')
-fh.write(generated_str)
-fh.close()