Update Yasm to 1.2.0 (Yasm Part 1/3)

This change updates our copy of Yasm to 1.2.0. (This change mainly consists of the files used by Chromium.) BUG=156030 TEST=build Chromium Review URL: https://codereview.chromium.org/11364046 git-svn-id: http://src.chromium.org/svn/trunk/deps/third_party/yasm/patched-yasm@167603 4ff67af0-8c30-449e-8e8b-ad334ec8d88c
author: hbono@chromium.org <hbono@chromium.org@4ff67af0-8c30-449e-8e8b-ad334ec8d88c> 2012-11-14 05:26:34 +0000
committer: hbono@chromium.org <hbono@chromium.org@4ff67af0-8c30-449e-8e8b-ad334ec8d88c> 2012-11-14 05:26:34 +0000
commit: d65182f1818d1c19e6f3866ab6e68a262fad5185 (patch)
tree: 641f34f2ec8c652a523034a533dc6c57e7ef853b
parent: 6b5f1af666c0fad6e4282d07267ff5ae84e7df9d (diff)
download: patched-yasm-d65182f1818d1c19e6f3866ab6e68a262fad5185.tar.gz
134 files changed, 3117 insertions, 1822 deletions
diff --git a/frontends/tasm/tasm-options.c b/frontends/tasm/tasm-options.c
index 2f8f46d..7c23c46 100644
--- a/frontends/tasm/tasm-options.c
+++ b/frontends/tasm/tasm-options.c
@@ -29,7 +29,6 @@
  */
 #include <util.h>
 #include <ctype.h>
-/*@unused@*/ RCSID("$Id: tasm-options.c 1197 2005-01-24 06:44:25Z peter $");
 
 #include "tasm-options.h"
 
diff --git a/frontends/tasm/tasm-options.h b/frontends/tasm/tasm-options.h
index 6f2e741..082409f 100644
--- a/frontends/tasm/tasm-options.h
+++ b/frontends/tasm/tasm-options.h
@@ -1,4 +1,4 @@
-/* $Id: tasm-options.h 1137 2004-09-04 01:24:57Z peter $
+/*
  * Generic Options Support Header File
  *
  * Copyright (c) 2001  Stanislav Karchebny <berk@madfire.net>
diff --git a/frontends/tasm/tasm.c b/frontends/tasm/tasm.c
index 400e1ba..b0b89de 100644
--- a/frontends/tasm/tasm.c
+++ b/frontends/tasm/tasm.c
@@ -26,7 +26,6 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include <util.h>
-/*@unused@*/ RCSID("$Id: tasm.c 1523 2006-05-06 16:11:56Z peter $");
 
 #include <ctype.h>
 #include <libyasm/compat-queue.h>
@@ -224,7 +223,7 @@ static opt_option options[] =
 
 /* version message */
 /*@observer@*/ static const char *version_msg[] = {
-    PACKAGE_NAME " " PACKAGE_INTVER "." PACKAGE_BUILD,
+    PACKAGE_STRING,
     "Compiled on " __DATE__ ".",
     "Copyright (c) 2001-2010 Peter Johnson and other Yasm developers.",
     "Run yasm --license for licensing overview and summary."
diff --git a/frontends/yasm/yasm-options.c b/frontends/yasm/yasm-options.c
index b018953..eff6ba9 100644
--- a/frontends/yasm/yasm-options.c
+++ b/frontends/yasm/yasm-options.c
@@ -29,7 +29,6 @@
  */
 #include <util.h>
 #include <ctype.h>
-/*@unused@*/ RCSID("$Id: yasm-options.c 2248 2009-12-26 04:41:21Z peter $");
 
 #include "yasm-options.h"
 
diff --git a/frontends/yasm/yasm-options.h b/frontends/yasm/yasm-options.h
index 336b843..63c4fbe 100644
--- a/frontends/yasm/yasm-options.h
+++ b/frontends/yasm/yasm-options.h
@@ -1,4 +1,4 @@
-/* $Id: yasm-options.h 1825 2007-04-22 03:32:46Z peter $
+/*
  * Generic Options Support Header File
  *
  * Copyright (c) 2001  Stanislav Karchebny <berk@madfire.net>
diff --git a/frontends/yasm/yasm.c b/frontends/yasm/yasm.c
index bd00db8..ddd044b 100644
--- a/frontends/yasm/yasm.c
+++ b/frontends/yasm/yasm.c
@@ -25,7 +25,6 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include <util.h>
-/*@unused@*/ RCSID("$Id: yasm.c 2317 2010-04-08 06:10:16Z peter $");
 
 #include <ctype.h>
 #include <libyasm/compat-queue.h>
@@ -213,9 +212,9 @@ static opt_option options[] =
 
 /* version message */
 /*@observer@*/ static const char *version_msg[] = {
-    PACKAGE_NAME " " PACKAGE_INTVER "." PACKAGE_BUILD,
+    PACKAGE_STRING,
     "Compiled on " __DATE__ ".",
-    "Copyright (c) 2001-2010 Peter Johnson and other Yasm developers.",
+    "Copyright (c) 2001-2011 Peter Johnson and other Yasm developers.",
     "Run yasm --license for licensing overview and summary."
 };
 
diff --git a/frontends/yasm/yasm.xml b/frontends/yasm/yasm.xml
index 929ee0a..0f07462 100644
--- a/frontends/yasm/yasm.xml
+++ b/frontends/yasm/yasm.xml
@@ -2,8 +2,6 @@
 <!DOCTYPE refentry PUBLIC "-//OASIS//DTD DocBook XML V4.1.2//EN"
           "http://www.oasis-open.org/docbook/xml/4.1.2/docbookx.dtd">
 
-<!-- $Id: yasm.xml 1822 2007-04-14 19:55:45Z peter $ -->     
-
 <refentry id="yasm">
 
  <refentryinfo>
@@ -172,16 +170,6 @@
     </varlistentry>
 
     <varlistentry>
-     <term><option>-h</option> or <option>--help</option>: Print a
-      summary of options</term>
-
-     <listitem>
-      <para>Prints a summary of invocation options.  All other options
-       are ignored, and no output file is generated.</para>
-     </listitem>
-    </varlistentry>
-
-    <varlistentry>
      <term><option>-L <replaceable>list</replaceable></option> or
       <option>--lformat=<replaceable>list</replaceable></option>:
       Select list file format</term>
@@ -290,6 +278,16 @@
     </varlistentry>
 
     <varlistentry>
+     <term><option>-h</option> or <option>--help</option>: Print a
+      summary of options</term>
+
+     <listitem>
+      <para>Prints a summary of invocation options.  All other options
+       are ignored, and no output file is generated.</para>
+     </listitem>
+    </varlistentry>
+
+    <varlistentry>
      <term><option>--version</option>: Get the Yasm version</term>
 
      <listitem>
diff --git a/genstring.c b/genstring.c
index 11fad3c..a66e2f5 100644
--- a/genstring.c
+++ b/genstring.c
@@ -1,4 +1,4 @@
-/* $Id: genstring.c 1827 2007-04-22 05:09:49Z peter $
+/*
  *
  * Generate array-of-const-string from text file.
  *
diff --git a/libyasm.h b/libyasm.h
index b3c4927..f52c133 100644
--- a/libyasm.h
+++ b/libyasm.h
@@ -2,10 +2,6 @@
  * \file libyasm.h
  * \brief YASM library primary header file.
  *
- * \rcs
- * $Id: libyasm.h 1895 2007-07-14 05:31:08Z peter $
- * \endrcs
- *
  * \license
  *  Copyright (C) 2003-2007  Peter Johnson
  *
diff --git a/libyasm/Makefile.inc b/libyasm/Makefile.inc
index c7a556d..042dd39 100644
--- a/libyasm/Makefile.inc
+++ b/libyasm/Makefile.inc
@@ -1,5 +1,3 @@
-# $Id: Makefile.inc 2111 2008-07-06 22:26:49Z peter $
-
 libyasm_a_SOURCES += libyasm/assocdat.c
 libyasm_a_SOURCES += libyasm/bitvect.c
 libyasm_a_SOURCES += libyasm/bc-align.c
diff --git a/libyasm/arch.h b/libyasm/arch.h
index df17a12..3da9f9f 100644
--- a/libyasm/arch.h
+++ b/libyasm/arch.h
@@ -2,10 +2,6 @@
  * \file libyasm/arch.h
  * \brief YASM architecture interface.
  *
- * \rcs
- * $Id: arch.h 1889 2007-07-08 05:31:59Z peter $
- * \endrcs
- *
  * \license
  *  Copyright (C) 2002-2007  Peter Johnson
  *
diff --git a/libyasm/assocdat.c b/libyasm/assocdat.c
index 98c8d8b..cdcda62 100644
--- a/libyasm/assocdat.c
+++ b/libyasm/assocdat.c
@@ -25,7 +25,6 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include "util.h"
-/*@unused@*/ RCSID("$Id: assocdat.c 1893 2007-07-14 03:11:32Z peter $");
 
 #include "coretype.h"
 #include "assocdat.h"
diff --git a/libyasm/assocdat.h b/libyasm/assocdat.h
index 235c9c8..cf42386 100644
--- a/libyasm/assocdat.h
+++ b/libyasm/assocdat.h
@@ -2,10 +2,6 @@
  * \file assocdat.h
  * \brief YASM associated data storage (libyasm internal use)
  *
- * \rcs
- * $Id: assocdat.h 2101 2008-05-23 06:46:51Z peter $
- * \endrcs
- *
  * \license
  *  Copyright (C) 2003-2007  Peter Johnson
  *
diff --git a/libyasm/bc-align.c b/libyasm/bc-align.c
index 03ebf36..2a47882 100644
--- a/libyasm/bc-align.c
+++ b/libyasm/bc-align.c
@@ -25,7 +25,6 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include "util.h"
-/*@unused@*/ RCSID("$Id: bc-align.c 2130 2008-10-07 05:38:11Z peter $");
 
 #include "libyasm-stdint.h"
 #include "coretype.h"
@@ -58,7 +57,8 @@ static int bc_align_calc_len(yasm_bytecode *bc, yasm_bc_add_span_func add_span,
 static int bc_align_expand(yasm_bytecode *bc, int span, long old_val,
                            long new_val, /*@out@*/ long *neg_thres,
                            /*@out@*/ long *pos_thres);
-static int bc_align_tobytes(yasm_bytecode *bc, unsigned char **bufp, void *d,
+static int bc_align_tobytes(yasm_bytecode *bc, unsigned char **bufp,
+                            unsigned char *bufstart, void *d,
                             yasm_output_value_func output_value,
                             /*@null@*/ yasm_output_reloc_func output_reloc);
 
@@ -164,7 +164,8 @@ bc_align_expand(yasm_bytecode *bc, int span, long old_val, long new_val,
 }
 
 static int
-bc_align_tobytes(yasm_bytecode *bc, unsigned char **bufp, void *d,
+bc_align_tobytes(yasm_bytecode *bc, unsigned char **bufp,
+                 unsigned char *bufstart, void *d,
                  yasm_output_value_func output_value,
                  /*@unused@*/ yasm_output_reloc_func output_reloc)
 {
diff --git a/libyasm/bc-data.c b/libyasm/bc-data.c
index fc36ac5..ebbdd6f 100644
--- a/libyasm/bc-data.c
+++ b/libyasm/bc-data.c
@@ -25,7 +25,6 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include "util.h"
-/*@unused@*/ RCSID("$Id: bc-data.c 2133 2008-10-07 05:59:29Z peter $");
 
 #include "libyasm-stdint.h"
 #include "coretype.h"
@@ -70,7 +69,8 @@ static void bc_data_finalize(yasm_bytecode *bc, yasm_bytecode *prev_bc);
 static int bc_data_item_size(yasm_bytecode *bc);
 static int bc_data_calc_len(yasm_bytecode *bc, yasm_bc_add_span_func add_span,
                             void *add_span_data);
-static int bc_data_tobytes(yasm_bytecode *bc, unsigned char **bufp, void *d,
+static int bc_data_tobytes(yasm_bytecode *bc, unsigned char **bufp,
+                           unsigned char *bufstart, void *d,
                            yasm_output_value_func output_value,
                            /*@null@*/ yasm_output_reloc_func output_reloc);
 
@@ -203,13 +203,13 @@ bc_data_calc_len(yasm_bytecode *bc, yasm_bc_add_span_func add_span,
 }
 
 static int
-bc_data_tobytes(yasm_bytecode *bc, unsigned char **bufp, void *d,
+bc_data_tobytes(yasm_bytecode *bc, unsigned char **bufp,
+                unsigned char *bufstart, void *d,
                 yasm_output_value_func output_value,
                 /*@unused@*/ yasm_output_reloc_func output_reloc)
 {
     bytecode_data *bc_data = (bytecode_data *)bc->contents;
     yasm_dataval *dv;
-    unsigned char *bufp_orig = *bufp;
     yasm_intnum *intn;
     unsigned int val_len;
     unsigned long multiple, i;
@@ -224,7 +224,7 @@ bc_data_tobytes(yasm_bytecode *bc, unsigned char **bufp, void *d,
                 val_len = dv->data.val.size/8;
                 for (i=0; i<multiple; i++) {
                     if (output_value(&dv->data.val, *bufp, val_len,
-                                     (unsigned long)(*bufp-bufp_orig), bc, 1,
+                                     (unsigned long)(*bufp-bufstart), bc, 1,
                                      d))
                         return 1;
                     *bufp += val_len;
@@ -480,6 +480,14 @@ yasm_dv_create_reserve(void)
     return retval;
 }
 
+yasm_value *
+yasm_dv_get_value(yasm_dataval *dv)
+{
+    if (dv->type != DV_VALUE)
+        return NULL;
+    return &dv->data.val;
+}
+
 void
 yasm_dv_set_multiple(yasm_dataval *dv, yasm_expr *e)
 {
diff --git a/libyasm/bc-incbin.c b/libyasm/bc-incbin.c
index fc59256..a8fec7d 100644
--- a/libyasm/bc-incbin.c
+++ b/libyasm/bc-incbin.c
@@ -25,7 +25,6 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include "util.h"
-/*@unused@*/ RCSID("$Id: bc-incbin.c 2130 2008-10-07 05:38:11Z peter $");
 
 #include "libyasm-stdint.h"
 #include "coretype.h"
@@ -58,7 +57,8 @@ static void bc_incbin_print(const void *contents, FILE *f, int indent_level);
 static void bc_incbin_finalize(yasm_bytecode *bc, yasm_bytecode *prev_bc);
 static int bc_incbin_calc_len(yasm_bytecode *bc, yasm_bc_add_span_func add_span,
                               void *add_span_data);
-static int bc_incbin_tobytes(yasm_bytecode *bc, unsigned char **bufp, void *d,
+static int bc_incbin_tobytes(yasm_bytecode *bc, unsigned char **bufp,
+                             unsigned char *bufstart, void *d,
                              yasm_output_value_func output_value,
                              /*@null@*/ yasm_output_reloc_func output_reloc);
 
@@ -195,7 +195,8 @@ bc_incbin_calc_len(yasm_bytecode *bc, yasm_bc_add_span_func add_span,
 }
 
 static int
-bc_incbin_tobytes(yasm_bytecode *bc, unsigned char **bufp, void *d,
+bc_incbin_tobytes(yasm_bytecode *bc, unsigned char **bufp,
+                  unsigned char *bufstart, void *d,
                   yasm_output_value_func output_value,
                   /*@unused@*/ yasm_output_reloc_func output_reloc)
 {
diff --git a/libyasm/bc-org.c b/libyasm/bc-org.c
index 413031b..7ef96c8 100644
--- a/libyasm/bc-org.c
+++ b/libyasm/bc-org.c
@@ -25,7 +25,6 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include "util.h"
-/*@unused@*/ RCSID("$Id: bc-org.c 2130 2008-10-07 05:38:11Z peter $");
 
 #include "libyasm-stdint.h"
 #include "coretype.h"
@@ -52,7 +51,8 @@ static int bc_org_calc_len(yasm_bytecode *bc, yasm_bc_add_span_func add_span,
 static int bc_org_expand(yasm_bytecode *bc, int span, long old_val,
                          long new_val, /*@out@*/ long *neg_thres,
                          /*@out@*/ long *pos_thres);
-static int bc_org_tobytes(yasm_bytecode *bc, unsigned char **bufp, void *d,
+static int bc_org_tobytes(yasm_bytecode *bc, unsigned char **bufp,
+                          unsigned char *bufstart, void *d,
                           yasm_output_value_func output_value,
                           /*@null@*/ yasm_output_reloc_func output_reloc);
 
@@ -120,7 +120,8 @@ bc_org_expand(yasm_bytecode *bc, int span, long old_val, long new_val,
 }
 
 static int
-bc_org_tobytes(yasm_bytecode *bc, unsigned char **bufp, void *d,
+bc_org_tobytes(yasm_bytecode *bc, unsigned char **bufp,
+               unsigned char *bufstart, void *d,
                yasm_output_value_func output_value,
                /*@unused@*/ yasm_output_reloc_func output_reloc)
 {
diff --git a/libyasm/bc-reserve.c b/libyasm/bc-reserve.c
index e3b07e2..197175b 100644
--- a/libyasm/bc-reserve.c
+++ b/libyasm/bc-reserve.c
@@ -25,7 +25,6 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include "util.h"
-/*@unused@*/ RCSID("$Id: bc-reserve.c 2130 2008-10-07 05:38:11Z peter $");
 
 #include "libyasm-stdint.h"
 #include "coretype.h"
@@ -50,7 +49,8 @@ static int bc_reserve_elem_size(yasm_bytecode *bc);
 static int bc_reserve_calc_len(yasm_bytecode *bc,
                                yasm_bc_add_span_func add_span,
                                void *add_span_data);
-static int bc_reserve_tobytes(yasm_bytecode *bc, unsigned char **bufp, void *d,
+static int bc_reserve_tobytes(yasm_bytecode *bc, unsigned char **bufp,
+                              unsigned char *bufstart, void *d,
                               yasm_output_value_func output_value,
                               /*@null@*/ yasm_output_reloc_func output_reloc);
 
@@ -114,7 +114,8 @@ bc_reserve_calc_len(yasm_bytecode *bc, yasm_bc_add_span_func add_span,
 }
 
 static int
-bc_reserve_tobytes(yasm_bytecode *bc, unsigned char **bufp, void *d,
+bc_reserve_tobytes(yasm_bytecode *bc, unsigned char **bufp,
+                   unsigned char *bufstart, void *d,
                    yasm_output_value_func output_value,
                    /*@unused@*/ yasm_output_reloc_func output_reloc)
 {
diff --git a/libyasm/bitvect.c b/libyasm/bitvect.c
index 1e76b7c..dfb0825 100644
--- a/libyasm/bitvect.c
+++ b/libyasm/bitvect.c
@@ -1,5 +1,4 @@
 #include "util.h"
-RCSID("$Id: bitvect.c 2063 2008-04-12 08:30:22Z peter $");
 
 #include "coretype.h"
 
diff --git a/libyasm/bitvect.h b/libyasm/bitvect.h
index 3e39a60..3aee3a5 100644
--- a/libyasm/bitvect.h
+++ b/libyasm/bitvect.h
@@ -1,5 +1,3 @@
-/* $Id: bitvect.h 2101 2008-05-23 06:46:51Z peter $ */
-
 #ifndef YASM_BITVECT_H
 #define YASM_BITVECT_H
 /*****************************************************************************/
diff --git a/libyasm/bytecode.c b/libyasm/bytecode.c
index ea43783..f864bae 100644
--- a/libyasm/bytecode.c
+++ b/libyasm/bytecode.c
@@ -25,7 +25,6 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include "util.h"
-/*@unused@*/ RCSID("$Id: bytecode.c 2233 2009-10-31 21:45:55Z peter $");
 
 #include "libyasm-stdint.h"
 #include "coretype.h"
@@ -73,7 +72,8 @@ yasm_bc_expand_common(yasm_bytecode *bc, int span, long old_val, long new_val,
 }
 
 int
-yasm_bc_tobytes_common(yasm_bytecode *bc, unsigned char **bufp, void *d,
+yasm_bc_tobytes_common(yasm_bytecode *bc, unsigned char **buf,
+                       unsigned char *bufstart, void *d,
                        yasm_output_value_func output_value,
                        /*@null@*/ yasm_output_reloc_func output_reloc)
 {
@@ -305,6 +305,7 @@ yasm_bc_tobytes(yasm_bytecode *bc, unsigned char *buf, unsigned long *bufsize,
     /*@sets *buf@*/
 {
     /*@only@*/ /*@null@*/ unsigned char *mybuf = NULL;
+    unsigned char *bufstart;
     unsigned char *origbuf, *destbuf;
     long i;
     int error = 0;
@@ -329,6 +330,7 @@ yasm_bc_tobytes(yasm_bytecode *bc, unsigned char *buf, unsigned long *bufsize,
         destbuf = mybuf;
     } else
         destbuf = buf;
+    bufstart = destbuf;
 
     *bufsize = bc->len*bc->mult_int;
 
@@ -336,7 +338,7 @@ yasm_bc_tobytes(yasm_bytecode *bc, unsigned char *buf, unsigned long *bufsize,
         yasm_internal_error(N_("got empty bytecode in bc_tobytes"));
     else for (i=0; i<bc->mult_int; i++) {
         origbuf = destbuf;
-        error = bc->callback->tobytes(bc, &destbuf, d, output_value,
+        error = bc->callback->tobytes(bc, &destbuf, bufstart, d, output_value,
                                       output_reloc);
 
         if (!error && ((unsigned long)(destbuf - origbuf) != bc->len))
diff --git a/libyasm/bytecode.h b/libyasm/bytecode.h
index d1244be..4e8a801 100644
--- a/libyasm/bytecode.h
+++ b/libyasm/bytecode.h
@@ -2,10 +2,6 @@
  * \file libyasm/bytecode.h
  * \brief YASM bytecode interface.
  *
- * \rcs
- * $Id: bytecode.h 2130 2008-10-07 05:38:11Z peter $
- * \endrcs
- *
  * \license
  *  Copyright (C) 2001-2007  Peter Johnson
  *
@@ -147,6 +143,8 @@ typedef struct yasm_bytecode_callback {
      *                      passed-in buf matches the bytecode length
      *                      (it's okay not to do this if an error
      *                      indication is returned)
+     * \param bufstart      For calculating the correct offset parameter for
+     *                      the \a output_value calls: *bufp - bufstart.
      * \param d             data to pass to each call to
      *                      output_value/output_reloc
      * \param output_value  function to call to convert values into their byte
@@ -158,7 +156,8 @@ typedef struct yasm_bytecode_callback {
      *       preferable if calling this function twice would result in the
      *       same output.
      */
-    int (*tobytes) (yasm_bytecode *bc, unsigned char **bufp, void *d,
+    int (*tobytes) (yasm_bytecode *bc, unsigned char **bufp,
+                    unsigned char *bufstart, void *d,
                     yasm_output_value_func output_value,
                     /*@null@*/ yasm_output_reloc_func output_reloc);
 
@@ -277,7 +276,7 @@ int yasm_bc_expand_common
  */
 YASM_LIB_DECL
 int yasm_bc_tobytes_common
-    (yasm_bytecode *bc, unsigned char **bufp, void *d,
+    (yasm_bytecode *bc, unsigned char **bufp, unsigned char *bufstart, void *d,
      yasm_output_value_func output_value,
      /*@null@*/ yasm_output_reloc_func output_reloc);
 
@@ -575,6 +574,12 @@ yasm_dataval *yasm_dv_create_reserve(void);
                                                        (unsigned long)(l))
 #endif
 
+/** Get the underlying value of a data value.
+ * \param dv    data value
+ * \return Value, or null if non-value (e.g. string or raw).
+ */
+yasm_value *yasm_dv_get_value(yasm_dataval *dv);
+
 /** Set multiple field of a data value.
  * A data value can be repeated a number of times when output.  This function
  * sets that multiple.
diff --git a/libyasm/compat-queue.h b/libyasm/compat-queue.h
index 6f9841a..da9eff4 100644
--- a/libyasm/compat-queue.h
+++ b/libyasm/compat-queue.h
@@ -1,4 +1,4 @@
-/* $Id: compat-queue.h 1825 2007-04-22 03:32:46Z peter $
+/*
  * <sys/queue.h> implementation for systems that don't have it.
  *
  * Copyright (c) 1991, 1993
diff --git a/libyasm/coretype.h b/libyasm/coretype.h
index 1aca61c..624e3c4 100644
--- a/libyasm/coretype.h
+++ b/libyasm/coretype.h
@@ -2,10 +2,6 @@
  * \file libyasm/coretype.h
  * \brief YASM core types and utility functions.
  *
- * \rcs
- * $Id: coretype.h 2101 2008-05-23 06:46:51Z peter $
- * \endrcs
- *
  * \license
  *  Copyright (C) 2001-2007  Peter Johnson
  *
diff --git a/libyasm/dbgfmt.h b/libyasm/dbgfmt.h
index 4d6b4f6..8e038bb 100644
--- a/libyasm/dbgfmt.h
+++ b/libyasm/dbgfmt.h
@@ -2,10 +2,6 @@
  * \file libyasm/dbgfmt.h
  * \brief YASM debug format interface.
  *
- * \rcs
- * $Id: dbgfmt.h 1827 2007-04-22 05:09:49Z peter $
- * \endrcs
- *
  * \license
  *  Copyright (C) 2002-2007  Peter Johnson
  *
diff --git a/libyasm/errwarn.c b/libyasm/errwarn.c
index 013b55c..d51a0de 100644
--- a/libyasm/errwarn.c
+++ b/libyasm/errwarn.c
@@ -25,7 +25,6 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include "util.h"
-/*@unused@*/ RCSID("$Id: errwarn.c 2258 2010-01-03 01:04:18Z peter $");
 
 #include <ctype.h>
 #include <stdarg.h>
diff --git a/libyasm/errwarn.h b/libyasm/errwarn.h
index 3d21fff..ede2f28 100644
--- a/libyasm/errwarn.h
+++ b/libyasm/errwarn.h
@@ -2,10 +2,6 @@
  * \file libyasm/errwarn.h
  * \brief YASM error and warning reporting interface.
  *
- * \rcs
- * $Id: errwarn.h 2130 2008-10-07 05:38:11Z peter $
- * \endrcs
- *
  * \license
  *  Copyright (C) 2001-2007  Peter Johnson
  *
diff --git a/libyasm/expr.c b/libyasm/expr.c
index 8b68d20..c2c868e 100644
--- a/libyasm/expr.c
+++ b/libyasm/expr.c
@@ -25,7 +25,6 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include "util.h"
-/*@unused@*/ RCSID("$Id: expr.c 2130 2008-10-07 05:38:11Z peter $");
 
 #include "libyasm-stdint.h"
 #include "coretype.h"
@@ -535,7 +534,7 @@ expr_can_destroy_int_right(yasm_expr_op op, yasm_intnum *intn)
  * NOTE: Really designed to only be used by expr_level_op().
  */
 static int
-expr_simplify_identity(yasm_expr *e, int numterms, int int_term,
+expr_simplify_identity(yasm_expr *e, int numterms, int *int_term,
                        int simplify_reg_mul)
 {
     int i;
@@ -547,26 +546,27 @@ expr_simplify_identity(yasm_expr *e, int numterms, int int_term,
     save_numterms = e->numterms;
     e->numterms = numterms;
     if (simplify_reg_mul || e->op != YASM_EXPR_MUL
-        || !yasm_intnum_is_pos1(e->terms[int_term].data.intn)
+        || !yasm_intnum_is_pos1(e->terms[*int_term].data.intn)
         || !yasm_expr__contains(e, YASM_EXPR_REG)) {
         /* Check for simple identities that delete the intnum.
          * Don't delete if the intnum is the only thing in the expn.
          */
-        if ((int_term == 0 && numterms > 1 &&
+        if ((*int_term == 0 && numterms > 1 &&
              expr_can_destroy_int_left(e->op, e->terms[0].data.intn)) ||
-            (int_term > 0 &&
-             expr_can_destroy_int_right(e->op, e->terms[int_term].data.intn))) {
+            (*int_term > 0 &&
+             expr_can_destroy_int_right(e->op,
+                                        e->terms[*int_term].data.intn))) {
             /* Delete the intnum */
-            yasm_intnum_destroy(e->terms[int_term].data.intn);
+            yasm_intnum_destroy(e->terms[*int_term].data.intn);
 
             /* Slide everything to its right over by 1 */
-            if (int_term != numterms-1) /* if it wasn't last.. */
-                memmove(&e->terms[int_term], &e->terms[int_term+1],
-                        (numterms-1-int_term)*sizeof(yasm_expr__item));
+            if (*int_term != numterms-1) /* if it wasn't last.. */
+                memmove(&e->terms[*int_term], &e->terms[*int_term+1],
+                        (numterms-1-*int_term)*sizeof(yasm_expr__item));
 
             /* Update numterms */
             numterms--;
-            int_term = -1;      /* no longer an int term */
+            *int_term = -1;     /* no longer an int term */
         }
     }
     e->numterms = save_numterms;
@@ -574,23 +574,23 @@ expr_simplify_identity(yasm_expr *e, int numterms, int int_term,
     /* Check for simple identites that delete everything BUT the intnum.
      * Don't bother if the intnum is the only thing in the expn.
      */
-    if (numterms > 1 && int_term != -1 &&
-        expr_is_constant(e->op, e->terms[int_term].data.intn)) {
+    if (numterms > 1 && *int_term != -1 &&
+        expr_is_constant(e->op, e->terms[*int_term].data.intn)) {
         /* Loop through, deleting everything but the integer term */
         for (i=0; i<e->numterms; i++)
-            if (i != int_term)
+            if (i != *int_term)
                 expr_delete_term(&e->terms[i], 1);
 
         /* Move integer term to the first term (if not already there) */
-        if (int_term != 0)
-            e->terms[0] = e->terms[int_term];   /* structure copy */
+        if (*int_term != 0)
+            e->terms[0] = e->terms[*int_term];  /* structure copy */
 
         /* Set numterms to 1 */
         numterms = 1;
     }
 
     /* Compute NOT, NEG, and LNOT on single intnum. */
-    if (numterms == 1 && int_term == 0 &&
+    if (numterms == 1 && *int_term == 0 &&
         (e->op == YASM_EXPR_NOT || e->op == YASM_EXPR_NEG ||
          e->op == YASM_EXPR_LNOT))
         yasm_intnum_calc(e->terms[0].data.intn, e->op, NULL);
@@ -698,7 +698,7 @@ expr_level_op(/*@returned@*/ /*@only@*/ yasm_expr *e, int fold_const,
             int new_fold_numterms;
             /* Simplify identities and make IDENT if possible. */
             new_fold_numterms =
-                expr_simplify_identity(e, fold_numterms, first_int_term,
+                expr_simplify_identity(e, fold_numterms, &first_int_term,
                                        simplify_reg_mul);
             level_numterms -= fold_numterms-new_fold_numterms;
             fold_numterms = new_fold_numterms;
@@ -789,7 +789,7 @@ expr_level_op(/*@returned@*/ /*@only@*/ yasm_expr *e, int fold_const,
     /* Simplify identities, make IDENT if possible, and save to e->numterms. */
     if (simplify_ident && first_int_term != -1) {
         e->numterms = expr_simplify_identity(e, level_numterms,
-                                             first_int_term, simplify_reg_mul);
+                                             &first_int_term, simplify_reg_mul);
     } else {
         e->numterms = level_numterms;
         if (level_numterms == 1)
diff --git a/libyasm/expr.h b/libyasm/expr.h
index a0b0935..2b06cd3 100644
--- a/libyasm/expr.h
+++ b/libyasm/expr.h
@@ -2,10 +2,6 @@
  * \file libyasm/expr.h
  * \brief YASM expression interface.
  *
- * \rcs
- * $Id: expr.h 2130 2008-10-07 05:38:11Z peter $
- * \endrcs
- *
  * \license
  *  Copyright (C) 2001-2007  Michael Urman, Peter Johnson
  *
diff --git a/libyasm/file.c b/libyasm/file.c
index 420a974..fc7dab6 100644
--- a/libyasm/file.c
+++ b/libyasm/file.c
@@ -25,12 +25,13 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include <util.h>
-/*@unused@*/ RCSID("$Id: file.c 2287 2010-02-13 08:42:27Z peter $");
 
-/* Need either unistd.h or direct.h (on Windows) to prototype getcwd() */
-#if defined(HAVE_UNISTD_H)
+/* Need either unistd.h or direct.h to prototype getcwd() and mkdir() */
+#ifdef HAVE_UNISTD_H
 #include <unistd.h>
-#elif defined(HAVE_DIRECT_H)
+#endif
+
+#ifdef HAVE_DIRECT_H
 #include <direct.h>
 #endif
 
@@ -243,6 +244,12 @@ yasm__getcwd(void)
 
     size = 1024;
     buf = yasm_xmalloc(size);
+
+    if (getenv("YASM_TEST_SUITE")) {
+        strcpy(buf, "./");
+        return buf;
+    }
+
     while (getcwd(buf, size-1) == NULL) {
         if (errno != ERANGE) {
             yasm__fatal(N_("could not determine current working directory"));
diff --git a/libyasm/file.h b/libyasm/file.h
index 3b6eab8..1e9b87b 100644
--- a/libyasm/file.h
+++ b/libyasm/file.h
@@ -2,10 +2,6 @@
  * \file libyasm/file.h
  * \brief YASM file helpers.
  *
- * \rcs
- * $Id: file.h 2287 2010-02-13 08:42:27Z peter $
- * \endrcs
- *
  * \license
  *  Copyright (C) 2001-2007  Peter Johnson
  *
diff --git a/libyasm/floatnum.c b/libyasm/floatnum.c
index c3b2c74..ab67c2b 100644
--- a/libyasm/floatnum.c
+++ b/libyasm/floatnum.c
@@ -27,7 +27,6 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include "util.h"
-/*@unused@*/ RCSID("$Id: floatnum.c 1954 2007-09-16 20:41:16Z peter $");
 
 #include <ctype.h>
 
diff --git a/libyasm/floatnum.h b/libyasm/floatnum.h
index 77d2f48..d2c7042 100644
--- a/libyasm/floatnum.h
+++ b/libyasm/floatnum.h
@@ -2,10 +2,6 @@
  * \file libyasm/floatnum.h
  * \brief YASM floating point (IEEE) interface.
  *
- * \rcs
- * $Id: floatnum.h 2101 2008-05-23 06:46:51Z peter $
- * \endrcs
- *
  * \license
  *  Copyright (C) 2001-2007  Peter Johnson
  *
diff --git a/libyasm/genmodule.c b/libyasm/genmodule.c
index c332135..a9be08a 100644
--- a/libyasm/genmodule.c
+++ b/libyasm/genmodule.c
@@ -1,4 +1,4 @@
-/* $Id: genmodule.c 1827 2007-04-22 05:09:49Z peter $
+/*
  *
  * Generate module.c from module.in and Makefile.am or Makefile.
  *
diff --git a/libyasm/hamt.c b/libyasm/hamt.c
index 6f64b18..59b7592 100644
--- a/libyasm/hamt.c
+++ b/libyasm/hamt.c
@@ -30,7 +30,6 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include "util.h"
-/*@unused@*/ RCSID("$Id: hamt.c 1907 2007-08-05 16:44:07Z peter $");
 
 #include <ctype.h>
 
diff --git a/libyasm/hamt.h b/libyasm/hamt.h
index afe52a5..1ce9b77 100644
--- a/libyasm/hamt.h
+++ b/libyasm/hamt.h
@@ -2,10 +2,6 @@
  * \file libyasm/hamt.h
  * \brief Hash Array Mapped Trie (HAMT) functions.
  *
- * \rcs
- * $Id: hamt.h 2101 2008-05-23 06:46:51Z peter $
- * \endrcs
- *
  * \license
  *  Copyright (C) 2001-2007  Peter Johnson
  *
diff --git a/libyasm/insn.c b/libyasm/insn.c
index 483a27e..8f7a4c1 100644
--- a/libyasm/insn.c
+++ b/libyasm/insn.c
@@ -25,7 +25,6 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include "util.h"
-/*@unused@*/ RCSID("$Id: insn.c 2130 2008-10-07 05:38:11Z peter $");
 
 #include "libyasm-stdint.h"
 #include "coretype.h"
diff --git a/libyasm/insn.h b/libyasm/insn.h
index 2ff4851..d2d175d 100644
--- a/libyasm/insn.h
+++ b/libyasm/insn.h
@@ -2,10 +2,6 @@
  * \file libyasm/insn.h
  * \brief YASM mnenomic instruction.
  *
- * \rcs
- * $Id: insn.h 2130 2008-10-07 05:38:11Z peter $
- * \endrcs
- *
  * \license
  *  Copyright (C) 2002-2007  Peter Johnson
  *
diff --git a/libyasm/intnum.c b/libyasm/intnum.c
index 7268d55..6feba33 100644
--- a/libyasm/intnum.c
+++ b/libyasm/intnum.c
@@ -25,7 +25,6 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include "util.h"
-/*@unused@*/ RCSID("$Id: intnum.c 2253 2010-01-01 20:47:58Z peter $");
 
 #include <ctype.h>
 #include <limits.h>
diff --git a/libyasm/intnum.h b/libyasm/intnum.h
index 296d14b..bec832c 100644
--- a/libyasm/intnum.h
+++ b/libyasm/intnum.h
@@ -2,10 +2,6 @@
  * \file libyasm/intnum.h
  * \brief YASM integer number interface.
  *
- * \rcs
- * $Id: intnum.h 2130 2008-10-07 05:38:11Z peter $
- * \endrcs
- *
  * \license
  *  Copyright (C) 2001-2007  Peter Johnson
  *
diff --git a/libyasm/inttree.c b/libyasm/inttree.c
index 6666c08..2ae10e9 100644
--- a/libyasm/inttree.c
+++ b/libyasm/inttree.c
@@ -1,5 +1,4 @@
 #include "util.h"
-/*@unused@*/ RCSID("$Id: inttree.c 2262 2010-01-03 02:46:11Z peter $");
 
 #include <stdlib.h>
 #include <stdio.h>
diff --git a/libyasm/inttree.h b/libyasm/inttree.h
index 2ae4096..f7a7651 100644
--- a/libyasm/inttree.h
+++ b/libyasm/inttree.h
@@ -1,4 +1,3 @@
-/* $Id: inttree.h 2101 2008-05-23 06:46:51Z peter $ */
 #ifndef YASM_INTTREE_H
 #define YASM_INTTREE_H
 
diff --git a/libyasm/linemap.c b/libyasm/linemap.c
index 1fa3f7d..42201d3 100644
--- a/libyasm/linemap.c
+++ b/libyasm/linemap.c
@@ -25,7 +25,6 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include "util.h"
-/*@unused@*/ RCSID("$Id: linemap.c 2259 2010-01-03 01:58:23Z peter $");
 
 #include "coretype.h"
 #include "hamt.h"
diff --git a/libyasm/linemap.h b/libyasm/linemap.h
index 3dcff1e..1c5aa46 100644
--- a/libyasm/linemap.h
+++ b/libyasm/linemap.h
@@ -2,10 +2,6 @@
  * \file libyasm/linemap.h
  * \brief YASM virtual line mapping interface.
  *
- * \rcs
- * $Id: linemap.h 2259 2010-01-03 01:58:23Z peter $
- * \endrcs
- *
  * \license
  *  Copyright (C) 2002-2007  Peter Johnson
  *
diff --git a/libyasm/listfmt.h b/libyasm/listfmt.h
index 20da9da..945f28e 100644
--- a/libyasm/listfmt.h
+++ b/libyasm/listfmt.h
@@ -2,10 +2,6 @@
  * \file libyasm/listfmt.h
  * \brief YASM list format interface.
  *
- * \rcs
- * $Id: listfmt.h 1827 2007-04-22 05:09:49Z peter $
- * \endrcs
- *
  * \license
  *  Copyright (C) 2004-2007  Peter Johnson
  *
diff --git a/libyasm/md5.c b/libyasm/md5.c
index 0260348..ba1a307 100644
--- a/libyasm/md5.c
+++ b/libyasm/md5.c
@@ -29,7 +29,6 @@
    this file is only about 3k of object code.  */
 
 #include <util.h>
-/*@unused@*/ RCSID("$Id: md5.c 1825 2007-04-22 03:32:46Z peter $");
 
 #include "md5.h"
 
diff --git a/libyasm/md5.h b/libyasm/md5.h
index 66313d1..7872fda 100644
--- a/libyasm/md5.h
+++ b/libyasm/md5.h
@@ -1,9 +1,5 @@
 /* See md5.c for explanation and copyright information.  */
 
-/*
- * $Id: md5.h 2101 2008-05-23 06:46:51Z peter $
- */
-
 #ifndef YASM_MD5_H
 #define YASM_MD5_H
 
diff --git a/libyasm/mergesort.c b/libyasm/mergesort.c
index cffcd8a..3eeaa82 100644
--- a/libyasm/mergesort.c
+++ b/libyasm/mergesort.c
@@ -32,7 +32,6 @@
  * SUCH DAMAGE.
  */
 #include "util.h"
-/*@unused@*/ RCSID("$Id: mergesort.c 1893 2007-07-14 03:11:32Z peter $");
 
 #if defined(LIBC_SCCS) && !defined(lint)
 static char sccsid[] = "@(#)merge.c     8.2 (Berkeley) 2/14/94";
diff --git a/libyasm/module.h b/libyasm/module.h
index 9eb3761..220017d 100644
--- a/libyasm/module.h
+++ b/libyasm/module.h
@@ -1,4 +1,4 @@
-/* $Id: module.h 2101 2008-05-23 06:46:51Z peter $
+/*
  * YASM module loader header file
  *
  *  Copyright (C) 2002-2007  Peter Johnson
diff --git a/libyasm/module.in b/libyasm/module.in
index bc47684..a18778b 100644
--- a/libyasm/module.in
+++ b/libyasm/module.in
@@ -25,7 +25,6 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include <util.h>
-/*@unused@*/ RCSID("$Id: module.in 2080 2008-04-30 04:40:29Z peter $");
 
 #include <libyasm.h>
 
diff --git a/libyasm/objfmt.h b/libyasm/objfmt.h
index 2332981..840296a 100644
--- a/libyasm/objfmt.h
+++ b/libyasm/objfmt.h
@@ -2,10 +2,6 @@
  * \file libyasm/objfmt.h
  * \brief YASM object format module interface.
  *
- * \rcs
- * $Id: objfmt.h 2310 2010-03-28 19:28:54Z peter $
- * \endrcs
- *
  * \license
  *  Copyright (C) 2001-2007  Peter Johnson
  *
diff --git a/libyasm/parser.h b/libyasm/parser.h
index fe82335..93d4d33 100644
--- a/libyasm/parser.h
+++ b/libyasm/parser.h
@@ -2,10 +2,6 @@
  * \file libyasm/parser.h
  * \brief YASM parser module interface.
  *
- * \rcs
- * $Id: parser.h 2082 2008-05-09 06:46:02Z peter $
- * \endrcs
- *
  * \license
  *  Copyright (C) 2001-2007  Peter Johnson
  *
diff --git a/libyasm/phash.c b/libyasm/phash.c
index 43183ab..cef8c78 100644
--- a/libyasm/phash.c
+++ b/libyasm/phash.c
@@ -1,6 +1,5 @@
 /* Modified for use with yasm by Peter Johnson. */
 #include "util.h"
-/*@unused@*/ RCSID("$Id: phash.c 1893 2007-07-14 03:11:32Z peter $");
 
 /*
 --------------------------------------------------------------------
diff --git a/libyasm/phash.h b/libyasm/phash.h
index bcc65c9..2273a5d 100644
--- a/libyasm/phash.h
+++ b/libyasm/phash.h
@@ -1,6 +1,4 @@
-/* Modified for use with yasm by Peter Johnson.
- * $Id: phash.h 2101 2008-05-23 06:46:51Z peter $
- */
+/* Modified for use with yasm by Peter Johnson. */
 /*
 ------------------------------------------------------------------------------
 By Bob Jenkins, September 1996.
diff --git a/libyasm/preproc.h b/libyasm/preproc.h
index 632f3fc..751b19e 100644
--- a/libyasm/preproc.h
+++ b/libyasm/preproc.h
@@ -2,10 +2,6 @@
  * \file libyasm/preproc.h
  * \brief YASM preprocessor module interface.
  *
- * \rcs
- * $Id: preproc.h 2082 2008-05-09 06:46:02Z peter $
- * \endrcs
- *
  * \license
  *  Copyright (C) 2001-2007  Peter Johnson
  *
diff --git a/libyasm/section.c b/libyasm/section.c
index ebff313..9242fb0 100644
--- a/libyasm/section.c
+++ b/libyasm/section.c
@@ -25,7 +25,6 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include "util.h"
-/*@unused@*/ RCSID("$Id: section.c 2310 2010-03-28 19:28:54Z peter $");
 
 #include <limits.h>
 
diff --git a/libyasm/section.h b/libyasm/section.h
index 8666859..2c7faa4 100644
--- a/libyasm/section.h
+++ b/libyasm/section.h
@@ -2,10 +2,6 @@
  * \file libyasm/section.h
  * \brief YASM section interface.
  *
- * \rcs
- * $Id: section.h 2109 2008-06-08 09:06:05Z peter $
- * \endrcs
- *
  * \license
  *  Copyright (C) 2001-2007  Peter Johnson
  *
diff --git a/libyasm/strcasecmp.c b/libyasm/strcasecmp.c
index 4bfa7c2..a87bd88 100644
--- a/libyasm/strcasecmp.c
+++ b/libyasm/strcasecmp.c
@@ -30,8 +30,6 @@
  * SUCH DAMAGE.
  */
 #include "util.h"
-/*@unused@*/ RCSID("$Id: strcasecmp.c 1893 2007-07-14 03:11:32Z peter $");
-
 
 #ifndef USE_OUR_OWN_STRCASECMP
 #undef yasm__strcasecmp
diff --git a/libyasm/strsep.c b/libyasm/strsep.c
index fd58484..0fecd47 100644
--- a/libyasm/strsep.c
+++ b/libyasm/strsep.c
@@ -30,7 +30,6 @@
  */
 #define NO_STRING_INLINES
 #include "util.h"
-/*@unused@*/ RCSID("$Id: strsep.c 1893 2007-07-14 03:11:32Z peter $");
 
 
 #if defined(LIBC_SCCS) && !defined(lint)
diff --git a/libyasm/symrec.c b/libyasm/symrec.c
index 27704d1..694f0c6 100644
--- a/libyasm/symrec.c
+++ b/libyasm/symrec.c
@@ -25,7 +25,6 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include "util.h"
-/*@unused@*/ RCSID("$Id: symrec.c 2130 2008-10-07 05:38:11Z peter $");
 
 #include <limits.h>
 #include <ctype.h>
diff --git a/libyasm/symrec.h b/libyasm/symrec.h
index 3953857..6207158 100644
--- a/libyasm/symrec.h
+++ b/libyasm/symrec.h
@@ -2,10 +2,6 @@
  * \file libyasm/symrec.h
  * \brief YASM symbol table interface.
  *
- * \rcs
- * $Id: symrec.h 2130 2008-10-07 05:38:11Z peter $
- * \endrcs
- *
  * \license
  *  Copyright (C) 2001-2007  Michael Urman, Peter Johnson
  *
diff --git a/libyasm/valparam.c b/libyasm/valparam.c
index 8904ae0..88e41a7 100644
--- a/libyasm/valparam.c
+++ b/libyasm/valparam.c
@@ -25,7 +25,6 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include "util.h"
-/*@unused@*/ RCSID("$Id: valparam.c 2010 2007-11-14 08:33:32Z peter $");
 
 #include "libyasm-stdint.h"
 #include "coretype.h"
diff --git a/libyasm/valparam.h b/libyasm/valparam.h
index 98f4972..d7343d4 100644
--- a/libyasm/valparam.h
+++ b/libyasm/valparam.h
@@ -2,10 +2,6 @@
  * \file libyasm/valparam.h
  * \brief YASM value/parameter interface.
  *
- * \rcs
- * $Id: valparam.h 2101 2008-05-23 06:46:51Z peter $
- * \endrcs
- *
  * \license
  *  Copyright (C) 2001-2007  Peter Johnson
  *
diff --git a/libyasm/value.c b/libyasm/value.c
index 4ad0db1..3ab73c1 100644
--- a/libyasm/value.c
+++ b/libyasm/value.c
@@ -25,7 +25,6 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include "util.h"
-/*@unused@*/ RCSID("$Id: value.c 2220 2009-07-24 19:01:35Z peter $");
 
 #include "libyasm-stdint.h"
 #include "coretype.h"
@@ -453,10 +452,17 @@ yasm_value_finalize_expr(yasm_value *value, yasm_expr *e,
         yasm_value_initialize(value, NULL, size);
         return 0;
     }
+    yasm_value_initialize(value, e, size);
+    return yasm_value_finalize(value, precbc);
+}
 
-    yasm_value_initialize(value,
-                          yasm_expr__level_tree(e, 1, 1, 0, 0, NULL, NULL),
-                          size);
+int
+yasm_value_finalize(yasm_value *value, yasm_bytecode *precbc)
+{
+    if (!value->abs)
+        return 0;
+
+    value->abs = yasm_expr__level_tree(value->abs, 1, 1, 0, 0, NULL, NULL);
 
     /* quit early if there was an issue in simplify() */
     if (yasm_error_occurred())
@@ -549,13 +555,6 @@ yasm_value_finalize_expr(yasm_value *value, yasm_expr *e,
     return 0;
 }
 
-int
-yasm_value_finalize(yasm_value *value, yasm_bytecode *precbc)
-{
-    unsigned int valsize = value->size;
-    return yasm_value_finalize_expr(value, value->abs, precbc, valsize);
-}
-
 yasm_intnum *
 yasm_value_get_intnum(yasm_value *value, yasm_bytecode *bc, int calc_bc_dist)
 {
diff --git a/libyasm/value.h b/libyasm/value.h
index df217a5..4dc294b 100644
--- a/libyasm/value.h
+++ b/libyasm/value.h
@@ -2,10 +2,6 @@
  * \file libyasm/value.h
  * \brief YASM value interface.
  *
- * \rcs
- * $Id: value.h 2101 2008-05-23 06:46:51Z peter $
- * \endrcs
- *
  * \license
  *  Copyright (C) 2006-2007  Peter Johnson
  *
diff --git a/libyasm/xmalloc.c b/libyasm/xmalloc.c
index e8a2552..81b608c 100644
--- a/libyasm/xmalloc.c
+++ b/libyasm/xmalloc.c
@@ -25,7 +25,6 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include "util.h"
-RCSID("$Id: xmalloc.c 2101 2008-05-23 06:46:51Z peter $");
 
 #include "coretype.h"
 #include "errwarn.h"
diff --git a/libyasm/xstrdup.c b/libyasm/xstrdup.c
index 0836ad8..b187704 100644
--- a/libyasm/xstrdup.c
+++ b/libyasm/xstrdup.c
@@ -29,7 +29,6 @@
  * SUCH DAMAGE.
  */
 #include "util.h"
-RCSID("$Id: xstrdup.c 1893 2007-07-14 03:11:32Z peter $");
 
 #include "coretype.h"
 
diff --git a/modules/arch/lc3b/lc3barch.c b/modules/arch/lc3b/lc3barch.c
index 87c0d08..0514528 100644
--- a/modules/arch/lc3b/lc3barch.c
+++ b/modules/arch/lc3b/lc3barch.c
@@ -25,7 +25,6 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include <util.h>
-/*@unused@*/ RCSID("$Id: lc3barch.c 1963 2007-09-19 07:47:10Z peter $");
 
 #include <libyasm.h>
 
diff --git a/modules/arch/lc3b/lc3barch.h b/modules/arch/lc3b/lc3barch.h
index 8f9aa04..9ded8cb 100644
--- a/modules/arch/lc3b/lc3barch.h
+++ b/modules/arch/lc3b/lc3barch.h
@@ -1,4 +1,4 @@
-/* $Id: lc3barch.h 1914 2007-08-20 05:13:35Z peter $
+/*
  * LC-3b Architecture header file
  *
  *  Copyright (C) 2003-2007  Peter Johnson
diff --git a/modules/arch/lc3b/lc3bbc.c b/modules/arch/lc3b/lc3bbc.c
index af60245..d077c7c 100644
--- a/modules/arch/lc3b/lc3bbc.c
+++ b/modules/arch/lc3b/lc3bbc.c
@@ -25,7 +25,6 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include <util.h>
-/*@unused@*/ RCSID("$Id: lc3bbc.c 2130 2008-10-07 05:38:11Z peter $");
 
 #include <libyasm.h>
 
@@ -44,6 +43,7 @@ static int lc3b_bc_insn_expand(yasm_bytecode *bc, int span, long old_val,
                                long new_val, /*@out@*/ long *neg_thres,
                                /*@out@*/ long *pos_thres);
 static int lc3b_bc_insn_tobytes(yasm_bytecode *bc, unsigned char **bufp,
+                                unsigned char *bufstart,
                                 void *d, yasm_output_value_func output_value,
                                 /*@null@*/ yasm_output_reloc_func output_reloc);
 
@@ -165,12 +165,14 @@ lc3b_bc_insn_expand(yasm_bytecode *bc, int span, long old_val, long new_val,
 }
 
 static int
-lc3b_bc_insn_tobytes(yasm_bytecode *bc, unsigned char **bufp, void *d,
+lc3b_bc_insn_tobytes(yasm_bytecode *bc, unsigned char **bufp,
+                     unsigned char *bufstart, void *d,
                      yasm_output_value_func output_value,
                      /*@unused@*/ yasm_output_reloc_func output_reloc)
 {
     lc3b_insn *insn = (lc3b_insn *)bc->contents;
     /*@only@*/ yasm_intnum *delta;
+    unsigned long buf_off = (unsigned long)(*bufp - bufstart);
 
     /* Output opcode */
     YASM_SAVE_16_L(*bufp, insn->opcode);
@@ -181,29 +183,29 @@ lc3b_bc_insn_tobytes(yasm_bytecode *bc, unsigned char **bufp, void *d,
             break;
         case LC3B_IMM_4:
             insn->imm.size = 4;
-            if (output_value(&insn->imm, *bufp, 2, 0, bc, 1, d))
+            if (output_value(&insn->imm, *bufp, 2, buf_off, bc, 1, d))
                 return 1;
             break;
         case LC3B_IMM_5:
             insn->imm.size = 5;
             insn->imm.sign = 1;
-            if (output_value(&insn->imm, *bufp, 2, 0, bc, 1, d))
+            if (output_value(&insn->imm, *bufp, 2, buf_off, bc, 1, d))
                 return 1;
             break;
         case LC3B_IMM_6_WORD:
             insn->imm.size = 6;
-            if (output_value(&insn->imm, *bufp, 2, 0, bc, 1, d))
+            if (output_value(&insn->imm, *bufp, 2, buf_off, bc, 1, d))
                 return 1;
             break;
         case LC3B_IMM_6_BYTE:
             insn->imm.size = 6;
             insn->imm.sign = 1;
-            if (output_value(&insn->imm, *bufp, 2, 0, bc, 1, d))
+            if (output_value(&insn->imm, *bufp, 2, buf_off, bc, 1, d))
                 return 1;
             break;
         case LC3B_IMM_8:
             insn->imm.size = 8;
-            if (output_value(&insn->imm, *bufp, 2, 0, bc, 1, d))
+            if (output_value(&insn->imm, *bufp, 2, buf_off, bc, 1, d))
                 return 1;
             break;
         case LC3B_IMM_9_PC:
@@ -220,12 +222,12 @@ lc3b_bc_insn_tobytes(yasm_bytecode *bc, unsigned char **bufp, void *d,
 
             insn->imm.size = 9;
             insn->imm.sign = 1;
-            if (output_value(&insn->imm, *bufp, 2, 0, bc, 1, d))
+            if (output_value(&insn->imm, *bufp, 2, buf_off, bc, 1, d))
                 return 1;
             break;
         case LC3B_IMM_9:
             insn->imm.size = 9;
-            if (output_value(&insn->imm, *bufp, 2, 0, bc, 1, d))
+            if (output_value(&insn->imm, *bufp, 2, buf_off, bc, 1, d))
                 return 1;
             break;
         default:
diff --git a/modules/arch/lc3b/lc3bid.re b/modules/arch/lc3b/lc3bid.re
index 24ec891..2b3cf7a 100644
--- a/modules/arch/lc3b/lc3bid.re
+++ b/modules/arch/lc3b/lc3bid.re
@@ -25,7 +25,6 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include <util.h>
-RCSID("$Id: lc3bid.re 2130 2008-10-07 05:38:11Z peter $");
 
 #include <libyasm.h>
 
diff --git a/modules/arch/x86/gen_x86_insn.py b/modules/arch/x86/gen_x86_insn.py
index 3aa8fab..8c9c8f0 100755
--- a/modules/arch/x86/gen_x86_insn.py
+++ b/modules/arch/x86/gen_x86_insn.py
@@ -26,19 +26,13 @@
 #
 # NOTE: operands are arranged in NASM / Intel order (e.g. dest, src)
 
-from sys import stdout, version_info
-
-rcstag = "$Id: gen_x86_insn.py 2346 2010-08-01 01:37:37Z peter $"
-
 import os
 import sys
 
-try:
-    scriptname = rcstag.split()[1]
-    scriptrev = rcstag.split()[2]
-except IndexError:
-    scriptname = "gen_x86_insn.py"
-    scriptrev = "HEAD"
+from sys import stdout, version_info
+
+scriptname = "gen_x86_insn.py"
+scriptrev = "HEAD"
 
 ordered_cpus = [
     "086", "186", "286", "386", "486", "586", "686", "K6", "Athlon", "P3",
@@ -47,7 +41,8 @@ ordered_cpu_features = [
     "FPU", "Cyrix", "AMD", "MMX", "3DNow", "SMM", "SSE", "SSE2",
     "SSE3", "SVM", "PadLock", "SSSE3", "SSE41", "SSE42", "SSE4a", "SSE5",
     "AVX", "FMA", "AES", "CLMUL", "MOVBE", "XOP", "FMA4", "F16C",
-    "FSGSBASE", "RDRAND", "XSAVEOPT", "EPTVPID", "SMX"]
+    "FSGSBASE", "RDRAND", "XSAVEOPT", "EPTVPID", "SMX", "AVX2", "BMI1",
+    "BMI2", "INVPCID", "LZCNT"]
 unordered_cpu_features = ["Priv", "Prot", "Undoc", "Obs"]
 
 # Predefined VEX prefix field values
@@ -564,11 +559,13 @@ def finalize_insns():
                         keyword = name
                     else:
                         keyword = name+suffix
+                    keyword = keyword.lower()
                     if keyword in gas_insns:
                         raise ValueError("duplicate gas instruction %s" %
                                          keyword)
                     newinsn = insn.copy()
-                    newinsn.suffix = suffix
+                    if insn.suffix is None:
+                        newinsn.suffix = suffix
                     newinsn.auto_cpu("gas")
                     newinsn.auto_misc_flags("gas")
                     gas_insns[keyword] = newinsn
@@ -1135,6 +1132,10 @@ add_insn("movsxd", "movsxd", parser="nasm")
 # Push instructions
 #
 add_group("push",
+    def_opersize_64=64,
+    opcode=[0x50],
+    operands=[Operand(type="Reg", size="BITS", dest="Op0Add")])
+add_group("push",
     suffix="w",
     opersize=16,
     def_opersize_64=64,
@@ -1148,9 +1149,16 @@ add_group("push",
     operands=[Operand(type="Reg", size=32, dest="Op0Add")])
 add_group("push",
     suffix="q",
+    only64=True,
     def_opersize_64=64,
     opcode=[0x50],
     operands=[Operand(type="Reg", size=64, dest="Op0Add")])
+
+add_group("push",
+    def_opersize_64=64,
+    opcode=[0xFF],
+    spare=6,
+    operands=[Operand(type="RM", size="BITS", dest="EA")])
 add_group("push",
     suffix="w",
     opersize=16,
@@ -1167,10 +1175,12 @@ add_group("push",
     operands=[Operand(type="RM", size=32, dest="EA")])
 add_group("push",
     suffix="q",
+    only64=True,
     def_opersize_64=64,
     opcode=[0xFF],
     spare=6,
     operands=[Operand(type="RM", size=64, dest="EA")])
+
 add_group("push",
     cpu=["186"],
     parsers=["nasm"],
@@ -1342,6 +1352,10 @@ add_insn("pushaw", "onebyte", modifiers=[0x60, 16], cpu=["186"], not64=True)
 # Pop instructions
 #
 add_group("pop",
+    def_opersize_64=64,
+    opcode=[0x58],
+    operands=[Operand(type="Reg", size="BITS", dest="Op0Add")])
+add_group("pop",
     suffix="w",
     opersize=16,
     def_opersize_64=64,
@@ -1355,9 +1369,15 @@ add_group("pop",
     operands=[Operand(type="Reg", size=32, dest="Op0Add")])
 add_group("pop",
     suffix="q",
+    only64=True,
     def_opersize_64=64,
     opcode=[0x58],
     operands=[Operand(type="Reg", size=64, dest="Op0Add")])
+
+add_group("pop",
+    def_opersize_64=64,
+    opcode=[0x8F],
+    operands=[Operand(type="RM", size="BITS", dest="EA")])
 add_group("pop",
     suffix="w",
     opersize=16,
@@ -1372,9 +1392,11 @@ add_group("pop",
     operands=[Operand(type="RM", size=32, dest="EA")])
 add_group("pop",
     suffix="q",
+    only64=True,
     def_opersize_64=64,
     opcode=[0x8F],
     operands=[Operand(type="RM", size=64, dest="EA")])
+
 # POP CS is debateably valid on the 8086, if obsolete and undocumented.
 # We don't include it because it's VERY unlikely it will ever be used
 # anywhere.  If someone really wants it they can db 0x0F it.
@@ -1731,7 +1753,7 @@ for sfx, sz in zip("wl", [16, 32]):
 add_insn("lds", "ldes", modifiers=[0xC5])
 add_insn("les", "ldes", modifiers=[0xC4])
 
-for sfx, sz in zip("wl", [16, 32]):
+for sfx, sz in zip("wlq", [16, 32, 64]):
     add_group("lfgss",
         suffix=sfx,
         cpu=["386"],
@@ -3083,8 +3105,24 @@ add_insn("nop", "onebyte", modifiers=[0x90])
 #
 # Protection control
 #
-add_insn("lar", "bsfr", modifiers=[0x02], cpu=["286", "Prot"])
-add_insn("lsl", "bsfr", modifiers=[0x03], cpu=["286", "Prot"])
+for sfx, sz, sz2 in zip("wlq", [16, 32, 64], [16, 32, 32]):
+    add_group("larlsl",
+        suffix=sfx,
+        modifiers=["Op1Add"],
+        opersize=sz,
+        opcode=[0x0F, 0x00],
+        operands=[Operand(type="Reg", size=sz, dest="Spare"),
+                  Operand(type="Reg", size=sz2, dest="EA")])
+    add_group("larlsl",
+        suffix=sfx,
+        modifiers=["Op1Add"],
+        opersize=sz,
+        opcode=[0x0F, 0x00],
+        operands=[Operand(type="Reg", size=sz, dest="Spare"),
+                  Operand(type="RM", size=16, relaxed=True, dest="EA")])
+
+add_insn("lar", "larlsl", modifiers=[0x02], cpu=["286", "Prot"])
+add_insn("lsl", "larlsl", modifiers=[0x03], cpu=["286", "Prot"])
 
 add_group("arpl",
     suffix="w",
@@ -3957,44 +3995,44 @@ add_insn("punpckldq", "mmxsse2", modifiers=[0x62])
 add_insn("pxor",      "mmxsse2", modifiers=[0xEF])
 
 # AVX versions don't support the MMX registers
-add_insn("vpackssdw",  "xmm_xmm128", modifiers=[0x66, 0x6B, VEXL0], avx=True)
-add_insn("vpacksswb",  "xmm_xmm128", modifiers=[0x66, 0x63, VEXL0], avx=True)
-add_insn("vpackuswb",  "xmm_xmm128", modifiers=[0x66, 0x67, VEXL0], avx=True)
-add_insn("vpaddb",     "xmm_xmm128", modifiers=[0x66, 0xFC, VEXL0], avx=True)
-add_insn("vpaddw",     "xmm_xmm128", modifiers=[0x66, 0xFD, VEXL0], avx=True)
-add_insn("vpaddd",     "xmm_xmm128", modifiers=[0x66, 0xFE, VEXL0], avx=True)
-add_insn("vpaddq",     "xmm_xmm128", modifiers=[0x66, 0xD4, VEXL0], avx=True)
-add_insn("vpaddsb",    "xmm_xmm128", modifiers=[0x66, 0xEC, VEXL0], avx=True)
-add_insn("vpaddsw",    "xmm_xmm128", modifiers=[0x66, 0xED, VEXL0], avx=True)
-add_insn("vpaddusb",   "xmm_xmm128", modifiers=[0x66, 0xDC, VEXL0], avx=True)
-add_insn("vpaddusw",   "xmm_xmm128", modifiers=[0x66, 0xDD, VEXL0], avx=True)
-add_insn("vpand",      "xmm_xmm128", modifiers=[0x66, 0xDB, VEXL0], avx=True)
-add_insn("vpandn",     "xmm_xmm128", modifiers=[0x66, 0xDF, VEXL0], avx=True)
-add_insn("vpcmpeqb",   "xmm_xmm128", modifiers=[0x66, 0x74, VEXL0], avx=True)
-add_insn("vpcmpeqw",   "xmm_xmm128", modifiers=[0x66, 0x75, VEXL0], avx=True)
-add_insn("vpcmpeqd",   "xmm_xmm128", modifiers=[0x66, 0x76, VEXL0], avx=True)
-add_insn("vpcmpgtb",   "xmm_xmm128", modifiers=[0x66, 0x64, VEXL0], avx=True)
-add_insn("vpcmpgtw",   "xmm_xmm128", modifiers=[0x66, 0x65, VEXL0], avx=True)
-add_insn("vpcmpgtd",   "xmm_xmm128", modifiers=[0x66, 0x66, VEXL0], avx=True)
-add_insn("vpmaddwd",   "xmm_xmm128", modifiers=[0x66, 0xF5, VEXL0], avx=True)
-add_insn("vpmulhw",    "xmm_xmm128", modifiers=[0x66, 0xE5, VEXL0], avx=True)
-add_insn("vpmullw",    "xmm_xmm128", modifiers=[0x66, 0xD5, VEXL0], avx=True)
-add_insn("vpor",       "xmm_xmm128", modifiers=[0x66, 0xEB, VEXL0], avx=True)
-add_insn("vpsubb",     "xmm_xmm128", modifiers=[0x66, 0xF8, VEXL0], avx=True)
-add_insn("vpsubw",     "xmm_xmm128", modifiers=[0x66, 0xF9, VEXL0], avx=True)
-add_insn("vpsubd",     "xmm_xmm128", modifiers=[0x66, 0xFA, VEXL0], avx=True)
-add_insn("vpsubq",     "xmm_xmm128", modifiers=[0x66, 0xFB, VEXL0], avx=True)
-add_insn("vpsubsb",    "xmm_xmm128", modifiers=[0x66, 0xE8, VEXL0], avx=True)
-add_insn("vpsubsw",    "xmm_xmm128", modifiers=[0x66, 0xE9, VEXL0], avx=True)
-add_insn("vpsubusb",   "xmm_xmm128", modifiers=[0x66, 0xD8, VEXL0], avx=True)
-add_insn("vpsubusw",   "xmm_xmm128", modifiers=[0x66, 0xD9, VEXL0], avx=True)
-add_insn("vpunpckhbw", "xmm_xmm128", modifiers=[0x66, 0x68, VEXL0], avx=True)
-add_insn("vpunpckhwd", "xmm_xmm128", modifiers=[0x66, 0x69, VEXL0], avx=True)
-add_insn("vpunpckhdq", "xmm_xmm128", modifiers=[0x66, 0x6A, VEXL0], avx=True)
-add_insn("vpunpcklbw", "xmm_xmm128", modifiers=[0x66, 0x60, VEXL0], avx=True)
-add_insn("vpunpcklwd", "xmm_xmm128", modifiers=[0x66, 0x61, VEXL0], avx=True)
-add_insn("vpunpckldq", "xmm_xmm128", modifiers=[0x66, 0x62, VEXL0], avx=True)
-add_insn("vpxor",      "xmm_xmm128", modifiers=[0x66, 0xEF, VEXL0], avx=True)
+add_insn("vpackssdw",  "xmm_xmm128_256avx2", modifiers=[0x66, 0x6B, VEXL0], avx=True)
+add_insn("vpacksswb",  "xmm_xmm128_256avx2", modifiers=[0x66, 0x63, VEXL0], avx=True)
+add_insn("vpackuswb",  "xmm_xmm128_256avx2", modifiers=[0x66, 0x67, VEXL0], avx=True)
+add_insn("vpaddb",     "xmm_xmm128_256avx2", modifiers=[0x66, 0xFC, VEXL0], avx=True)
+add_insn("vpaddw",     "xmm_xmm128_256avx2", modifiers=[0x66, 0xFD, VEXL0], avx=True)
+add_insn("vpaddd",     "xmm_xmm128_256avx2", modifiers=[0x66, 0xFE, VEXL0], avx=True)
+add_insn("vpaddq",     "xmm_xmm128_256avx2", modifiers=[0x66, 0xD4, VEXL0], avx=True)
+add_insn("vpaddsb",    "xmm_xmm128_256avx2", modifiers=[0x66, 0xEC, VEXL0], avx=True)
+add_insn("vpaddsw",    "xmm_xmm128_256avx2", modifiers=[0x66, 0xED, VEXL0], avx=True)
+add_insn("vpaddusb",   "xmm_xmm128_256avx2", modifiers=[0x66, 0xDC, VEXL0], avx=True)
+add_insn("vpaddusw",   "xmm_xmm128_256avx2", modifiers=[0x66, 0xDD, VEXL0], avx=True)
+add_insn("vpand",      "xmm_xmm128_256avx2", modifiers=[0x66, 0xDB, VEXL0], avx=True)
+add_insn("vpandn",     "xmm_xmm128_256avx2", modifiers=[0x66, 0xDF, VEXL0], avx=True)
+add_insn("vpcmpeqb",   "xmm_xmm128_256avx2", modifiers=[0x66, 0x74, VEXL0], avx=True)
+add_insn("vpcmpeqw",   "xmm_xmm128_256avx2", modifiers=[0x66, 0x75, VEXL0], avx=True)
+add_insn("vpcmpeqd",   "xmm_xmm128_256avx2", modifiers=[0x66, 0x76, VEXL0], avx=True)
+add_insn("vpcmpgtb",   "xmm_xmm128_256avx2", modifiers=[0x66, 0x64, VEXL0], avx=True)
+add_insn("vpcmpgtw",   "xmm_xmm128_256avx2", modifiers=[0x66, 0x65, VEXL0], avx=True)
+add_insn("vpcmpgtd",   "xmm_xmm128_256avx2", modifiers=[0x66, 0x66, VEXL0], avx=True)
+add_insn("vpmaddwd",   "xmm_xmm128_256avx2", modifiers=[0x66, 0xF5, VEXL0], avx=True)
+add_insn("vpmulhw",    "xmm_xmm128_256avx2", modifiers=[0x66, 0xE5, VEXL0], avx=True)
+add_insn("vpmullw",    "xmm_xmm128_256avx2", modifiers=[0x66, 0xD5, VEXL0], avx=True)
+add_insn("vpor",       "xmm_xmm128_256avx2", modifiers=[0x66, 0xEB, VEXL0], avx=True)
+add_insn("vpsubb",     "xmm_xmm128_256avx2", modifiers=[0x66, 0xF8, VEXL0], avx=True)
+add_insn("vpsubw",     "xmm_xmm128_256avx2", modifiers=[0x66, 0xF9, VEXL0], avx=True)
+add_insn("vpsubd",     "xmm_xmm128_256avx2", modifiers=[0x66, 0xFA, VEXL0], avx=True)
+add_insn("vpsubq",     "xmm_xmm128_256avx2", modifiers=[0x66, 0xFB, VEXL0], avx=True)
+add_insn("vpsubsb",    "xmm_xmm128_256avx2", modifiers=[0x66, 0xE8, VEXL0], avx=True)
+add_insn("vpsubsw",    "xmm_xmm128_256avx2", modifiers=[0x66, 0xE9, VEXL0], avx=True)
+add_insn("vpsubusb",   "xmm_xmm128_256avx2", modifiers=[0x66, 0xD8, VEXL0], avx=True)
+add_insn("vpsubusw",   "xmm_xmm128_256avx2", modifiers=[0x66, 0xD9, VEXL0], avx=True)
+add_insn("vpunpckhbw", "xmm_xmm128_256avx2", modifiers=[0x66, 0x68, VEXL0], avx=True)
+add_insn("vpunpckhwd", "xmm_xmm128_256avx2", modifiers=[0x66, 0x69, VEXL0], avx=True)
+add_insn("vpunpckhdq", "xmm_xmm128_256avx2", modifiers=[0x66, 0x6A, VEXL0], avx=True)
+add_insn("vpunpcklbw", "xmm_xmm128_256avx2", modifiers=[0x66, 0x60, VEXL0], avx=True)
+add_insn("vpunpcklwd", "xmm_xmm128_256avx2", modifiers=[0x66, 0x61, VEXL0], avx=True)
+add_insn("vpunpckldq", "xmm_xmm128_256avx2", modifiers=[0x66, 0x62, VEXL0], avx=True)
+add_insn("vpxor",      "xmm_xmm128_256avx2", modifiers=[0x66, 0xEF, VEXL0], avx=True)
 
 add_group("pshift",
     cpu=["MMX"],
@@ -4035,42 +4073,43 @@ add_insn("psrld", "pshift", modifiers=[0xD2, 0x72, 2])
 add_insn("psrlq", "pshift", modifiers=[0xD3, 0x73, 2])
 
 # Ran out of modifiers, so AVX has to be separate
-add_group("vpshift",
-    cpu=["AVX"],
-    modifiers=["Op1Add"],
-    vex=128,
-    prefix=0x66,
-    opcode=[0x0F, 0x00],
-    operands=[Operand(type="SIMDReg", size=128, dest="SpareVEX"),
-              Operand(type="SIMDRM", size=128, relaxed=True, dest="EA")])
-add_group("vpshift",
-    cpu=["AVX"],
-    modifiers=["Gap", "Op1Add", "SpAdd"],
-    vex=128,
-    prefix=0x66,
-    opcode=[0x0F, 0x00],
-    spare=0,
-    operands=[Operand(type="SIMDReg", size=128, dest="EAVEX"),
-              Operand(type="Imm", size=8, relaxed=True, dest="Imm")])
-add_group("vpshift",
-    cpu=["AVX"],
-    modifiers=["Op1Add"],
-    vex=128,
-    prefix=0x66,
-    opcode=[0x0F, 0x00],
-    operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
-              Operand(type="SIMDReg", size=128, dest="VEX"),
-              Operand(type="SIMDRM", size=128, relaxed=True, dest="EA")])
-add_group("vpshift",
-    cpu=["AVX"],
-    modifiers=["Gap", "Op1Add", "SpAdd"],
-    vex=128,
-    prefix=0x66,
-    opcode=[0x0F, 0x00],
-    spare=0,
-    operands=[Operand(type="SIMDReg", size=128, dest="VEX"),
-              Operand(type="SIMDReg", size=128, dest="EA"),
-              Operand(type="Imm", size=8, relaxed=True, dest="Imm")])
+for cpu, sz in zip(["AVX", "AVX2"], [128, 256]):
+    add_group("vpshift",
+        cpu=[cpu],
+        modifiers=["Op1Add"],
+        vex=sz,
+        prefix=0x66,
+        opcode=[0x0F, 0x00],
+        operands=[Operand(type="SIMDReg", size=sz, dest="SpareVEX"),
+                  Operand(type="SIMDRM", size=128, relaxed=True, dest="EA")])
+    add_group("vpshift",
+        cpu=[cpu],
+        modifiers=["Gap", "Op1Add", "SpAdd"],
+        vex=sz,
+        prefix=0x66,
+        opcode=[0x0F, 0x00],
+        spare=0,
+        operands=[Operand(type="SIMDReg", size=sz, dest="EAVEX"),
+                  Operand(type="Imm", size=8, relaxed=True, dest="Imm")])
+    add_group("vpshift",
+        cpu=[cpu],
+        modifiers=["Op1Add"],
+        vex=sz,
+        prefix=0x66,
+        opcode=[0x0F, 0x00],
+        operands=[Operand(type="SIMDReg", size=sz, dest="Spare"),
+                  Operand(type="SIMDReg", size=sz, dest="VEX"),
+                  Operand(type="SIMDRM", size=128, relaxed=True, dest="EA")])
+    add_group("vpshift",
+        cpu=[cpu],
+        modifiers=["Gap", "Op1Add", "SpAdd"],
+        vex=sz,
+        prefix=0x66,
+        opcode=[0x0F, 0x00],
+        spare=0,
+        operands=[Operand(type="SIMDReg", size=sz, dest="VEX"),
+                  Operand(type="SIMDReg", size=sz, dest="EA"),
+                  Operand(type="Imm", size=8, relaxed=True, dest="Imm")])
 
 add_insn("vpsllw", "vpshift", modifiers=[0xF1, 0x71, 6])
 add_insn("vpslld", "vpshift", modifiers=[0xF2, 0x72, 6])
@@ -4094,14 +4133,14 @@ add_insn("pmulhuw", "mmxsse2", modifiers=[0xE4], cpu=["P3", "MMX"])
 add_insn("psadbw",  "mmxsse2", modifiers=[0xF6], cpu=["P3", "MMX"])
 
 # AVX versions don't support MMX register
-add_insn("vpavgb",   "xmm_xmm128", modifiers=[0x66, 0xE0, VEXL0], avx=True)
-add_insn("vpavgw",   "xmm_xmm128", modifiers=[0x66, 0xE3, VEXL0], avx=True)
-add_insn("vpmaxsw",  "xmm_xmm128", modifiers=[0x66, 0xEE, VEXL0], avx=True)
-add_insn("vpmaxub",  "xmm_xmm128", modifiers=[0x66, 0xDE, VEXL0], avx=True)
-add_insn("vpminsw",  "xmm_xmm128", modifiers=[0x66, 0xEA, VEXL0], avx=True)
-add_insn("vpminub",  "xmm_xmm128", modifiers=[0x66, 0xDA, VEXL0], avx=True)
-add_insn("vpmulhuw", "xmm_xmm128", modifiers=[0x66, 0xE4, VEXL0], avx=True)
-add_insn("vpsadbw",  "xmm_xmm128", modifiers=[0x66, 0xF6, VEXL0], avx=True)
+add_insn("vpavgb",   "xmm_xmm128_256avx2", modifiers=[0x66, 0xE0, VEXL0], avx=True)
+add_insn("vpavgw",   "xmm_xmm128_256avx2", modifiers=[0x66, 0xE3, VEXL0], avx=True)
+add_insn("vpmaxsw",  "xmm_xmm128_256avx2", modifiers=[0x66, 0xEE, VEXL0], avx=True)
+add_insn("vpmaxub",  "xmm_xmm128_256avx2", modifiers=[0x66, 0xDE, VEXL0], avx=True)
+add_insn("vpminsw",  "xmm_xmm128_256avx2", modifiers=[0x66, 0xEA, VEXL0], avx=True)
+add_insn("vpminub",  "xmm_xmm128_256avx2", modifiers=[0x66, 0xDA, VEXL0], avx=True)
+add_insn("vpmulhuw", "xmm_xmm128_256avx2", modifiers=[0x66, 0xE4, VEXL0], avx=True)
+add_insn("vpsadbw",  "xmm_xmm128_256avx2", modifiers=[0x66, 0xF6, VEXL0], avx=True)
 
 add_insn("prefetchnta", "twobytemem", modifiers=[0, 0x0F, 0x18], cpu=["P3"])
 add_insn("prefetcht0", "twobytemem", modifiers=[1, 0x0F, 0x18], cpu=["P3"])
@@ -4132,6 +4171,49 @@ add_group("xmm_xmm128_256",
     vex=256,
     prefix=0x00,
     opcode=[0x0F, 0x00],
+    operands=[Operand(type="SIMDReg", size=256, dest="SpareVEX"),
+              Operand(type="SIMDRM", size=256, relaxed=True, dest="EA")])
+add_group("xmm_xmm128_256",
+    cpu=["AVX"],
+    modifiers=["PreAdd", "Op1Add"],
+    vex=256,
+    prefix=0x00,
+    opcode=[0x0F, 0x00],
+    operands=[Operand(type="SIMDReg", size=256, dest="Spare"),
+              Operand(type="SIMDReg", size=256, dest="VEX"),
+              Operand(type="SIMDRM", size=256, relaxed=True, dest="EA")])
+
+# Same as above, except 256-bit version only available in AVX2
+add_group("xmm_xmm128_256avx2",
+    cpu=["SSE"],
+    modifiers=["PreAdd", "Op1Add", "SetVEX"],
+    prefix=0x00,
+    opcode=[0x0F, 0x00],
+    operands=[Operand(type="SIMDReg", size=128, dest="SpareVEX"),
+              Operand(type="SIMDRM", size=128, relaxed=True, dest="EA")])
+add_group("xmm_xmm128_256avx2",
+    cpu=["AVX"],
+    modifiers=["PreAdd", "Op1Add"],
+    vex=128,
+    prefix=0x00,
+    opcode=[0x0F, 0x00],
+    operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
+              Operand(type="SIMDReg", size=128, dest="VEX"),
+              Operand(type="SIMDRM", size=128, relaxed=True, dest="EA")])
+add_group("xmm_xmm128_256avx2",
+    cpu=["AVX2"],
+    modifiers=["PreAdd", "Op1Add"],
+    vex=256,
+    prefix=0x00,
+    opcode=[0x0F, 0x00],
+    operands=[Operand(type="SIMDReg", size=256, dest="SpareVEX"),
+              Operand(type="SIMDRM", size=256, relaxed=True, dest="EA")])
+add_group("xmm_xmm128_256avx2",
+    cpu=["AVX2"],
+    modifiers=["PreAdd", "Op1Add"],
+    vex=256,
+    prefix=0x00,
+    opcode=[0x0F, 0x00],
     operands=[Operand(type="SIMDReg", size=256, dest="Spare"),
               Operand(type="SIMDReg", size=256, dest="VEX"),
               Operand(type="SIMDRM", size=256, relaxed=True, dest="EA")])
@@ -4486,6 +4568,23 @@ add_group("xmm_xmm128_imm",
 add_insn("cmpps", "xmm_xmm128_imm", modifiers=[0, 0xC2])
 add_insn("shufps", "xmm_xmm128_imm", modifiers=[0, 0xC6])
 
+# YMM register AVX2 version of above
+add_group("xmm_xmm128_imm_256avx2",
+    cpu=["SSE"],
+    modifiers=["PreAdd", "Op1Add", "SetVEX"],
+    opcode=[0x0F, 0x00],
+    operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
+              Operand(type="SIMDRM", size=128, relaxed=True, dest="EA"),
+              Operand(type="Imm", size=8, relaxed=True, dest="Imm")])
+add_group("xmm_xmm128_imm_256avx2",
+    cpu=["AVX2"],
+    modifiers=["PreAdd", "Op1Add"],
+    vex=256,
+    opcode=[0x0F, 0x00],
+    operands=[Operand(type="SIMDReg", size=256, dest="Spare"),
+              Operand(type="SIMDRM", size=256, relaxed=True, dest="EA"),
+              Operand(type="Imm", size=8, relaxed=True, dest="Imm")])
+
 # YMM register and 4-operand version of above
 add_group("xmm_xmm128_imm_256",
     cpu=["SSE"],
@@ -4951,10 +5050,19 @@ add_group("pmovmskb",
     operands=[Operand(type="Reg", size=32, dest="Spare"),
               Operand(type="SIMDReg", size=128, dest="EA")])
 add_group("pmovmskb",
+    suffix="l",
+    cpu=["AVX2"],
+    vex=256,
+    prefix=0x66,
+    opcode=[0x0F, 0xD7],
+    operands=[Operand(type="Reg", size=32, dest="Spare"),
+              Operand(type="SIMDReg", size=256, dest="EA")])
+add_group("pmovmskb",
     suffix="q",
     cpu=["MMX", "P3"],
     notavx=True,
     opersize=64,
+    def_opersize_64=64,
     opcode=[0x0F, 0xD7],
     operands=[Operand(type="Reg", size=64, dest="Spare"),
               Operand(type="SIMDReg", size=64, dest="EA")])
@@ -4963,10 +5071,21 @@ add_group("pmovmskb",
     cpu=["SSE2"],
     modifiers=["SetVEX"],
     opersize=64,
+    def_opersize_64=64,
     prefix=0x66,
     opcode=[0x0F, 0xD7],
     operands=[Operand(type="Reg", size=64, dest="Spare"),
               Operand(type="SIMDReg", size=128, dest="EA")])
+add_group("pmovmskb",
+    suffix="q",
+    cpu=["SSE2"],
+    vex=256,
+    opersize=64,
+    def_opersize_64=64,
+    prefix=0x66,
+    opcode=[0x0F, 0xD7],
+    operands=[Operand(type="Reg", size=64, dest="Spare"),
+              Operand(type="SIMDReg", size=256, dest="EA")])
 
 add_insn("pmovmskb", "pmovmskb")
 add_insn("vpmovmskb", "pmovmskb", modifiers=[VEXL0], avx=True)
@@ -5377,12 +5496,12 @@ add_insn("punpcklqdq", "xmm_xmm128", modifiers=[0x66, 0x6C], cpu=["SSE2"])
 add_insn("vcvttsd2si", "cvt_rx_xmm64", modifiers=[0xF2, 0x2C, VEXL0], avx=True)
 # vcvttpd2dq takes xmm, ymm combination
 # vcvttps2dq is two-operand
-add_insn("vpmuludq", "xmm_xmm128", modifiers=[0x66, 0xF4, VEXL0], avx=True)
-add_insn("vpshufd", "xmm_xmm128_imm", modifiers=[0x66, 0x70, VEXL0], avx=True)
-add_insn("vpshufhw", "xmm_xmm128_imm", modifiers=[0xF3, 0x70, VEXL0], avx=True)
-add_insn("vpshuflw", "xmm_xmm128_imm", modifiers=[0xF2, 0x70, VEXL0], avx=True)
-add_insn("vpunpckhqdq", "xmm_xmm128", modifiers=[0x66, 0x6D, VEXL0], avx=True)
-add_insn("vpunpcklqdq", "xmm_xmm128", modifiers=[0x66, 0x6C, VEXL0], avx=True)
+add_insn("vpmuludq", "xmm_xmm128_256avx2", modifiers=[0x66, 0xF4, VEXL0], avx=True)
+add_insn("vpshufd", "xmm_xmm128_imm_256avx2", modifiers=[0x66, 0x70, VEXL0], avx=True)
+add_insn("vpshufhw", "xmm_xmm128_imm_256avx2", modifiers=[0xF3, 0x70, VEXL0], avx=True)
+add_insn("vpshuflw", "xmm_xmm128_imm_256avx2", modifiers=[0xF2, 0x70, VEXL0], avx=True)
+add_insn("vpunpckhqdq", "xmm_xmm128_256avx2", modifiers=[0x66, 0x6D, VEXL0], avx=True)
+add_insn("vpunpcklqdq", "xmm_xmm128_256avx2", modifiers=[0x66, 0x6C, VEXL0], avx=True)
 
 add_insn("cvtss2sd", "xmm_xmm32", modifiers=[0xF3, 0x5A], cpu=["SSE2"])
 add_insn("vcvtss2sd", "xmm_xmm32", modifiers=[0xF3, 0x5A, VEXL0], avx=True)
@@ -5438,6 +5557,25 @@ add_group("pslrldq",
     operands=[Operand(type="SIMDReg", size=128, dest="VEX"),
               Operand(type="SIMDReg", size=128, dest="EA"),
               Operand(type="Imm", size=8, relaxed=True, dest="Imm")])
+add_group("pslrldq",
+    cpu=["AVX2"],
+    modifiers=["SpAdd"],
+    vex=256,
+    prefix=0x66,
+    opcode=[0x0F, 0x73],
+    spare=0,
+    operands=[Operand(type="SIMDReg", size=256, dest="EAVEX"),
+              Operand(type="Imm", size=8, relaxed=True, dest="Imm")])
+add_group("pslrldq",
+    cpu=["AVX2"],
+    modifiers=["SpAdd"],
+    vex=256,
+    prefix=0x66,
+    opcode=[0x0F, 0x73],
+    spare=0,
+    operands=[Operand(type="SIMDReg", size=256, dest="VEX"),
+              Operand(type="SIMDReg", size=256, dest="EA"),
+              Operand(type="Imm", size=8, relaxed=True, dest="Imm")])
 
 add_insn("pslldq", "pslrldq", modifiers=[7])
 add_insn("psrldq", "pslrldq", modifiers=[3])
@@ -5514,6 +5652,23 @@ add_group("ssse3",
     operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
               Operand(type="SIMDReg", size=128, dest="VEX"),
               Operand(type="SIMDRM", size=128, relaxed=True, dest="EA")])
+add_group("ssse3",
+    cpu=["AVX2"],
+    modifiers=["Op2Add"],
+    vex=256,
+    prefix=0x66,
+    opcode=[0x0F, 0x38, 0x00],
+    operands=[Operand(type="SIMDReg", size=256, dest="SpareVEX"),
+              Operand(type="SIMDRM", size=256, relaxed=True, dest="EA")])
+add_group("ssse3",
+    cpu=["AVX2"],
+    modifiers=["Op2Add"],
+    vex=256,
+    prefix=0x66,
+    opcode=[0x0F, 0x38, 0x00],
+    operands=[Operand(type="SIMDReg", size=256, dest="Spare"),
+              Operand(type="SIMDReg", size=256, dest="VEX"),
+              Operand(type="SIMDRM", size=256, relaxed=True, dest="EA")])
 
 add_insn("pshufb",    "ssse3", modifiers=[0x00])
 add_insn("phaddw",    "ssse3", modifiers=[0x01])
@@ -5562,7 +5717,7 @@ add_group("ssse3imm",
               Operand(type="Imm", size=8, relaxed=True, dest="Imm")])
 
 add_insn("palignr", "ssse3imm", modifiers=[0x0F])
-add_insn("vpalignr", "sse4imm", modifiers=[0x0F, VEXL0], avx=True)
+add_insn("vpalignr", "sse4imm_256avx2", modifiers=[0x0F, VEXL0], avx=True)
 
 #####################################################################
 # SSE4.1 / SSE4.2 instructions
@@ -5642,6 +5797,54 @@ add_group("sse4imm_256",
     vex=256,
     prefix=0x66,
     opcode=[0x0F, 0x3A, 0x00],
+    operands=[Operand(type="SIMDReg", size=256, dest="SpareVEX"),
+              Operand(type="SIMDRM", size=256, relaxed=True, dest="EA"),
+              Operand(type="Imm", size=8, relaxed=True, dest="Imm")])
+add_group("sse4imm_256",
+    cpu=["AVX"],
+    modifiers=["Op2Add"],
+    vex=256,
+    prefix=0x66,
+    opcode=[0x0F, 0x3A, 0x00],
+    operands=[Operand(type="SIMDReg", size=256, dest="Spare"),
+              Operand(type="SIMDReg", size=256, dest="VEX"),
+              Operand(type="SIMDRM", size=256, relaxed=True, dest="EA"),
+              Operand(type="Imm", size=8, relaxed=True, dest="Imm")])
+
+# Same as above except AVX2 required for 256-bit.
+add_group("sse4imm_256avx2",
+    cpu=["SSE41"],
+    modifiers=["Op2Add", "SetVEX"],
+    prefix=0x66,
+    opcode=[0x0F, 0x3A, 0x00],
+    operands=[Operand(type="SIMDReg", size=128, dest="SpareVEX"),
+              Operand(type="SIMDRM", size=128, relaxed=True, dest="EA"),
+              Operand(type="Imm", size=8, relaxed=True, dest="Imm")])
+add_group("sse4imm_256avx2",
+    cpu=["AVX"],
+    modifiers=["Op2Add"],
+    vex=128,
+    prefix=0x66,
+    opcode=[0x0F, 0x3A, 0x00],
+    operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
+              Operand(type="SIMDReg", size=128, dest="VEX"),
+              Operand(type="SIMDRM", size=128, relaxed=True, dest="EA"),
+              Operand(type="Imm", size=8, relaxed=True, dest="Imm")])
+add_group("sse4imm_256avx2",
+    cpu=["AVX2"],
+    modifiers=["Op2Add"],
+    vex=256,
+    prefix=0x66,
+    opcode=[0x0F, 0x3A, 0x00],
+    operands=[Operand(type="SIMDReg", size=256, dest="SpareVEX"),
+              Operand(type="SIMDRM", size=256, relaxed=True, dest="EA"),
+              Operand(type="Imm", size=8, relaxed=True, dest="Imm")])
+add_group("sse4imm_256avx2",
+    cpu=["AVX2"],
+    modifiers=["Op2Add"],
+    vex=256,
+    prefix=0x66,
+    opcode=[0x0F, 0x3A, 0x00],
     operands=[Operand(type="SIMDReg", size=256, dest="Spare"),
               Operand(type="SIMDReg", size=256, dest="VEX"),
               Operand(type="SIMDRM", size=256, relaxed=True, dest="EA"),
@@ -5716,13 +5919,14 @@ add_insn("roundps", "sse4imm", modifiers=[0x08])
 add_insn("roundsd", "sse4m64imm", modifiers=[0x0B])
 add_insn("roundss", "sse4m32imm", modifiers=[0x0A])
 
-# vdppd, vmpsadbw, and vpblendw do not allow YMM registers
+# vdppd does not allow YMM registers
+# vmpsadbw and vpblendw do not allow YMM registers unless AVX2
 add_insn("vblendpd", "sse4imm_256", modifiers=[0x0D, VEXL0], avx=True)
 add_insn("vblendps", "sse4imm_256", modifiers=[0x0C, VEXL0], avx=True)
 add_insn("vdppd",    "sse4imm", modifiers=[0x41, VEXL0], avx=True)
 add_insn("vdpps",    "sse4imm_256", modifiers=[0x40, VEXL0], avx=True)
-add_insn("vmpsadbw", "sse4imm", modifiers=[0x42, VEXL0], avx=True)
-add_insn("vpblendw", "sse4imm", modifiers=[0x0E, VEXL0], avx=True)
+add_insn("vmpsadbw", "sse4imm_256avx2", modifiers=[0x42, VEXL0], avx=True)
+add_insn("vpblendw", "sse4imm_256avx2", modifiers=[0x0E, VEXL0], avx=True)
 # vroundpd and vroundps don't add another register operand
 add_insn("vroundsd", "sse4m64imm", modifiers=[0x0B, VEXL0], avx=True)
 add_insn("vroundss", "sse4m32imm", modifiers=[0x0A, VEXL0], avx=True)
@@ -5772,9 +5976,9 @@ add_group("avx_sse4xmm0",
 add_insn("vblendvpd", "avx_sse4xmm0", modifiers=[0x4B])
 add_insn("vblendvps", "avx_sse4xmm0", modifiers=[0x4A])
 
-# vpblendvb doesn't have a 256-bit form
-add_group("avx_sse4xmm0_128",
-    cpu=["AVX"],
+# vpblendvb didn't have a 256-bit form until AVX2
+add_group("avx2_sse4xmm0",
+    cpu=["AVX2"],
     modifiers=["Op2Add"],
     vex=128,
     prefix=0x66,
@@ -5783,8 +5987,18 @@ add_group("avx_sse4xmm0_128",
               Operand(type="SIMDReg", size=128, dest="VEX"),
               Operand(type="SIMDRM", size=128, relaxed=True, dest="EA"),
               Operand(type="SIMDReg", size=128, dest="VEXImmSrc")])
+add_group("avx2_sse4xmm0",
+    cpu=["AVX2"],
+    modifiers=["Op2Add"],
+    vex=256,
+    prefix=0x66,
+    opcode=[0x0F, 0x3A, 0x00],
+    operands=[Operand(type="SIMDReg", size=256, dest="Spare"),
+              Operand(type="SIMDReg", size=256, dest="VEX"),
+              Operand(type="SIMDRM", size=256, relaxed=True, dest="EA"),
+              Operand(type="SIMDReg", size=256, dest="VEXImmSrc")])
 
-add_insn("vpblendvb", "avx_sse4xmm0_128", modifiers=[0x4C])
+add_insn("vpblendvb", "avx2_sse4xmm0", modifiers=[0x4C])
 
 for sfx, sz in zip("bwl", [8, 16, 32]):
     add_group("crc32",
@@ -5873,6 +6087,13 @@ add_group("movntdqa",
     opcode=[0x0F, 0x38, 0x2A],
     operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
               Operand(type="Mem", size=128, relaxed=True, dest="EA")])
+add_group("movntdqa",
+    cpu=["AVX2"],
+    vex=256,
+    prefix=0x66,
+    opcode=[0x0F, 0x38, 0x2A],
+    operands=[Operand(type="SIMDReg", size=256, dest="Spare"),
+              Operand(type="Mem", size=256, relaxed=True, dest="EA")])
 
 add_insn("movntdqa", "movntdqa")
 add_insn("vmovntdqa", "movntdqa", modifiers=[VEXL0], avx=True)
@@ -6047,6 +6268,22 @@ for sz in [16, 32, 64]:
         opcode=[0x0F, 0x38, 0x00],
         operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
                   Operand(type="SIMDReg", size=128, dest="EA")])
+    add_group("sse4m%d" % sz,
+        cpu=["AVX2"],
+        modifiers=["Op2Add"],
+        vex=256,
+        prefix=0x66,
+        opcode=[0x0F, 0x38, 0x00],
+        operands=[Operand(type="SIMDReg", size=256, dest="Spare"),
+                  Operand(type="Mem", size=sz*2, relaxed=True, dest="EA")])
+    add_group("sse4m%d" % sz,
+        cpu=["AVX2"],
+        modifiers=["Op2Add"],
+        vex=256,
+        prefix=0x66,
+        opcode=[0x0F, 0x38, 0x00],
+        operands=[Operand(type="SIMDReg", size=256, dest="Spare"),
+                  Operand(type="SIMDReg", size=128, dest="EA")])
 
 add_insn("pmovsxbw", "sse4m64", modifiers=[0x20])
 add_insn("pmovsxwd", "sse4m64", modifiers=[0x23])
@@ -6323,12 +6560,22 @@ add_group("avx_ssse3_2op",
     opcode=[0x0F, 0x38, 0x00],
     operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
               Operand(type="SIMDRM", size=128, relaxed=True, dest="EA")])
-
-add_insn("vpabsb",     "avx_ssse3_2op", modifiers=[0x1C], avx=True)
-add_insn("vpabsw",     "avx_ssse3_2op", modifiers=[0x1D], avx=True)
-add_insn("vpabsd",     "avx_ssse3_2op", modifiers=[0x1E], avx=True)
 add_insn("vphminposuw", "avx_ssse3_2op", modifiers=[0x41], avx=True)
 
+# VPABS* are extended to 256-bit in AVX2
+for cpu, sz in zip(["AVX", "AVX2"], [128, 256]):
+    add_group("avx2_ssse3_2op",
+        cpu=[cpu],
+        modifiers=["Op2Add"],
+        vex=sz,
+        prefix=0x66,
+        opcode=[0x0F, 0x38, 0x00],
+        operands=[Operand(type="SIMDReg", size=sz, dest="Spare"),
+                  Operand(type="SIMDRM", size=sz, relaxed=True, dest="EA")])
+add_insn("vpabsb",     "avx2_ssse3_2op", modifiers=[0x1C], avx=True)
+add_insn("vpabsw",     "avx2_ssse3_2op", modifiers=[0x1D], avx=True)
+add_insn("vpabsd",     "avx2_ssse3_2op", modifiers=[0x1E], avx=True)
+
 # Some conversion functions take xmm, ymm combination
 # Need separate x and y versions for gas mode
 add_group("avx_cvt_xmm128_x",
@@ -6395,6 +6642,20 @@ add_group("vbroadcastss",
     opcode=[0x0F, 0x38, 0x18],
     operands=[Operand(type="SIMDReg", size=256, dest="Spare"),
               Operand(type="Mem", size=32, relaxed=True, dest="EA")])
+add_group("vbroadcastss",
+    cpu=["AVX2"],
+    vex=128,
+    prefix=0x66,
+    opcode=[0x0F, 0x38, 0x18],
+    operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
+              Operand(type="SIMDReg", size=128, dest="EA")])
+add_group("vbroadcastss",
+    cpu=["AVX2"],
+    vex=256,
+    prefix=0x66,
+    opcode=[0x0F, 0x38, 0x18],
+    operands=[Operand(type="SIMDReg", size=256, dest="Spare"),
+              Operand(type="SIMDReg", size=128, dest="EA")])
 
 add_insn("vbroadcastss", "vbroadcastss")
 
@@ -6405,41 +6666,51 @@ add_group("vbroadcastsd",
     opcode=[0x0F, 0x38, 0x19],
     operands=[Operand(type="SIMDReg", size=256, dest="Spare"),
               Operand(type="Mem", size=64, relaxed=True, dest="EA")])
+add_group("vbroadcastsd",
+    cpu=["AVX2"],
+    vex=256,
+    prefix=0x66,
+    opcode=[0x0F, 0x38, 0x19],
+    operands=[Operand(type="SIMDReg", size=256, dest="Spare"),
+              Operand(type="SIMDReg", size=128, dest="EA")])
 
 add_insn("vbroadcastsd", "vbroadcastsd")
 
-add_group("vbroadcastf128",
-    cpu=["AVX"],
+add_group("vbroadcastif128",
+    modifiers=["Op2Add"],
     vex=256,
     prefix=0x66,
-    opcode=[0x0F, 0x38, 0x1A],
+    opcode=[0x0F, 0x38, 0x00],
     operands=[Operand(type="SIMDReg", size=256, dest="Spare"),
               Operand(type="Mem", size=128, relaxed=True, dest="EA")])
 
-add_insn("vbroadcastf128", "vbroadcastf128")
+add_insn("vbroadcastf128", "vbroadcastif128", modifiers=[0x1A], cpu=["AVX"])
+add_insn("vbroadcasti128", "vbroadcastif128", modifiers=[0x5A], cpu=["AVX2"])
 
-add_group("vextractf128",
-    cpu=["AVX"],
+add_group("vextractif128",
+    modifiers=["Op2Add"],
     vex=256,
     prefix=0x66,
-    opcode=[0x0F, 0x3A, 0x19],
+    opcode=[0x0F, 0x3A, 0x00],
     operands=[Operand(type="SIMDRM", size=128, relaxed=True, dest="EA"),
               Operand(type="SIMDReg", size=256, dest="Spare"),
               Operand(type="Imm", size=8, relaxed=True, dest="Imm")])
 
-add_insn("vextractf128", "vextractf128")
+add_insn("vextractf128", "vextractif128", modifiers=[0x19], cpu=["AVX"])
+add_insn("vextracti128", "vextractif128", modifiers=[0x39], cpu=["AVX2"])
 
-add_group("vinsertf128",
-    cpu=["AVX"],
+add_group("vinsertif128",
+    modifiers=["Op2Add"],
     vex=256,
     prefix=0x66,
-    opcode=[0x0F, 0x3A, 0x18],
+    opcode=[0x0F, 0x3A, 0x00],
     operands=[Operand(type="SIMDReg", size=256, dest="Spare"),
               Operand(type="SIMDReg", size=256, dest="VEX"),
               Operand(type="SIMDRM", size=128, relaxed=True, dest="EA"),
               Operand(type="Imm", size=8, relaxed=True, dest="Imm")])
 
-add_insn("vinsertf128", "vinsertf128")
+add_insn("vinsertf128", "vinsertif128", modifiers=[0x18], cpu=["AVX"])
+add_insn("vinserti128", "vinsertif128", modifiers=[0x38], cpu=["AVX2"])
 
 add_group("vzero",
     cpu=["AVX"],
@@ -6451,7 +6722,6 @@ add_insn("vzeroall", "vzero", modifiers=[VEXL1])
 add_insn("vzeroupper", "vzero", modifiers=[VEXL0])
 
 add_group("vmaskmov",
-    cpu=["AVX"],
     modifiers=["Op2Add"],
     vex=128,
     prefix=0x66,
@@ -6460,7 +6730,6 @@ add_group("vmaskmov",
               Operand(type="SIMDReg", size=128, dest="VEX"),
               Operand(type="SIMDRM", size=128, relaxed=True, dest="EA")])
 add_group("vmaskmov",
-    cpu=["AVX"],
     modifiers=["Op2Add"],
     vex=256,
     prefix=0x66,
@@ -6469,7 +6738,6 @@ add_group("vmaskmov",
               Operand(type="SIMDReg", size=256, dest="VEX"),
               Operand(type="SIMDRM", size=256, relaxed=True, dest="EA")])
 add_group("vmaskmov",
-    cpu=["AVX"],
     modifiers=["Op2Add"],
     vex=128,
     prefix=0x66,
@@ -6478,7 +6746,6 @@ add_group("vmaskmov",
               Operand(type="SIMDReg", size=128, dest="VEX"),
               Operand(type="SIMDReg", size=128, dest="Spare")])
 add_group("vmaskmov",
-    cpu=["AVX"],
     modifiers=["Op2Add"],
     vex=256,
     prefix=0x66,
@@ -6487,8 +6754,8 @@ add_group("vmaskmov",
               Operand(type="SIMDReg", size=256, dest="VEX"),
               Operand(type="SIMDReg", size=256, dest="Spare")])
 
-add_insn("vmaskmovps", "vmaskmov", modifiers=[0x2C])
-add_insn("vmaskmovpd", "vmaskmov", modifiers=[0x2D])
+add_insn("vmaskmovps", "vmaskmov", modifiers=[0x2C], cpu=["AVX"])
+add_insn("vmaskmovpd", "vmaskmov", modifiers=[0x2D], cpu=["AVX"])
 
 add_group("vpermil",
     cpu=["AVX"],
@@ -6543,6 +6810,315 @@ add_group("vperm2f128",
 add_insn("vperm2f128", "vperm2f128")
 
 #####################################################################
+# Intel AVX2 instructions
+#####################################################################
+
+# Most AVX2 instructions are mixed in with above SSEx/AVX groups.
+# Some make more sense to have separate groups.
+
+# vex.vvvv=1111b
+add_group("vperm_var_avx2",
+    cpu=["AVX2"],
+    modifiers=["Op2Add"],
+    vex=256,
+    vexw=0,
+    prefix=0x66,
+    opcode=[0x0F, 0x38, 0x00],
+    operands=[Operand(type="SIMDReg", size=256, dest="Spare"),
+              Operand(type="SIMDReg", size=256, dest="VEX"),
+              Operand(type="SIMDRM", size=256, relaxed=True, dest="EA")])
+
+add_insn("vpermd",     "vperm_var_avx2", modifiers=[0x36])
+add_insn("vpermps",    "vperm_var_avx2", modifiers=[0x16])
+
+# vex.vvvv=1111b
+add_group("vperm_imm_avx2",
+    cpu=["AVX2"],
+    modifiers=["Op2Add"],
+    vex=256,
+    vexw=1,
+    prefix=0x66,
+    opcode=[0x0F, 0x3A, 0x00],
+    operands=[Operand(type="SIMDReg", size=256, dest="Spare"),
+              Operand(type="SIMDRM", size=256, relaxed=True, dest="EA"),
+              Operand(type="Imm", size=8, relaxed=True, dest="Imm")])
+
+add_insn("vpermq",     "vperm_imm_avx2", modifiers=[0x00])
+add_insn("vpermpd",    "vperm_imm_avx2", modifiers=[0x01])
+
+add_group("vperm2i128_avx2",
+    cpu=["AVX2"],
+    vex=256,
+    prefix=0x66,
+    opcode=[0x0F, 0x3A, 0x46],
+    operands=[Operand(type="SIMDReg", size=256, dest="Spare"),
+              Operand(type="SIMDReg", size=256, dest="VEX"),
+              Operand(type="SIMDRM", size=256, relaxed=True, dest="EA"),
+              Operand(type="Imm", size=8, relaxed=True, dest="Imm")])
+
+add_insn("vperm2i128", "vperm2i128_avx2")
+
+# vex.vvvv=1111b
+for sz in [128, 256]:
+    add_group("vpbroadcastb_avx2",
+        cpu=["AVX2"],
+        vex=sz,
+        vexw=0,
+        prefix=0x66,
+        opcode=[0x0F, 0x38, 0x78],
+        operands=[Operand(type="SIMDReg", size=sz, dest="Spare"),
+                  Operand(type="SIMDReg", size=128, relaxed=True, dest="EA")])
+# vex.vvvv=1111b
+for sz in [128, 256]:
+    add_group("vpbroadcastb_avx2",
+        cpu=["AVX2"],
+        vex=sz,
+        vexw=0,
+        prefix=0x66,
+        opcode=[0x0F, 0x38, 0x78],
+        operands=[Operand(type="SIMDReg", size=sz, dest="Spare"),
+                  Operand(type="RM", size=8, relaxed=True, dest="EA")])
+
+add_insn("vpbroadcastb", "vpbroadcastb_avx2")
+
+# vex.vvvv=1111b
+for sz in [128, 256]:
+    add_group("vpbroadcastw_avx2",
+        cpu=["AVX2"],
+        vex=sz,
+        vexw=0,
+        prefix=0x66,
+        opcode=[0x0F, 0x38, 0x79],
+        operands=[Operand(type="SIMDReg", size=sz, dest="Spare"),
+                  Operand(type="SIMDReg", size=128, relaxed=True, dest="EA")])
+# vex.vvvv=1111b
+for sz in [128, 256]:
+    add_group("vpbroadcastw_avx2",
+        cpu=["AVX2"],
+        vex=sz,
+        vexw=0,
+        prefix=0x66,
+        opcode=[0x0F, 0x38, 0x79],
+        operands=[Operand(type="SIMDReg", size=sz, dest="Spare"),
+                  Operand(type="RM", size=16, relaxed=True, dest="EA")])
+
+add_insn("vpbroadcastw", "vpbroadcastw_avx2")
+
+# vex.vvvv=1111b
+for sz in [128, 256]:
+    add_group("vpbroadcastd_avx2",
+        cpu=["AVX2"],
+        vex=sz,
+        vexw=0,
+        prefix=0x66,
+        opcode=[0x0F, 0x38, 0x58],
+        operands=[Operand(type="SIMDReg", size=sz, dest="Spare"),
+                  Operand(type="SIMDReg", size=128, relaxed=True, dest="EA")])
+# vex.vvvv=1111b
+for sz in [128, 256]:
+    add_group("vpbroadcastd_avx2",
+        cpu=["AVX2"],
+        vex=sz,
+        vexw=0,
+        prefix=0x66,
+        opcode=[0x0F, 0x38, 0x58],
+        operands=[Operand(type="SIMDReg", size=sz, dest="Spare"),
+                  Operand(type="RM", size=32, relaxed=True, dest="EA")])
+
+add_insn("vpbroadcastd", "vpbroadcastd_avx2")
+
+# vex.vvvv=1111b
+for sz in [128, 256]:
+    add_group("vpbroadcastq_avx2",
+        cpu=["AVX2"],
+        vex=sz,
+        vexw=0,
+        prefix=0x66,
+        opcode=[0x0F, 0x38, 0x59],
+        operands=[Operand(type="SIMDReg", size=sz, dest="Spare"),
+                  Operand(type="SIMDReg", size=128, relaxed=True, dest="EA")])
+# vex.vvvv=1111b
+for sz in [128, 256]:
+    add_group("vpbroadcastq_avx2",
+        cpu=["AVX2"],
+        vex=sz,
+        vexw=0,
+        prefix=0x66,
+        opcode=[0x0F, 0x38, 0x59],
+        operands=[Operand(type="SIMDReg", size=sz, dest="Spare"),
+                  Operand(type="RM", size=64, relaxed=True, dest="EA")])
+
+add_insn("vpbroadcastq", "vpbroadcastq_avx2")
+
+for sz in [128, 256]:
+    add_group("vpshiftv_vexw0_avx2",
+        cpu=["AVX2"],
+        modifiers=["Op2Add"],
+        vex=sz,
+        vexw=0,
+        prefix=0x66,
+        opcode=[0x0F, 0x38, 0x00],
+        operands=[Operand(type="SIMDReg", size=sz, dest="Spare"),
+                  Operand(type="SIMDReg", size=sz, dest="VEX"),
+                  Operand(type="SIMDRM", size=sz, relaxed=True, dest="EA")])
+
+for sz in [128, 256]:
+    add_group("vpshiftv_vexw1_avx2",
+        cpu=["AVX2"],
+        modifiers=["Op2Add"],
+        vex=sz,
+        vexw=1,
+        prefix=0x66,
+        opcode=[0x0F, 0x38, 0x00],
+        operands=[Operand(type="SIMDReg", size=sz, dest="Spare"),
+                  Operand(type="SIMDReg", size=sz, dest="VEX"),
+                  Operand(type="SIMDRM", size=sz, relaxed=True, dest="EA")])
+
+add_insn("vpsrlvd", "vpshiftv_vexw0_avx2", modifiers=[0x45])
+add_insn("vpsrlvq", "vpshiftv_vexw1_avx2", modifiers=[0x45])
+add_insn("vpsravd", "vpshiftv_vexw0_avx2", modifiers=[0x46])
+
+add_insn("vpsllvd", "vpshiftv_vexw0_avx2", modifiers=[0x47])
+add_insn("vpsllvq", "vpshiftv_vexw1_avx2", modifiers=[0x47])
+
+add_insn("vpmaskmovd", "vmaskmov", modifiers=[0x8C], cpu=["AVX2"])
+
+# vex.vvvv=1111b
+for sz in [128, 256]:
+    add_group("vmaskmov_vexw1_avx2",
+        cpu=["AVX2"],
+        modifiers=["Op2Add"],
+        vex=sz,
+        vexw=1,
+        prefix=0x66,
+        opcode=[0x0F, 0x38, 0x00],
+        operands=[Operand(type="SIMDReg", size=sz, dest="Spare"),
+                  Operand(type="SIMDReg", size=sz, dest="VEX"),
+                  Operand(type="SIMDRM", size=sz, relaxed=True, dest="EA")])
+ 
+for sz in [128, 256]:
+    add_group("vmaskmov_vexw1_avx2",
+        cpu=["AVX2"],
+        modifiers=["Op2Add"],
+        vex=sz,
+        vexw=1,
+        prefix=0x66,
+        opcode=[0x0F, 0x38, 0x02],
+        operands=[Operand(type="SIMDRM", size=sz, relaxed=True, dest="EA"),
+                  Operand(type="SIMDReg", size=sz, dest="VEX"),
+                  Operand(type="SIMDReg", size=sz, dest="Spare")])
+ 
+add_insn("vpmaskmovq", "vmaskmov_vexw1_avx2", modifiers=[0x8C])
+
+for sz in [128, 256]:
+    add_group("vex_66_0F3A_imm8_avx2",
+        cpu=["AVX2"],
+        modifiers=["Op2Add"],
+        vex=sz,
+        vexw=0,
+        prefix=0x66,
+        opcode=[0x0F, 0x3A, 0x00],
+        operands=[Operand(type="SIMDReg", size=sz, dest="Spare"),
+                  Operand(type="SIMDReg", size=sz, dest="VEX"),
+                  Operand(type="SIMDRM", size=sz, relaxed=True, dest="EA"),
+                  Operand(type="Imm", size=8, relaxed=True, dest="Imm")])
+
+add_insn("vpblendd", "vex_66_0F3A_imm8_avx2", modifiers=[0x02]) 
+
+# Vector register in EA.
+add_group("gather_64x_64x",
+    cpu=["AVX2"],
+    modifiers=["Op2Add"],
+    vex=128,
+    vexw=1,
+    prefix=0x66,
+    opcode=[0x0F, 0x38, 0x00],
+    operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
+              Operand(type="MemXMMIndex", size=64, relaxed=True, dest="EA"),
+              Operand(type="SIMDReg", size=128, dest="VEX")])
+add_group("gather_64x_64x",
+    cpu=["AVX2"],
+    modifiers=["Op2Add"],
+    vex=256,
+    vexw=1,
+    prefix=0x66,
+    opcode=[0x0F, 0x38, 0x00],
+    operands=[Operand(type="SIMDReg", size=256, dest="Spare"),
+              Operand(type="MemXMMIndex", size=64, relaxed=True, dest="EA"),
+              Operand(type="SIMDReg", size=256, dest="VEX")])
+add_insn("vgatherdpd", "gather_64x_64x", modifiers=[0x92])
+add_insn("vpgatherdq", "gather_64x_64x", modifiers=[0x90])
+
+add_group("gather_64x_64y",
+    cpu=["AVX2"],
+    modifiers=["Op2Add"],
+    vex=128,
+    vexw=1,
+    prefix=0x66,
+    opcode=[0x0F, 0x38, 0x00],
+    operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
+              Operand(type="MemXMMIndex", size=64, relaxed=True, dest="EA"),
+              Operand(type="SIMDReg", size=128, dest="VEX")])
+add_group("gather_64x_64y",
+    cpu=["AVX2"],
+    modifiers=["Op2Add"],
+    vex=256,
+    vexw=1,
+    prefix=0x66,
+    opcode=[0x0F, 0x38, 0x00],
+    operands=[Operand(type="SIMDReg", size=256, dest="Spare"),
+              Operand(type="MemYMMIndex", size=64, relaxed=True, dest="EA"),
+              Operand(type="SIMDReg", size=256, dest="VEX")])
+add_insn("vgatherqpd", "gather_64x_64y", modifiers=[0x93])
+add_insn("vpgatherqq", "gather_64x_64y", modifiers=[0x91])
+
+add_group("gather_32x_32y",
+    cpu=["AVX2"],
+    modifiers=["Op2Add"],
+    vex=128,
+    vexw=0,
+    prefix=0x66,
+    opcode=[0x0F, 0x38, 0x00],
+    operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
+              Operand(type="MemXMMIndex", size=32, relaxed=True, dest="EA"),
+              Operand(type="SIMDReg", size=128, dest="VEX")])
+add_group("gather_32x_32y",
+    cpu=["AVX2"],
+    modifiers=["Op2Add"],
+    vex=256,
+    vexw=0,
+    prefix=0x66,
+    opcode=[0x0F, 0x38, 0x00],
+    operands=[Operand(type="SIMDReg", size=256, dest="Spare"),
+              Operand(type="MemYMMIndex", size=32, relaxed=True, dest="EA"),
+              Operand(type="SIMDReg", size=256, dest="VEX")])
+add_insn("vgatherdps", "gather_32x_32y", modifiers=[0x92])
+add_insn("vpgatherdd", "gather_32x_32y", modifiers=[0x90])
+
+add_group("gather_32x_32y_128",
+    cpu=["AVX2"],
+    modifiers=["Op2Add"],
+    vex=128,
+    vexw=0,
+    prefix=0x66,
+    opcode=[0x0F, 0x38, 0x00],
+    operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
+              Operand(type="MemXMMIndex", size=32, relaxed=True, dest="EA"),
+              Operand(type="SIMDReg", size=128, dest="VEX")])
+add_group("gather_32x_32y_128",
+    cpu=["AVX2"],
+    modifiers=["Op2Add"],
+    vex=256,
+    vexw=0,
+    prefix=0x66,
+    opcode=[0x0F, 0x38, 0x00],
+    operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
+              Operand(type="MemYMMIndex", size=32, relaxed=True, dest="EA"),
+              Operand(type="SIMDReg", size=128, dest="VEX")])
+add_insn("vgatherqps", "gather_32x_32y_128", modifiers=[0x93])
+add_insn("vpgatherqd", "gather_32x_32y_128", modifiers=[0x91])
+
+#####################################################################
 # Intel FMA instructions
 #####################################################################
 
@@ -6568,7 +7144,7 @@ add_group("vfma_ps",
               Operand(type="SIMDReg", size=256, dest="VEX"),
               Operand(type="SIMDRM", size=256, relaxed=True, dest="EA")])
 
-### 128/256b FMA PD(W=1) 
+### 128/256b FMA PD(W=1)
 add_group("vfma_pd",
     cpu=["FMA"],
     modifiers=["Op2Add"],
@@ -7314,6 +7890,115 @@ for sz in (16, 32, 64):
 add_insn("movbe", "movbe")
 
 #####################################################################
+# Intel advanced bit manipulations (BMI1/2)
+#####################################################################
+
+add_insn("tzcnt", "cnt", modifiers=[0xBC], cpu=["BMI1"])
+# LZCNT is present as AMD ext
+
+for sfx, sz in zip("wlq", [32, 64]):
+    add_group("vex_gpr_ndd_rm_0F38_regext",
+        suffix=sfx,
+        modifiers=["PreAdd", "Op2Add", "SpAdd" ],
+        opersize=sz,
+        prefix=0x00,
+        opcode=[0x0F, 0x38, 0x00],
+        vex=0, ## VEX.L=0
+        operands=[Operand(type="Reg", size=sz, dest="VEX"),
+                  Operand(type="RM", size=sz, relaxed=True, dest="EA")])
+
+
+add_insn("blsr",   "vex_gpr_ndd_rm_0F38_regext", modifiers=[0x00, 0xF3, 1],
+         cpu=["BMI1"])
+add_insn("blsmsk", "vex_gpr_ndd_rm_0F38_regext", modifiers=[0x00, 0xF3, 2],
+         cpu=["BMI1"])
+add_insn("blsi",   "vex_gpr_ndd_rm_0F38_regext", modifiers=[0x00, 0xF3, 3],
+         cpu=["BMI1"])
+
+for sfx, sz in zip("wlq", [32, 64]):
+    add_group("vex_gpr_reg_rm_0F_imm8",
+        suffix=sfx,
+        modifiers=["PreAdd", "Op1Add", "Op2Add"],
+        opersize=sz,
+        prefix=0x00,
+        opcode=[0x0F, 0x00, 0x00],
+        vex=0, ## VEX.L=0
+        operands=[Operand(type="Reg", size=sz, dest="Spare"),
+                  Operand(type="RM", size=sz, relaxed=True, dest="EA"),
+                  Operand(type="Imm", size=8, relaxed=True, dest="Imm")])
+
+add_insn("rorx", "vex_gpr_reg_rm_0F_imm8", modifiers=[0xF2, 0x3A, 0xF0],
+         cpu=["BMI2"])
+
+for sfx, sz in zip("lq", [32, 64]):  # no 16-bit forms
+    add_group("vex_gpr_reg_nds_rm_0F",
+        suffix=sfx,
+        modifiers=["PreAdd", "Op1Add", "Op2Add"],
+        opersize=sz,
+        prefix=0x00,
+        opcode=[0x0F, 0x00, 0x00],
+        vex=0,
+        operands=[Operand(type="Reg", size=sz, dest="Spare"),
+                  Operand(type="Reg", size=sz, dest="VEX"),
+                  Operand(type="RM", size=sz, relaxed=True, dest="EA")])
+
+add_insn("andn", "vex_gpr_reg_nds_rm_0F", modifiers=[0x00, 0x38, 0xF2],
+         cpu=["BMI1"])
+
+add_insn("pdep", "vex_gpr_reg_nds_rm_0F", modifiers=[0xF2, 0x38, 0xF5],
+         cpu=["BMI2"])
+add_insn("pext", "vex_gpr_reg_nds_rm_0F", modifiers=[0xF3, 0x38, 0xF5],
+         cpu=["BMI2"])
+
+for sfx, sz in zip("lq", [32, 64]):  # no 16-bit forms
+    add_group("vex_gpr_reg_rm_nds_0F",
+        suffix=sfx,
+        modifiers=["PreAdd", "Op1Add", "Op2Add"],
+        opersize=sz,
+        prefix=0x00,
+        opcode=[0x0F, 0x00, 0x00],
+        vex=0,
+        operands=[Operand(type="Reg", size=sz, dest="Spare"),
+                  Operand(type="RM", size=sz, relaxed=True, dest="EA"),
+                  Operand(type="Reg", size=sz, dest="VEX")])
+
+add_insn("bzhi", "vex_gpr_reg_rm_nds_0F", modifiers=[0x00, 0x38, 0xF5],
+         cpu=["BMI2"])
+add_insn("bextr","vex_gpr_reg_rm_nds_0F", modifiers=[0x00, 0x38, 0xF7],
+         cpu=["BMI1"])
+add_insn("shlx", "vex_gpr_reg_rm_nds_0F", modifiers=[0x66, 0x38, 0xF7],
+         cpu=["BMI2"])
+add_insn("shrx", "vex_gpr_reg_rm_nds_0F", modifiers=[0xF2, 0x38, 0xF7],
+         cpu=["BMI2"])
+add_insn("sarx", "vex_gpr_reg_rm_nds_0F", modifiers=[0xF3, 0x38, 0xF7],
+         cpu=["BMI2"])
+
+add_insn("mulx", "vex_gpr_reg_nds_rm_0F", modifiers=[0xF2, 0x38, 0xF6],
+         cpu=["BMI2"])
+
+
+
+#####################################################################
+# Intel INVPCID instruction
+#####################################################################
+add_group("invpcid",
+    cpu=["INVPCID", "Priv"],
+    not64=True,
+    prefix=0x66,
+    opcode=[0x0F, 0x38, 0x82],
+    operands=[Operand(type="Reg", size=32, dest="Spare"),
+              Operand(type="Mem", size=128, relaxed=True, dest="EA")])
+add_group("invpcid",
+    cpu=["INVPCID", "Priv"],
+    only64=True,
+    def_opersize_64=64,
+    prefix=0x66,
+    opcode=[0x0F, 0x38, 0x82],
+    operands=[Operand(type="Reg", size=64, dest="Spare"),
+              Operand(type="Mem", size=128, relaxed=True, dest="EA")])
+add_insn("invpcid", "invpcid")
+
+#####################################################################
 # AMD 3DNow! instructions
 #####################################################################
 
@@ -7361,7 +8046,7 @@ add_insn("syscall", "twobyte", modifiers=[0x0F, 0x05], cpu=["686", "AMD"])
 for sfx in [None, "l", "q"]:
     add_insn("sysret"+(sfx or ""), "twobyte", suffix=sfx, modifiers=[0x0F, 0x07],
              cpu=["686", "AMD", "Priv"])
-add_insn("lzcnt", "cnt", modifiers=[0xBD], cpu=["686", "AMD"])
+add_insn("lzcnt", "cnt", modifiers=[0xBD], cpu=["LZCNT"])
 
 #####################################################################
 # AMD x86-64 extensions
@@ -7649,3 +8334,4 @@ if len(sys.argv) > 1:
 output_groups(file(os.path.join(out_dir, "x86insns.c"), "wt"))
 output_gas_insns(file(os.path.join(out_dir, "x86insn_gas.gperf"), "wt"))
 output_nasm_insns(file(os.path.join(out_dir, "x86insn_nasm.gperf"), "wt"))
+
diff --git a/modules/arch/x86/x86arch.c b/modules/arch/x86/x86arch.c
index ab0901d..833e94c 100644
--- a/modules/arch/x86/x86arch.c
+++ b/modules/arch/x86/x86arch.c
@@ -25,7 +25,6 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include <util.h>
-/*@unused@*/ RCSID("$Id: x86arch.c 2279 2010-01-19 07:57:43Z peter $");
 
 #include <libyasm.h>
 
diff --git a/modules/arch/x86/x86arch.h b/modules/arch/x86/x86arch.h
index bb9a814..0c387f7 100644
--- a/modules/arch/x86/x86arch.h
+++ b/modules/arch/x86/x86arch.h
@@ -1,4 +1,4 @@
-/* $Id: x86arch.h 2346 2010-08-01 01:37:37Z peter $
+/*
  * x86 Architecture header file
  *
  *  Copyright (C) 2001-2007  Peter Johnson
@@ -78,6 +78,11 @@
 #define CPU_XSAVEOPT 44     /* Intel XSAVEOPT instruction */
 #define CPU_EPTVPID 45      /* Intel INVEPT, INVVPID instructions */
 #define CPU_SMX     46      /* Intel SMX instruction (GETSEC) */
+#define CPU_AVX2    47      /* Intel AVX2 instructions */
+#define CPU_BMI1    48      /* Intel BMI1 instructions */
+#define CPU_BMI2    49      /* Intel BMI2 instructions */
+#define CPU_INVPCID 50      /* Intel INVPCID instruction */
+#define CPU_LZCNT   51      /* Intel LZCNT instruction */
 
 enum x86_parser_type {
     X86_PARSER_NASM = 0,
@@ -172,6 +177,9 @@ int yasm_x86__set_rex_from_reg(unsigned char *rex, unsigned char *low3,
 typedef struct x86_effaddr {
     yasm_effaddr ea;            /* base structure */
 
+    /* VSIB uses the normal SIB byte, but this flag enables it. */
+    unsigned char vsib_mode;    /* 0 if not, 1 if XMM, 2 if YMM */
+
     /* How the spare (register) bits in Mod/RM are handled:
      * Even if valid_modrm=0, the spare bits are still valid (don't overwrite!)
      * They're set in bytecode_create_insn().
diff --git a/modules/arch/x86/x86bc.c b/modules/arch/x86/x86bc.c
index be5af13..1670df7 100644
--- a/modules/arch/x86/x86bc.c
+++ b/modules/arch/x86/x86bc.c
@@ -25,7 +25,6 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include <util.h>
-/*@unused@*/ RCSID("$Id: x86bc.c 2279 2010-01-19 07:57:43Z peter $");
 
 #include <libyasm.h>
 
@@ -44,6 +43,7 @@ static int x86_bc_insn_expand(yasm_bytecode *bc, int span, long old_val,
                               long new_val, /*@out@*/ long *neg_thres,
                               /*@out@*/ long *pos_thres);
 static int x86_bc_insn_tobytes(yasm_bytecode *bc, unsigned char **bufp,
+                               unsigned char *bufstart,
                                void *d, yasm_output_value_func output_value,
                                /*@null@*/ yasm_output_reloc_func output_reloc);
 
@@ -56,6 +56,7 @@ static int x86_bc_jmp_expand(yasm_bytecode *bc, int span, long old_val,
                              long new_val, /*@out@*/ long *neg_thres,
                              /*@out@*/ long *pos_thres);
 static int x86_bc_jmp_tobytes(yasm_bytecode *bc, unsigned char **bufp,
+                              unsigned char *bufstart,
                               void *d, yasm_output_value_func output_value,
                               /*@null@*/ yasm_output_reloc_func output_reloc);
 
@@ -66,7 +67,7 @@ static int x86_bc_jmpfar_calc_len(yasm_bytecode *bc,
                                   yasm_bc_add_span_func add_span,
                                   void *add_span_data);
 static int x86_bc_jmpfar_tobytes
-    (yasm_bytecode *bc, unsigned char **bufp, void *d,
+    (yasm_bytecode *bc, unsigned char **bufp, unsigned char *bufstart, void *d,
      yasm_output_value_func output_value,
      /*@null@*/ yasm_output_reloc_func output_reloc);
 
@@ -189,6 +190,7 @@ ea_create(void)
     x86_ea->ea.pc_rel = 0;
     x86_ea->ea.not_pc_rel = 0;
     x86_ea->ea.data_len = 0;
+    x86_ea->vsib_mode = 0;
     x86_ea->modrm = 0;
     x86_ea->valid_modrm = 0;
     x86_ea->need_modrm = 0;
@@ -380,6 +382,8 @@ yasm_x86__ea_print(const yasm_effaddr *ea, FILE *f, int indent_level)
     fprintf(f, "%*sNoSplit=%u\n", indent_level, "", (unsigned int)ea->nosplit);
     fprintf(f, "%*sSegmentOv=%02x\n", indent_level, "",
             (unsigned int)x86_ea->ea.segreg);
+    fprintf(f, "%*sVSIBMode=%u\n", indent_level, "",
+            (unsigned int)x86_ea->vsib_mode);
     fprintf(f, "%*sModRM=%03o ValidRM=%u NeedRM=%u\n", indent_level, "",
             (unsigned int)x86_ea->modrm, (unsigned int)x86_ea->valid_modrm,
             (unsigned int)x86_ea->need_modrm);
@@ -800,14 +804,14 @@ x86_opcode_tobytes(const x86_opcode *opcode, unsigned char **bufp)
 }
 
 static int
-x86_bc_insn_tobytes(yasm_bytecode *bc, unsigned char **bufp, void *d,
+x86_bc_insn_tobytes(yasm_bytecode *bc, unsigned char **bufp,
+                    unsigned char *bufstart, void *d,
                     yasm_output_value_func output_value,
                     /*@unused@*/ yasm_output_reloc_func output_reloc)
 {
     x86_insn *insn = (x86_insn *)bc->contents;
     /*@null@*/ x86_effaddr *x86_ea = (x86_effaddr *)insn->x86_ea;
     yasm_value *imm = insn->imm;
-    unsigned char *bufp_orig = *bufp;
 
     /* Prefixes */
     x86_common_tobytes(&insn->common, bufp,
@@ -874,7 +878,7 @@ x86_bc_insn_tobytes(yasm_bytecode *bc, unsigned char **bufp, void *d,
                                          yasm_expr_int(delta), bc->line);
             }
             if (output_value(&x86_ea->ea.disp, *bufp, disp_len,
-                             (unsigned long)(*bufp-bufp_orig), bc, 1, d))
+                             (unsigned long)(*bufp-bufstart), bc, 1, d))
                 return 1;
             *bufp += disp_len;
         }
@@ -892,7 +896,7 @@ x86_bc_insn_tobytes(yasm_bytecode *bc, unsigned char **bufp, void *d,
             imm_len = 1;
         } else
             imm_len = imm->size/8;
-        if (output_value(imm, *bufp, imm_len, (unsigned long)(*bufp-bufp_orig),
+        if (output_value(imm, *bufp, imm_len, (unsigned long)(*bufp-bufstart),
                          bc, 1, d))
             return 1;
         *bufp += imm_len;
@@ -902,14 +906,14 @@ x86_bc_insn_tobytes(yasm_bytecode *bc, unsigned char **bufp, void *d,
 }
 
 static int
-x86_bc_jmp_tobytes(yasm_bytecode *bc, unsigned char **bufp, void *d,
+x86_bc_jmp_tobytes(yasm_bytecode *bc, unsigned char **bufp,
+                   unsigned char *bufstart, void *d,
                    yasm_output_value_func output_value,
                    /*@unused@*/ yasm_output_reloc_func output_reloc)
 {
     x86_jmp *jmp = (x86_jmp *)bc->contents;
     unsigned char opersize;
     unsigned int i;
-    unsigned char *bufp_orig = *bufp;
     /*@only@*/ yasm_intnum *delta;
 
     /* Prefixes */
@@ -944,7 +948,7 @@ x86_bc_jmp_tobytes(yasm_bytecode *bc, unsigned char **bufp, void *d,
             jmp->target.size = 8;
             jmp->target.sign = 1;
             if (output_value(&jmp->target, *bufp, 1,
-                             (unsigned long)(*bufp-bufp_orig), bc, 1, d))
+                             (unsigned long)(*bufp-bufstart), bc, 1, d))
                 return 1;
             *bufp += 1;
             break;
@@ -976,7 +980,7 @@ x86_bc_jmp_tobytes(yasm_bytecode *bc, unsigned char **bufp, void *d,
             jmp->target.size = i*8;
             jmp->target.sign = 1;
             if (output_value(&jmp->target, *bufp, i,
-                             (unsigned long)(*bufp-bufp_orig), bc, 1, d))
+                             (unsigned long)(*bufp-bufstart), bc, 1, d))
                 return 1;
             *bufp += i;
             break;
@@ -989,13 +993,13 @@ x86_bc_jmp_tobytes(yasm_bytecode *bc, unsigned char **bufp, void *d,
 }
 
 static int
-x86_bc_jmpfar_tobytes(yasm_bytecode *bc, unsigned char **bufp, void *d,
+x86_bc_jmpfar_tobytes(yasm_bytecode *bc, unsigned char **bufp,
+                      unsigned char *bufstart, void *d,
                       yasm_output_value_func output_value,
                       /*@unused@*/ yasm_output_reloc_func output_reloc)
 {
     x86_jmpfar *jmpfar = (x86_jmpfar *)bc->contents;
     unsigned int i;
-    unsigned char *bufp_orig = *bufp;
     unsigned char opersize;
 
     x86_common_tobytes(&jmpfar->common, bufp, 0);
@@ -1009,12 +1013,12 @@ x86_bc_jmpfar_tobytes(yasm_bytecode *bc, unsigned char **bufp, void *d,
     i = (opersize == 16) ? 2 : 4;
     jmpfar->offset.size = i*8;
     if (output_value(&jmpfar->offset, *bufp, i,
-                     (unsigned long)(*bufp-bufp_orig), bc, 1, d))
+                     (unsigned long)(*bufp-bufstart), bc, 1, d))
         return 1;
     *bufp += i;
     jmpfar->segment.size = 16;
     if (output_value(&jmpfar->segment, *bufp, 2,
-                     (unsigned long)(*bufp-bufp_orig), bc, 1, d))
+                     (unsigned long)(*bufp-bufstart), bc, 1, d))
         return 1;
     *bufp += 2;
 
diff --git a/modules/arch/x86/x86cpu.gperf b/modules/arch/x86/x86cpu.gperf
index 944a229..669a588 100644
--- a/modules/arch/x86/x86cpu.gperf
+++ b/modules/arch/x86/x86cpu.gperf
@@ -25,7 +25,6 @@
 # POSSIBILITY OF SUCH DAMAGE.
 %{
 #include <util.h>
-RCSID("$Id: x86cpu.gperf 2346 2010-08-01 01:37:37Z peter $");
 
 #include <ctype.h>
 #include <libyasm.h>
@@ -389,6 +388,16 @@ eptvpid,	x86_cpu_set,	CPU_EPTVPID
 noeptvpid,	x86_cpu_clear,	CPU_EPTVPID
 smx,		x86_cpu_set,	CPU_SMX
 nosmx,		x86_cpu_clear,	CPU_SMX
+avx2,		x86_cpu_set,	CPU_AVX2
+noavx2,		x86_cpu_clear,	CPU_AVX2
+bmi1,		x86_cpu_set,	CPU_BMI1
+nobmi1,		x86_cpu_clear,	CPU_BMI1
+bmi2,		x86_cpu_set,	CPU_BMI2
+nobmi2,		x86_cpu_clear,	CPU_BMI2
+invpcid,	x86_cpu_set,	CPU_INVPCID
+noinvpcid,	x86_cpu_clear,	CPU_INVPCID
+lzcnt,		x86_cpu_set,	CPU_LZCNT
+nolzcnt,	x86_cpu_clear,	CPU_LZCNT
 # Change NOP patterns
 basicnop,	x86_nop,	X86_NOP_BASIC
 intelnop,	x86_nop,	X86_NOP_INTEL
diff --git a/modules/arch/x86/x86expr.c b/modules/arch/x86/x86expr.c
index fce5b26..85feb78 100644
--- a/modules/arch/x86/x86expr.c
+++ b/modules/arch/x86/x86expr.c
@@ -25,7 +25,6 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include <util.h>
-/*@unused@*/ RCSID("$Id: x86expr.c 2199 2009-05-10 05:24:46Z peter $");
 
 #include <libyasm.h>
 
@@ -34,6 +33,7 @@
 
 typedef struct x86_checkea_reg3264_data {
     int *regs;          /* total multiplier for each reg */
+    unsigned char vsib_mode;
     unsigned char bits;
     unsigned char addrsize;
 } x86_checkea_reg3264_data;
@@ -58,6 +58,20 @@ x86_expr_checkea_get_reg3264(yasm_expr__item *ei, int *regnum,
                 return 0;
             *regnum = (unsigned int)(ei->data.reg & 0xF);
             break;
+        case X86_XMMREG:
+            if (data->vsib_mode != 1)
+                return 0;
+            if (data->bits != 64 && (ei->data.reg & 0x8) == 0x8)
+                return 0;
+            *regnum = 17+(unsigned int)(ei->data.reg & 0xF);
+            break;
+        case X86_YMMREG:
+            if (data->vsib_mode != 2)
+                return 0;
+            if (data->bits != 64 && (ei->data.reg & 0x8) == 0x8)
+                return 0;
+            *regnum = 17+(unsigned int)(ei->data.reg & 0xF);
+            break;
         case X86_RIP:
             if (data->bits != 64)
                 return 0;
@@ -606,6 +620,11 @@ yasm_x86__expr_checkea(x86_effaddr *x86_ea, unsigned char *addrsize,
                 }
                 /*@fallthrough@*/
             default:
+                /* If SIB is required, but we're in 16-bit mode, set to 32. */
+                if (bits == 16 && x86_ea->need_sib == 1) {
+                    *addrsize = 32;
+                    break;
+                }
                 /* check for use of 16 or 32-bit registers; if none are used
                  * default to bits setting.
                  */
@@ -643,13 +662,19 @@ yasm_x86__expr_checkea(x86_effaddr *x86_ea, unsigned char *addrsize,
             REG64_R13,
             REG64_R14,
             REG64_R15,
-            REG64_RIP
+            REG64_RIP,
+            SIMDREGS
         } reg3264type;
-        int reg3264mult[17] = {0, 0, 0, 0, 0, 0, 0, 0,
-                               0, 0, 0, 0, 0, 0, 0, 0, 0};
+        int reg3264mult[33] =
+            {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+             0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
         x86_checkea_reg3264_data reg3264_data;
         int basereg = REG3264_NONE;     /* "base" register (for SIB) */
         int indexreg = REG3264_NONE;    /* "index" register (for SIB) */
+        int regcount = 17;              /* normally don't check SIMD regs */
+
+        if (x86_ea->vsib_mode != 0)
+            regcount = 33;
 
         /* We can only do 64-bit addresses in 64-bit mode. */
         if (*addrsize == 64 && bits != 64) {
@@ -665,6 +690,7 @@ yasm_x86__expr_checkea(x86_effaddr *x86_ea, unsigned char *addrsize,
         }
 
         reg3264_data.regs = reg3264mult;
+        reg3264_data.vsib_mode = x86_ea->vsib_mode;
         reg3264_data.bits = bits;
         reg3264_data.addrsize = *addrsize;
         if (x86_ea->ea.disp.abs) {
@@ -698,7 +724,7 @@ yasm_x86__expr_checkea(x86_effaddr *x86_ea, unsigned char *addrsize,
          * Also, if an indexreg hasn't been assigned, try to find one.
          * Meanwhile, check to make sure there's no negative register mults.
          */
-        for (i=0; i<17; i++) {
+        for (i=0; i<regcount; i++) {
             if (reg3264mult[i] < 0) {
                 yasm_error_set(YASM_ERROR_VALUE,
                                N_("invalid effective address"));
@@ -711,10 +737,26 @@ yasm_x86__expr_checkea(x86_effaddr *x86_ea, unsigned char *addrsize,
                 indexreg = i;
         }
 
-        /* Handle certain special cases of indexreg mults when basereg is
-         * empty.
-         */
-        if (indexreg != REG3264_NONE && basereg == REG3264_NONE)
+        if (x86_ea->vsib_mode != 0) {
+            /* For VSIB, the SIMD register needs to go into the indexreg.
+             * Also check basereg (must be a GPR if present) and indexreg
+             * (must be a SIMD register).
+             */
+            if (basereg >= SIMDREGS &&
+                (indexreg == REG3264_NONE || reg3264mult[indexreg] == 1)) {
+                int temp = basereg;
+                basereg = indexreg;
+                indexreg = temp;
+            }
+            if (basereg >= REG64_RIP || indexreg < SIMDREGS) {
+                yasm_error_set(YASM_ERROR_VALUE,
+                               N_("invalid effective address"));
+                return 1;
+            }
+        } else if (indexreg != REG3264_NONE && basereg == REG3264_NONE)
+            /* Handle certain special cases of indexreg mults when basereg is
+             * empty.
+             */
             switch (reg3264mult[indexreg]) {
                 case 1:
                     /* Only optimize this way if nosplit wasn't specified */
@@ -741,7 +783,7 @@ yasm_x86__expr_checkea(x86_effaddr *x86_ea, unsigned char *addrsize,
         /* Make sure there's no other registers than the basereg and indexreg
          * we just found.
          */
-        for (i=0; i<17; i++)
+        for (i=0; i<regcount; i++)
             if (i != basereg && i != indexreg && reg3264mult[i] != 0) {
                 yasm_error_set(YASM_ERROR_VALUE,
                                N_("invalid effective address"));
@@ -861,10 +903,17 @@ yasm_x86__expr_checkea(x86_effaddr *x86_ea, unsigned char *addrsize,
                 x86_ea->sib |= 040;
                 /* Any scale field is valid, just leave at 0. */
             else {
-                if (yasm_x86__set_rex_from_reg(rex, &low3, (unsigned int)
-                                               (X86_REG64 | indexreg), bits,
-                                               X86_REX_X))
-                    return 1;
+                if (indexreg >= SIMDREGS) {
+                    if (yasm_x86__set_rex_from_reg(rex, &low3,
+                            (unsigned int)(X86_XMMREG | (indexreg-SIMDREGS)),
+                            bits, X86_REX_X))
+                        return 1;
+                } else {
+                    if (yasm_x86__set_rex_from_reg(rex, &low3,
+                            (unsigned int)(X86_REG64 | indexreg),
+                            bits, X86_REX_X))
+                        return 1;
+                }
                 x86_ea->sib |= low3 << 3;
                 /* Set scale field, 1 case -> 0, so don't bother. */
                 switch (reg3264mult[indexreg]) {
diff --git a/modules/arch/x86/x86id.c b/modules/arch/x86/x86id.c
index e73cc8c..6e2042f 100644
--- a/modules/arch/x86/x86id.c
+++ b/modules/arch/x86/x86id.c
@@ -26,7 +26,6 @@
  */
 #include <ctype.h>
 #include <util.h>
-RCSID("$Id: x86id.c 2279 2010-01-19 07:57:43Z peter $");
 
 #include <libyasm.h>
 #include <libyasm/phash.h>
@@ -111,7 +110,11 @@ enum x86_operand_type {
      */
     OPT_MemrAX = 25,
     /* EAX memory operand only (EA) [special case for SVM skinit opcode] */
-    OPT_MemEAX = 26
+    OPT_MemEAX = 26,
+    /* XMM VSIB memory operand */
+    OPT_MemXMMIndex = 27,
+    /* YMM VSIB memory operand */
+    OPT_MemYMMIndex = 28
 };
 
 enum x86_operand_size {
@@ -347,6 +350,37 @@ static const yasm_bytecode_callback x86_id_insn_callback = {
 
 #include "x86insns.c"
 
+/* Looks for the first SIMD register match for the purposes of VSIB matching.
+ * Full legality checking is performed in EA code.
+ */
+static int
+x86_expr_contains_simd_cb(const yasm_expr__item *ei, void *d)
+{
+    int ymm = *((int *)d);
+    if (ei->type != YASM_EXPR_REG)
+        return 0;
+    switch ((x86_expritem_reg_size)(ei->data.reg & ~0xFUL)) {
+        case X86_XMMREG:
+            if (!ymm)
+                return 1;
+            break;
+        case X86_YMMREG:
+            if (ymm)
+                return 1;
+            break;
+        default:
+            break;
+    }
+    return 0;
+}
+
+static int
+x86_expr_contains_simd(const yasm_expr *e, int ymm)
+{
+    return yasm_expr__traverse_leaves_in_const(e, &ymm,
+                                               x86_expr_contains_simd_cb);
+}
+
 static void
 x86_finalize_common(x86_common *common, const x86_insn_info *info,
                     unsigned int mode_bits)
@@ -851,6 +885,16 @@ x86_find_match(x86_id_insn *id_insn, yasm_insn_operand **ops,
                         mismatch = 1;
                     break;
                 }
+                case OPT_MemXMMIndex:
+                    if (op->type != YASM_INSN__OPERAND_MEMORY ||
+                        !x86_expr_contains_simd(op->data.ea->disp.abs, 0))
+                        mismatch = 1;
+                    break;
+                case OPT_MemYMMIndex:
+                    if (op->type != YASM_INSN__OPERAND_MEMORY ||
+                        !x86_expr_contains_simd(op->data.ea->disp.abs, 1))
+                        mismatch = 1;
+                    break;
                 default:
                     yasm_internal_error(N_("invalid operand type"));
             }
@@ -1231,12 +1275,20 @@ x86_id_insn_finalize(yasm_bytecode *bc, yasm_bytecode *prev_bc)
                             if (info_ops[i].type == OPT_MemOffs)
                                 /* Special-case for MOV MemOffs instruction */
                                 yasm_x86__ea_set_disponly(insn->x86_ea);
-                            else if (id_insn->default_rel &&
-                                     !op->data.ea->not_pc_rel &&
-                                     op->data.ea->segreg != 0x6404 &&
-                                     op->data.ea->segreg != 0x6505 &&
-                                     !yasm_expr__contains(
-                                        op->data.ea->disp.abs, YASM_EXPR_REG))
+                            else if (info_ops[i].type == OPT_MemXMMIndex) {
+                                /* Remember VSIB mode */
+                                insn->x86_ea->vsib_mode = 1;
+                                insn->x86_ea->need_sib = 1;
+                            } else if (info_ops[i].type == OPT_MemYMMIndex) {
+                                /* Remember VSIB mode */
+                                insn->x86_ea->vsib_mode = 2;
+                                insn->x86_ea->need_sib = 1;
+                            } else if (id_insn->default_rel &&
+                                       !op->data.ea->not_pc_rel &&
+                                       op->data.ea->segreg != 0x6404 &&
+                                       op->data.ea->segreg != 0x6505 &&
+                                       !yasm_expr__contains(
+                                          op->data.ea->disp.abs, YASM_EXPR_REG))
                                 /* Enable default PC-rel if no regs and segreg
                                  * is not FS or GS.
                                  */
diff --git a/modules/arch/x86/x86regtmod.gperf b/modules/arch/x86/x86regtmod.gperf
index 1429586..64ee7d9 100644
--- a/modules/arch/x86/x86regtmod.gperf
+++ b/modules/arch/x86/x86regtmod.gperf
@@ -25,7 +25,6 @@
 # POSSIBILITY OF SUCH DAMAGE.
 %{
 #include <util.h>
-RCSID("$Id: x86regtmod.gperf 2061 2008-04-12 01:33:54Z peter $");
 
 #include <ctype.h>
 #include <libyasm.h>
diff --git a/modules/dbgfmts/codeview/cv-dbgfmt.c b/modules/dbgfmts/codeview/cv-dbgfmt.c
index 06dda54..9b06fe3 100644
--- a/modules/dbgfmts/codeview/cv-dbgfmt.c
+++ b/modules/dbgfmts/codeview/cv-dbgfmt.c
@@ -25,7 +25,6 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include <util.h>
-/*@unused@*/ RCSID("$Id: cv-dbgfmt.c 1894 2007-07-14 04:34:41Z peter $");
 
 #include <libyasm.h>
 
diff --git a/modules/dbgfmts/codeview/cv-dbgfmt.h b/modules/dbgfmts/codeview/cv-dbgfmt.h
index c7e82da..134b0b8 100644
--- a/modules/dbgfmts/codeview/cv-dbgfmt.h
+++ b/modules/dbgfmts/codeview/cv-dbgfmt.h
@@ -1,4 +1,4 @@
-/* $Id: cv-dbgfmt.h 1827 2007-04-22 05:09:49Z peter $
+/*
  * CodeView debugging formats implementation for Yasm
  *
  *  Copyright (C) 2006-2007  Peter Johnson
diff --git a/modules/dbgfmts/codeview/cv-symline.c b/modules/dbgfmts/codeview/cv-symline.c
index 133195b..2b71302 100644
--- a/modules/dbgfmts/codeview/cv-symline.c
+++ b/modules/dbgfmts/codeview/cv-symline.c
@@ -28,7 +28,6 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include <util.h>
-/*@unused@*/ RCSID("$Id: cv-symline.c 2258 2010-01-03 01:04:18Z peter $");
 
 #include <libyasm.h>
 
@@ -163,7 +162,7 @@ static void cv8_symhead_bc_print(const void *contents, FILE *f,
 static int cv8_symhead_bc_calc_len
     (yasm_bytecode *bc, yasm_bc_add_span_func add_span, void *add_span_data);
 static int cv8_symhead_bc_tobytes
-    (yasm_bytecode *bc, unsigned char **bufp, void *d,
+    (yasm_bytecode *bc, unsigned char **bufp, unsigned char *bufstart, void *d,
      yasm_output_value_func output_value,
      /*@null@*/ yasm_output_reloc_func output_reloc);
 
@@ -173,7 +172,7 @@ static void cv8_fileinfo_bc_print(const void *contents, FILE *f,
 static int cv8_fileinfo_bc_calc_len
     (yasm_bytecode *bc, yasm_bc_add_span_func add_span, void *add_span_data);
 static int cv8_fileinfo_bc_tobytes
-    (yasm_bytecode *bc, unsigned char **bufp, void *d,
+    (yasm_bytecode *bc, unsigned char **bufp, unsigned char *bufstart, void *d,
      yasm_output_value_func output_value,
      /*@null@*/ yasm_output_reloc_func output_reloc);
 
@@ -183,7 +182,7 @@ static void cv8_lineinfo_bc_print(const void *contents, FILE *f,
 static int cv8_lineinfo_bc_calc_len
     (yasm_bytecode *bc, yasm_bc_add_span_func add_span, void *add_span_data);
 static int cv8_lineinfo_bc_tobytes
-    (yasm_bytecode *bc, unsigned char **bufp, void *d,
+    (yasm_bytecode *bc, unsigned char **bufp, unsigned char *bufstart, void *d,
      yasm_output_value_func output_value,
      /*@null@*/ yasm_output_reloc_func output_reloc);
 
@@ -192,7 +191,7 @@ static void cv_sym_bc_print(const void *contents, FILE *f, int indent_level);
 static int cv_sym_bc_calc_len
     (yasm_bytecode *bc, yasm_bc_add_span_func add_span, void *add_span_data);
 static int cv_sym_bc_tobytes
-    (yasm_bytecode *bc, unsigned char **bufp, void *d,
+    (yasm_bytecode *bc, unsigned char **bufp, unsigned char *bufstart, void *d,
      yasm_output_value_func output_value,
      /*@null@*/ yasm_output_reloc_func output_reloc);
 
@@ -638,9 +637,12 @@ yasm_cv__generate_symline(yasm_object *object, yasm_linemap *linemap,
     /* add object and compile flag first */
     cv8_add_sym_objname(info.debug_symline,
                         yasm__abspath(object->obj_filename));
-    cv8_add_sym_compile(object, info.debug_symline,
-                        yasm__xstrdup(PACKAGE_NAME " " PACKAGE_INTVER "."
-                                      PACKAGE_BUILD));
+    if (getenv("YASM_TEST_SUITE"))
+        cv8_add_sym_compile(object, info.debug_symline,
+                            yasm__xstrdup("yasm HEAD"));
+    else
+        cv8_add_sym_compile(object, info.debug_symline,
+                            yasm__xstrdup(PACKAGE_STRING));
     /* then iterate through symbol table */
     yasm_symtab_traverse(object->symtab, &info, cv_generate_sym);
     cv8_set_symhead_end(head, yasm_section_bcs_last(info.debug_symline));
@@ -724,7 +726,8 @@ cv8_symhead_bc_calc_len(yasm_bytecode *bc, yasm_bc_add_span_func add_span,
 }
 
 static int
-cv8_symhead_bc_tobytes(yasm_bytecode *bc, unsigned char **bufp, void *d,
+cv8_symhead_bc_tobytes(yasm_bytecode *bc, unsigned char **bufp,
+                       unsigned char *bufstart, void *d,
                        yasm_output_value_func output_value,
                        yasm_output_reloc_func output_reloc)
 {
@@ -797,7 +800,8 @@ cv8_fileinfo_bc_calc_len(yasm_bytecode *bc, yasm_bc_add_span_func add_span,
 }
 
 static int
-cv8_fileinfo_bc_tobytes(yasm_bytecode *bc, unsigned char **bufp, void *d,
+cv8_fileinfo_bc_tobytes(yasm_bytecode *bc, unsigned char **bufp,
+                        unsigned char *bufstart, void *d,
                         yasm_output_value_func output_value,
                         yasm_output_reloc_func output_reloc)
 {
@@ -864,7 +868,8 @@ cv8_lineinfo_bc_calc_len(yasm_bytecode *bc, yasm_bc_add_span_func add_span,
 }
 
 static int
-cv8_lineinfo_bc_tobytes(yasm_bytecode *bc, unsigned char **bufp, void *d,
+cv8_lineinfo_bc_tobytes(yasm_bytecode *bc, unsigned char **bufp,
+                        unsigned char *bufstart, void *d,
                         yasm_output_value_func output_value,
                         yasm_output_reloc_func output_reloc)
 {
@@ -876,7 +881,8 @@ cv8_lineinfo_bc_tobytes(yasm_bytecode *bc, unsigned char **bufp, void *d,
     cv8_lineset *ls;
 
     /* start offset and section */
-    cv_out_sym(li->sectsym, 0, bc, &buf, d, output_value);
+    cv_out_sym(li->sectsym, (unsigned long)(buf - bufstart), bc, &buf,
+               d, output_value);
 
     /* Two bytes of pad/alignment */
     YASM_WRITE_8(buf, 0);
@@ -1019,7 +1025,8 @@ cv_sym_bc_calc_len(yasm_bytecode *bc, yasm_bc_add_span_func add_span,
 }
 
 static int
-cv_sym_bc_tobytes(yasm_bytecode *bc, unsigned char **bufp, void *d,
+cv_sym_bc_tobytes(yasm_bytecode *bc, unsigned char **bufp,
+                  unsigned char *bufstart, void *d,
                   yasm_output_value_func output_value,
                   yasm_output_reloc_func output_reloc)
 {
@@ -1061,7 +1068,7 @@ cv_sym_bc_tobytes(yasm_bytecode *bc, unsigned char **bufp, void *d,
                 break;
             case 'Y':
                 cv_out_sym((yasm_symrec *)cvs->args[arg++].p,
-                           (unsigned long)(buf-(*bufp)), bc, &buf, d,
+                           (unsigned long)(buf-bufstart), bc, &buf, d,
                            output_value);
                 break;
             case 'T':
diff --git a/modules/dbgfmts/codeview/cv-type.c b/modules/dbgfmts/codeview/cv-type.c
index df69e3f..2a52f18 100644
--- a/modules/dbgfmts/codeview/cv-type.c
+++ b/modules/dbgfmts/codeview/cv-type.c
@@ -28,7 +28,6 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include <util.h>
-/*@unused@*/ RCSID("$Id: cv-type.c 2130 2008-10-07 05:38:11Z peter $");
 
 #include <libyasm.h>
 
@@ -483,7 +482,7 @@ static void cv_type_bc_print(const void *contents, FILE *f, int indent_level);
 static int cv_type_bc_calc_len
     (yasm_bytecode *bc, yasm_bc_add_span_func add_span, void *add_span_data);
 static int cv_type_bc_tobytes
-    (yasm_bytecode *bc, unsigned char **bufp, void *d,
+    (yasm_bytecode *bc, unsigned char **bufp, unsigned char *bufstart, void *d,
      yasm_output_value_func output_value,
      /*@null@*/ yasm_output_reloc_func output_reloc);
 
@@ -732,7 +731,8 @@ cv_type_bc_calc_len(yasm_bytecode *bc, yasm_bc_add_span_func add_span,
 }
 
 static int
-cv_type_bc_tobytes(yasm_bytecode *bc, unsigned char **bufp, void *d,
+cv_type_bc_tobytes(yasm_bytecode *bc, unsigned char **bufp,
+                   unsigned char *bufstart, void *d,
                    yasm_output_value_func output_value,
                    yasm_output_reloc_func output_reloc)
 {
diff --git a/modules/dbgfmts/dwarf2/dwarf2-aranges.c b/modules/dbgfmts/dwarf2/dwarf2-aranges.c
index 3b4b578..f398b7f 100644
--- a/modules/dbgfmts/dwarf2/dwarf2-aranges.c
+++ b/modules/dbgfmts/dwarf2/dwarf2-aranges.c
@@ -25,7 +25,6 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include <util.h>
-/*@unused@*/ RCSID("$Id: dwarf2-aranges.c 2010 2007-11-14 08:33:32Z peter $");
 
 #include <libyasm.h>
 
diff --git a/modules/dbgfmts/dwarf2/dwarf2-dbgfmt.c b/modules/dbgfmts/dwarf2/dwarf2-dbgfmt.c
index d16803f..5b66f8a 100644
--- a/modules/dbgfmts/dwarf2/dwarf2-dbgfmt.c
+++ b/modules/dbgfmts/dwarf2/dwarf2-dbgfmt.c
@@ -25,7 +25,6 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include <util.h>
-/*@unused@*/ RCSID("$Id: dwarf2-dbgfmt.c 2130 2008-10-07 05:38:11Z peter $");
 
 #include <libyasm.h>
 
@@ -46,7 +45,7 @@ static void dwarf2_head_bc_print(const void *contents, FILE *f,
 static int dwarf2_head_bc_calc_len
     (yasm_bytecode *bc, yasm_bc_add_span_func add_span, void *add_span_data);
 static int dwarf2_head_bc_tobytes
-    (yasm_bytecode *bc, unsigned char **bufp, void *d,
+    (yasm_bytecode *bc, unsigned char **bufp, unsigned char *bufstart, void *d,
      yasm_output_value_func output_value,
      /*@null@*/ yasm_output_reloc_func output_reloc);
 
@@ -248,7 +247,8 @@ dwarf2_head_bc_calc_len(yasm_bytecode *bc, yasm_bc_add_span_func add_span,
 }
 
 static int
-dwarf2_head_bc_tobytes(yasm_bytecode *bc, unsigned char **bufp, void *d,
+dwarf2_head_bc_tobytes(yasm_bytecode *bc, unsigned char **bufp,
+                       unsigned char *bufstart, void *d,
                        yasm_output_value_func output_value,
                        yasm_output_reloc_func output_reloc)
 {
@@ -288,7 +288,7 @@ dwarf2_head_bc_tobytes(yasm_bytecode *bc, unsigned char **bufp, void *d,
                                 yasm_section_bcs_first(head->debug_ptr)),
             dbgfmt_dwarf2->sizeof_offset*8);
         output_value(&value, buf, dbgfmt_dwarf2->sizeof_offset,
-                     (unsigned long)(buf-*bufp), bc, 0, d);
+                     (unsigned long)(buf-bufstart), bc, 0, d);
         buf += dbgfmt_dwarf2->sizeof_offset;
     }
 
diff --git a/modules/dbgfmts/dwarf2/dwarf2-dbgfmt.h b/modules/dbgfmts/dwarf2/dwarf2-dbgfmt.h
index 7331bf3..0375234 100644
--- a/modules/dbgfmts/dwarf2/dwarf2-dbgfmt.h
+++ b/modules/dbgfmts/dwarf2/dwarf2-dbgfmt.h
@@ -1,4 +1,4 @@
-/* $Id$
+/*
  * DWARF2 debugging format
  *
  *  Copyright (C) 2006-2007  Peter Johnson
@@ -66,6 +66,7 @@ typedef struct dwarf2_loc {
     unsigned long file;     /* index into table of filenames */
     unsigned long line;     /* source line number */
     unsigned long column;   /* source column */
+    unsigned long discriminator;
     int isa_change;
     unsigned long isa;
     enum {
diff --git a/modules/dbgfmts/dwarf2/dwarf2-info.c b/modules/dbgfmts/dwarf2/dwarf2-info.c
index 387c7eb..7dbe43a 100644
--- a/modules/dbgfmts/dwarf2/dwarf2-info.c
+++ b/modules/dbgfmts/dwarf2/dwarf2-info.c
@@ -25,7 +25,6 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include <util.h>
-/*@unused@*/ RCSID("$Id: dwarf2-info.c 2130 2008-10-07 05:38:11Z peter $");
 
 #include <libyasm.h>
 
@@ -197,7 +196,7 @@ static void dwarf2_abbrev_bc_print(const void *contents, FILE *f,
 static int dwarf2_abbrev_bc_calc_len
     (yasm_bytecode *bc, yasm_bc_add_span_func add_span, void *add_span_data);
 static int dwarf2_abbrev_bc_tobytes
-    (yasm_bytecode *bc, unsigned char **bufp, void *d,
+    (yasm_bytecode *bc, unsigned char **bufp, unsigned char *bufstart, void *d,
      yasm_output_value_func output_value,
      /*@null@*/ yasm_output_reloc_func output_reloc);
 
@@ -337,7 +336,10 @@ yasm_dwarf2__generate_info(yasm_object *object, yasm_section *debug_line,
 
     /* producer - assembler name */
     abc->len += dwarf2_add_abbrev_attr(abbrev, DW_AT_producer, DW_FORM_string);
-    dwarf2_append_str(debug_info, PACKAGE " " VERSION);
+    if (getenv("YASM_TEST_SUITE"))
+        dwarf2_append_str(debug_info, "yasm HEAD");
+    else
+        dwarf2_append_str(debug_info, PACKAGE_STRING);
 
     /* language - no standard code for assembler, use MIPS as a substitute */
     abc->len += dwarf2_add_abbrev_attr(abbrev, DW_AT_language, DW_FORM_data2);
@@ -394,7 +396,8 @@ dwarf2_abbrev_bc_calc_len(yasm_bytecode *bc, yasm_bc_add_span_func add_span,
 }
 
 static int
-dwarf2_abbrev_bc_tobytes(yasm_bytecode *bc, unsigned char **bufp, void *d,
+dwarf2_abbrev_bc_tobytes(yasm_bytecode *bc, unsigned char **bufp,
+                         unsigned char *bufstart, void *d,
                          yasm_output_value_func output_value,
                          yasm_output_reloc_func output_reloc)
 {
diff --git a/modules/dbgfmts/dwarf2/dwarf2-line.c b/modules/dbgfmts/dwarf2/dwarf2-line.c
index 489b24c..151dc19 100644
--- a/modules/dbgfmts/dwarf2/dwarf2-line.c
+++ b/modules/dbgfmts/dwarf2/dwarf2-line.c
@@ -28,7 +28,6 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include <util.h>
-/*@unused@*/ RCSID("$Id: dwarf2-line.c 2130 2008-10-07 05:38:11Z peter $");
 
 #include <libyasm.h>
 
@@ -77,7 +76,8 @@ static unsigned char line_opcode_num_operands[DWARF2_LINE_OPCODE_BASE-1] = {
 typedef enum {
     DW_LNE_end_sequence = 1,
     DW_LNE_set_address,
-    DW_LNE_define_file
+    DW_LNE_define_file,
+    DW_LNE_set_discriminator
 } dwarf_line_number_ext_op;
 
 /* Base and range for line offsets in special opcodes */
@@ -120,6 +120,7 @@ typedef struct dwarf2_line_op {
     /* extended opcode */
     dwarf_line_number_ext_op ext_opcode;
     /*@null@*/ /*@dependent@*/ yasm_symrec *ext_operand;  /* unsigned */
+    /*@null@*/ /*@dependent@*/ yasm_intnum *ext_operand_int; /* unsigned */
     unsigned long ext_operandsize;
 } dwarf2_line_op;
 
@@ -130,7 +131,7 @@ static void dwarf2_spp_bc_print(const void *contents, FILE *f,
 static int dwarf2_spp_bc_calc_len
     (yasm_bytecode *bc, yasm_bc_add_span_func add_span, void *add_span_data);
 static int dwarf2_spp_bc_tobytes
-    (yasm_bytecode *bc, unsigned char **bufp, void *d,
+    (yasm_bytecode *bc, unsigned char **bufp, unsigned char *bufstart, void *d,
      yasm_output_value_func output_value,
      /*@null@*/ yasm_output_reloc_func output_reloc);
 
@@ -140,7 +141,7 @@ static void dwarf2_line_op_bc_print(const void *contents, FILE *f,
 static int dwarf2_line_op_bc_calc_len
     (yasm_bytecode *bc, yasm_bc_add_span_func add_span, void *add_span_data);
 static int dwarf2_line_op_bc_tobytes
-    (yasm_bytecode *bc, unsigned char **bufp, void *d,
+    (yasm_bytecode *bc, unsigned char **bufp, unsigned char *bufstart, void *d,
      yasm_output_value_func output_value,
      /*@null@*/ yasm_output_reloc_func output_reloc);
 
@@ -254,6 +255,7 @@ dwarf2_dbgfmt_append_line_op(yasm_section *sect, dwarf_line_number_op opcode,
     line_op->operand = operand;
     line_op->ext_opcode = 0;
     line_op->ext_operand = NULL;
+    line_op->ext_operand_int = NULL;
     line_op->ext_operandsize = 0;
 
     bc = yasm_bc_create_common(&dwarf2_line_op_bc_callback, line_op, 0);
@@ -282,6 +284,31 @@ dwarf2_dbgfmt_append_line_ext_op(yasm_section *sect,
     line_op->operand = yasm_intnum_create_uint(ext_operandsize+1);
     line_op->ext_opcode = ext_opcode;
     line_op->ext_operand = ext_operand;
+    line_op->ext_operand_int = NULL;
+    line_op->ext_operandsize = ext_operandsize;
+
+    bc = yasm_bc_create_common(&dwarf2_line_op_bc_callback, line_op, 0);
+    bc->len = 2 + yasm_intnum_size_leb128(line_op->operand, 0) +
+        ext_operandsize;
+
+    yasm_dwarf2__append_bc(sect, bc);
+    return bc;
+}
+
+static yasm_bytecode *
+dwarf2_dbgfmt_append_line_ext_op_int(yasm_section *sect,
+                                     dwarf_line_number_ext_op ext_opcode,
+                                     /*@only@*/ yasm_intnum *ext_operand)
+{
+    dwarf2_line_op *line_op = yasm_xmalloc(sizeof(dwarf2_line_op));
+    unsigned long ext_operandsize = yasm_intnum_size_leb128(ext_operand, 0);
+    yasm_bytecode *bc;
+
+    line_op->opcode = DW_LNS_extended_op;
+    line_op->operand = yasm_intnum_create_uint(ext_operandsize+1);
+    line_op->ext_opcode = ext_opcode;
+    line_op->ext_operand = NULL;
+    line_op->ext_operand_int = ext_operand;
     line_op->ext_operandsize = ext_operandsize;
 
     bc = yasm_bc_create_common(&dwarf2_line_op_bc_callback, line_op, 0);
@@ -344,6 +371,11 @@ dwarf2_dbgfmt_gen_line_op(yasm_section *debug_line, dwarf2_line_state *state,
         dwarf2_dbgfmt_append_line_op(debug_line, DW_LNS_set_column,
                                      yasm_intnum_create_uint(state->column));
     }
+    if (loc->discriminator != 0) {
+        dwarf2_dbgfmt_append_line_ext_op_int(debug_line,
+            DW_LNE_set_discriminator,
+            yasm_intnum_create_uint(loc->discriminator));
+    }
 #ifdef WITH_DWARF3
     if (loc->isa_change) {
         state->isa = loc->isa;
@@ -453,12 +485,34 @@ typedef struct dwarf2_line_bc_info {
 } dwarf2_line_bc_info;
 
 static int
+dwarf2_filename_equals(const dwarf2_filename *fn,
+                       char **dirs,
+                       const char *pathname,
+                       unsigned long dirlen,
+                       const char *filename)
+{
+    /* check directory */
+    if (fn->dir == 0) {
+        if (dirlen != 0)
+            return 0;
+    } else {
+        if (strncmp(dirs[fn->dir-1], pathname, dirlen) != 0 ||
+            dirs[fn->dir-1][dirlen] != '\0')
+            return 0;
+    }
+
+    /* check filename */
+    return strcmp(fn->filename, filename) == 0;
+}
+
+static int
 dwarf2_generate_line_bc(yasm_bytecode *bc, /*@null@*/ void *d)
 {
     dwarf2_line_bc_info *info = (dwarf2_line_bc_info *)d;
     yasm_dbgfmt_dwarf2 *dbgfmt_dwarf2 = info->dbgfmt_dwarf2;
     unsigned long i;
-    const char *filename;
+    size_t dirlen;
+    const char *pathname, *filename;
     /*@null@*/ yasm_bytecode *nextbc = yasm_bc__next(bc);
 
     if (nextbc && bc->offset == nextbc->offset)
@@ -476,15 +530,20 @@ dwarf2_generate_line_bc(yasm_bytecode *bc, /*@null@*/ void *d)
         }
     }
 
-    yasm_linemap_lookup(info->linemap, bc->line, &filename, &info->loc.line);
+    yasm_linemap_lookup(info->linemap, bc->line, &pathname, &info->loc.line);
+    dirlen = yasm__splitpath(pathname, &filename);
+
     /* Find file index; just linear search it unless it was the last used */
     if (info->lastfile > 0
-        && strcmp(filename, dbgfmt_dwarf2->filenames[info->lastfile-1].pathname)
-           == 0)
+        && dwarf2_filename_equals(&dbgfmt_dwarf2->filenames[info->lastfile-1],
+                                  dbgfmt_dwarf2->dirs, pathname, dirlen,
+                                  filename))
         info->loc.file = info->lastfile;
     else {
         for (i=0; i<dbgfmt_dwarf2->filenames_size; i++) {
-            if (strcmp(filename, dbgfmt_dwarf2->filenames[i].pathname) == 0)
+            if (dwarf2_filename_equals(&dbgfmt_dwarf2->filenames[i],
+                                       dbgfmt_dwarf2->dirs, pathname, dirlen,
+                                       filename))
                 break;
         }
         if (i >= dbgfmt_dwarf2->filenames_size)
@@ -561,6 +620,7 @@ dwarf2_generate_line_section(yasm_section *sect, /*@null@*/ void *d)
         bcinfo.lastfile = 0;
         bcinfo.loc.isa_change = 0;
         bcinfo.loc.column = 0;
+        bcinfo.loc.discriminator = 0;
         bcinfo.loc.is_stmt = IS_STMT_NOCHANGE;
         bcinfo.loc.basic_block = 0;
         bcinfo.loc.prologue_end = 0;
@@ -717,7 +777,8 @@ dwarf2_spp_bc_calc_len(yasm_bytecode *bc, yasm_bc_add_span_func add_span,
 }
 
 static int
-dwarf2_spp_bc_tobytes(yasm_bytecode *bc, unsigned char **bufp, void *d,
+dwarf2_spp_bc_tobytes(yasm_bytecode *bc, unsigned char **bufp,
+                      unsigned char *bufstart, void *d,
                       yasm_output_value_func output_value,
                       yasm_output_reloc_func output_reloc)
 {
@@ -780,6 +841,8 @@ dwarf2_line_op_bc_destroy(void *contents)
     dwarf2_line_op *line_op = (dwarf2_line_op *)contents;
     if (line_op->operand)
         yasm_intnum_destroy(line_op->operand);
+    if (line_op->ext_operand_int)
+        yasm_intnum_destroy(line_op->ext_operand_int);
     yasm_xfree(contents);
 }
 
@@ -799,7 +862,8 @@ dwarf2_line_op_bc_calc_len(yasm_bytecode *bc, yasm_bc_add_span_func add_span,
 }
 
 static int
-dwarf2_line_op_bc_tobytes(yasm_bytecode *bc, unsigned char **bufp, void *d,
+dwarf2_line_op_bc_tobytes(yasm_bytecode *bc, unsigned char **bufp,
+                          unsigned char *bufstart, void *d,
                           yasm_output_value_func output_value,
                           yasm_output_reloc_func output_reloc)
 {
@@ -817,9 +881,12 @@ dwarf2_line_op_bc_tobytes(yasm_bytecode *bc, unsigned char **bufp, void *d,
             yasm_value_init_sym(&value, line_op->ext_operand,
                                 line_op->ext_operandsize*8);
             output_value(&value, buf, line_op->ext_operandsize,
-                         (unsigned long)(buf-*bufp), bc, 0, d);
+                         (unsigned long)(buf-bufstart), bc, 0, d);
             buf += line_op->ext_operandsize;
         }
+        if (line_op->ext_operand_int) {
+            buf += yasm_intnum_get_leb128(line_op->ext_operand_int, buf, 0);
+        }
     }
 
     *bufp = buf;
@@ -831,7 +898,7 @@ yasm_dwarf2__dir_loc(yasm_object *object, yasm_valparamhead *valparams,
                      yasm_valparamhead *objext_valparams, unsigned long line)
 {
     yasm_valparam *vp;
-    int in_is_stmt = 0, in_isa = 0;
+    int in_is_stmt = 0, in_isa = 0, in_discriminator = 0;
 
     /*@dependent@*/ /*@null@*/ const yasm_intnum *intn;
     dwarf2_section_data *dsd;
@@ -892,6 +959,7 @@ yasm_dwarf2__dir_loc(yasm_object *object, yasm_valparamhead *valparams,
 
     /* Defaults for optional settings */
     loc->column = 0;
+    loc->discriminator = 0;
     loc->isa_change = 0;
     loc->isa = 0;
     loc->is_stmt = IS_STMT_NOCHANGE;
@@ -966,11 +1034,33 @@ restart:
             loc->isa_change = 1;
             loc->isa = yasm_intnum_get_uint(intn);
             yasm_expr_destroy(e);
+        } else if (in_discriminator) {
+            in_discriminator = 0;
+            if (!(e = yasm_vp_expr(vp, object->symtab, line)) ||
+                !(intn = yasm_expr_get_intnum(&e, 0))) {
+                yasm_error_set(YASM_ERROR_NOT_CONSTANT,
+                               N_("discriminator value is not a constant"));
+                yasm_xfree(loc);
+                if (e)
+                    yasm_expr_destroy(e);
+                return;
+            }
+            if (yasm_intnum_sign(intn) < 0) {
+                yasm_error_set(YASM_ERROR_VALUE,
+                               N_("discriminator value less than zero"));
+                yasm_xfree(loc);
+                yasm_expr_destroy(e);
+                return;
+            }
+            loc->discriminator = yasm_intnum_get_uint(intn);
+            yasm_expr_destroy(e);
         } else if (!vp->val && (s = yasm_vp_id(vp))) {
             if (yasm__strcasecmp(s, "is_stmt") == 0)
                 in_is_stmt = 1;
             else if (yasm__strcasecmp(s, "isa") == 0)
                 in_isa = 1;
+            else if (yasm__strcasecmp(s, "discriminator") == 0)
+                in_discriminator = 1;
             else if (yasm__strcasecmp(s, "basic_block") == 0)
                 loc->basic_block = 1;
             else if (yasm__strcasecmp(s, "prologue_end") == 0)
@@ -989,15 +1079,19 @@ restart:
         } else if (yasm__strcasecmp(vp->val, "isa") == 0) {
             in_isa = 1;
             goto restart; /* don't go to the next valparam */
+        } else if (yasm__strcasecmp(vp->val, "discriminator") == 0) {
+            in_discriminator = 1;
+            goto restart; /* don't go to the next valparam */
         } else
             yasm_warn_set(YASM_WARN_GENERAL,
                           N_("unrecognized loc option `%s'"), vp->val);
         vp = yasm_vps_next(vp);
     }
 
-    if (in_is_stmt || in_isa) {
+    if (in_is_stmt || in_isa || in_discriminator) {
         yasm_error_set(YASM_ERROR_SYNTAX, N_("%s requires value"),
-                       in_is_stmt ? "is_stmt" : "isa");
+                       in_is_stmt ? "is_stmt" :
+                       (in_isa ? "isa" : "discriminator"));
         yasm_xfree(loc);
         return;
     }
diff --git a/modules/dbgfmts/null/null-dbgfmt.c b/modules/dbgfmts/null/null-dbgfmt.c
index 6ff5d0d..d2d1bed 100644
--- a/modules/dbgfmts/null/null-dbgfmt.c
+++ b/modules/dbgfmts/null/null-dbgfmt.c
@@ -25,7 +25,6 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include <util.h>
-/*@unused@*/ RCSID("$Id: null-dbgfmt.c 1893 2007-07-14 03:11:32Z peter $");
 
 #include <libyasm.h>
 
diff --git a/modules/dbgfmts/stabs/stabs-dbgfmt.c b/modules/dbgfmts/stabs/stabs-dbgfmt.c
index 1648ac6..c8cf9b3 100644
--- a/modules/dbgfmts/stabs/stabs-dbgfmt.c
+++ b/modules/dbgfmts/stabs/stabs-dbgfmt.c
@@ -25,7 +25,6 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include <util.h>
-/*@unused@*/ RCSID("$Id: stabs-dbgfmt.c 2130 2008-10-07 05:38:11Z peter $");
 
 #include <libyasm.h>
 
@@ -119,7 +118,7 @@ static void stabs_bc_str_print(const void *contents, FILE *f, int
 static int stabs_bc_str_calc_len
     (yasm_bytecode *bc, yasm_bc_add_span_func add_span, void *add_span_data);
 static int stabs_bc_str_tobytes
-    (yasm_bytecode *bc, unsigned char **bufp, void *d,
+    (yasm_bytecode *bc, unsigned char **bufp, unsigned char *bufstart, void *d,
      yasm_output_value_func output_value,
      /*@null@*/ yasm_output_reloc_func output_reloc);
 
@@ -129,7 +128,7 @@ static void stabs_bc_stab_print(const void *contents, FILE *f, int
 static int stabs_bc_stab_calc_len
     (yasm_bytecode *bc, yasm_bc_add_span_func add_span, void *add_span_data);
 static int stabs_bc_stab_tobytes
-    (yasm_bytecode *bc, unsigned char **bufp, void *d,
+    (yasm_bytecode *bc, unsigned char **bufp, unsigned char *bufstart, void *d,
      yasm_output_value_func output_value,
      /*@null@*/ yasm_output_reloc_func output_reloc);
 
@@ -405,7 +404,8 @@ stabs_dbgfmt_generate(yasm_object *object, yasm_linemap *linemap,
 }
 
 static int
-stabs_bc_stab_tobytes(yasm_bytecode *bc, unsigned char **bufp, void *d,
+stabs_bc_stab_tobytes(yasm_bytecode *bc, unsigned char **bufp,
+                      unsigned char *bufstart, void *d,
                       yasm_output_value_func output_value,
                       yasm_output_reloc_func output_reloc)
 {
@@ -439,7 +439,8 @@ stabs_bc_stab_tobytes(yasm_bytecode *bc, unsigned char **bufp, void *d,
 }
 
 static int
-stabs_bc_str_tobytes(yasm_bytecode *bc, unsigned char **bufp, void *d,
+stabs_bc_str_tobytes(yasm_bytecode *bc, unsigned char **bufp,
+                     unsigned char *bufstart, void *d,
                      yasm_output_value_func output_value,
                      yasm_output_reloc_func output_reloc)
 {
diff --git a/modules/dbgfmts/yasm_dbgfmts.xml b/modules/dbgfmts/yasm_dbgfmts.xml
index a80d86b..7cd38a4 100644
--- a/modules/dbgfmts/yasm_dbgfmts.xml
+++ b/modules/dbgfmts/yasm_dbgfmts.xml
@@ -2,8 +2,6 @@
 <!DOCTYPE refentry PUBLIC "-//OASIS//DTD DocBook XML V4.1.2//EN"
           "http://www.oasis-open.org/docbook/xml/4.1.2/docbookx.dtd">
 
-<!-- $Id: yasm_dbgfmts.xml 1662 2006-10-21 18:52:29Z peter $ -->     
-
 <refentry id="yasm_dbgfmts">
 
  <refentryinfo>
diff --git a/modules/listfmts/nasm/nasm-listfmt.c b/modules/listfmts/nasm/nasm-listfmt.c
index 168dbc2..1dfc5b6 100644
--- a/modules/listfmts/nasm/nasm-listfmt.c
+++ b/modules/listfmts/nasm/nasm-listfmt.c
@@ -25,7 +25,6 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include <util.h>
-/*@unused@*/ RCSID("$Id: nasm-listfmt.c 1894 2007-07-14 04:34:41Z peter $");
 
 #include <libyasm.h>
 
diff --git a/modules/objfmts/bin/bin-objfmt.c b/modules/objfmts/bin/bin-objfmt.c
index 8527e38..5f42224 100644
--- a/modules/objfmts/bin/bin-objfmt.c
+++ b/modules/objfmts/bin/bin-objfmt.c
@@ -25,7 +25,6 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include <util.h>
-/*@unused@*/ RCSID("$Id: bin-objfmt.c 2310 2010-03-28 19:28:54Z peter $");
 
 #ifdef HAVE_UNISTD_H
 #include <unistd.h>
diff --git a/modules/objfmts/coff/coff-objfmt.c b/modules/objfmts/coff/coff-objfmt.c
index b3d8848..c9646c6 100644
--- a/modules/objfmts/coff/coff-objfmt.c
+++ b/modules/objfmts/coff/coff-objfmt.c
@@ -26,7 +26,6 @@
  */
 #include <util.h>
 #include <time.h>
-/*@unused@*/ RCSID("$Id: coff-objfmt.c 2347 2010-08-01 17:31:12Z peter $");
 
 #include <libyasm.h>
 
@@ -183,10 +182,15 @@ typedef struct yasm_objfmt_coff {
 
     coff_symrec_data *filesym_data;         /* Data for .file symbol */
 
+    /* data for .def/.endef and related directives */
+    coff_symrec_data *def_sym;              /* symbol specified by .def */
+
     /* data for win64 proc_frame and related directives */
     unsigned long proc_frame;   /* Line number of start of proc, or 0 */
     unsigned long done_prolog;  /* Line number of end of prologue, or 0 */
     /*@null@*/ coff_unwind_info *unwind;        /* Unwind info */
+
+    yasm_symrec *ssym_imagebase;            /* ..imagebase symbol for win64 */
 } yasm_objfmt_coff;
 
 typedef struct coff_objfmt_output_info {
@@ -227,7 +231,7 @@ static void win32_sxdata_bc_print(const void *contents, FILE *f,
 static int win32_sxdata_bc_calc_len
     (yasm_bytecode *bc, yasm_bc_add_span_func add_span, void *add_span_data);
 static int win32_sxdata_bc_tobytes
-    (yasm_bytecode *bc, unsigned char **bufp, void *d,
+    (yasm_bytecode *bc, unsigned char **bufp, unsigned char *bufstart, void *d,
      yasm_output_value_func output_value,
      /*@null@*/ yasm_output_reloc_func output_reloc);
 
@@ -294,6 +298,7 @@ coff_common_create(yasm_object *object)
     objfmt_coff->proc_frame = 0;
     objfmt_coff->done_prolog = 0;
     objfmt_coff->unwind = NULL;
+    objfmt_coff->ssym_imagebase = NULL;
 
     return objfmt_coff;
 }
@@ -380,6 +385,8 @@ win64_objfmt_create(yasm_object *object)
         objfmt_coff->objfmt.module = &yasm_win64_LTX_objfmt;
         objfmt_coff->win32 = 1;
         objfmt_coff->win64 = 1;
+        objfmt_coff->ssym_imagebase =
+            yasm_symtab_define_label(object->symtab, "..imagebase", NULL, 0, 0);
     }
     return (yasm_objfmt *)objfmt_coff;
 }
@@ -487,14 +494,18 @@ coff_objfmt_output_value(yasm_value *value, unsigned char *buf,
         /*@dependent@*/ /*@null@*/ yasm_symrec *sym = value->rel;
         unsigned long addr;
         coff_reloc *reloc;
+        int nobase = info->csd->flags2 & COFF_FLAG_NOBASE;
 
         /* Sometimes we want the relocation to be generated against one
          * symbol but the value generated correspond to a different symbol.
          * This is done through (sym being referenced) WRT (sym used for
          * reloc).  Note both syms need to be in the same section!
          */
-        if (value->wrt) {
+        if (value->wrt && value->wrt == objfmt_coff->ssym_imagebase)
+            nobase = 1;
+        else if (value->wrt) {
             /*@dependent@*/ /*@null@*/ yasm_bytecode *rel_precbc, *wrt_precbc;
+
             if (!yasm_symrec_get_label(sym, &rel_precbc)
                 || !yasm_symrec_get_label(value->wrt, &wrt_precbc)) {
                 yasm_error_set(YASM_ERROR_TOO_COMPLEX,
@@ -569,8 +580,8 @@ coff_objfmt_output_value(yasm_value *value, unsigned char *buf,
                 intn_minus = bc->offset;
         }
 
-        if (value->seg_of || value->section_rel) {
-            /* Segment or section-relative generation; zero value. */
+        if (value->seg_of) {
+            /* Segment generation; zero value. */
             intn_val = 0;
             intn_minus = 0;
         }
@@ -642,13 +653,13 @@ coff_objfmt_output_value(yasm_value *value, unsigned char *buf,
                 yasm_internal_error(N_("coff objfmt: unrecognized machine"));
         } else {
             if (objfmt_coff->machine == COFF_MACHINE_I386) {
-                if (info->csd->flags2 & COFF_FLAG_NOBASE)
+                if (nobase)
                     reloc->type = COFF_RELOC_I386_ADDR32NB;
                 else
                     reloc->type = COFF_RELOC_I386_ADDR32;
             } else if (objfmt_coff->machine == COFF_MACHINE_AMD64) {
                 if (valsize == 32) {
-                    if (info->csd->flags2 & COFF_FLAG_NOBASE)
+                    if (nobase)
                         reloc->type = COFF_RELOC_AMD64_ADDR32NB;
                     else
                         reloc->type = COFF_RELOC_AMD64_ADDR32;
@@ -1512,6 +1523,7 @@ coff_objfmt_section_switch(yasm_object *object, yasm_valparamhead *valparams,
     } else if (objfmt_coff->win64 && strcmp(sectname, ".xdata") == 0) {
         data.flags = COFF_STYP_DATA | COFF_STYP_READ;
         align = 8;
+        data.flags2 = COFF_FLAG_NOBASE;
     } else if (objfmt_coff->win32 && strcmp(sectname, ".sxdata") == 0) {
         data.flags = COFF_STYP_INFO;
     } else if (strcmp(sectname, ".comment") == 0) {
@@ -1594,6 +1606,17 @@ coff_objfmt_get_special_sym(yasm_object *object, const char *name,
     return NULL;
 }
 
+static /*@observer@*/ /*@null@*/ yasm_symrec *
+win64_objfmt_get_special_sym(yasm_object *object, const char *name,
+                             const char *parser)
+{
+    if (yasm__strcasecmp(name, "imagebase") == 0) {
+        yasm_objfmt_coff *objfmt_coff = (yasm_objfmt_coff *)object->objfmt;
+        return objfmt_coff->ssym_imagebase;
+    }
+    return NULL;
+}
+
 static void
 coff_section_data_destroy(void *data)
 {
@@ -1758,7 +1781,8 @@ win32_sxdata_bc_calc_len(yasm_bytecode *bc, yasm_bc_add_span_func add_span,
 }
 
 static int
-win32_sxdata_bc_tobytes(yasm_bytecode *bc, unsigned char **bufp, void *d,
+win32_sxdata_bc_tobytes(yasm_bytecode *bc, unsigned char **bufp,
+                        unsigned char *bufstart, void *d,
                         yasm_output_value_func output_value,
                         yasm_output_reloc_func output_reloc)
 {
@@ -1840,6 +1864,131 @@ dir_ident(yasm_object *object, yasm_valparamhead *valparams,
 }
 
 static void
+dir_secrel32(yasm_object *object, yasm_valparamhead *valparams,
+             yasm_valparamhead *objext_valparams, unsigned long line)
+{
+    yasm_datavalhead dvs;
+    yasm_valparam *vp;
+
+    if (!object->cur_section) {
+        yasm_error_set(YASM_ERROR_SYNTAX,
+                       N_(".secrel32 can only be used inside of a section"));
+        return;
+    }
+
+    vp = yasm_vps_first(valparams);
+    yasm_dvs_initialize(&dvs);
+    do {
+        yasm_expr *e = yasm_vp_expr(vp, object->symtab, line);
+        yasm_dataval *dv;
+        if (!e) {
+            yasm_error_set(YASM_ERROR_VALUE,
+                           N_(".secrel32 requires expressions"));
+            yasm_dvs_delete(&dvs);
+            return;
+        }
+        dv = yasm_dv_create_expr(e);
+        yasm_dv_get_value(dv)->section_rel = 1;
+        yasm_dvs_append(&dvs, dv);
+    } while ((vp = yasm_vps_next(vp)));
+
+    yasm_section_bcs_append(object->cur_section,
+        yasm_bc_create_data(&dvs, 4, 0, object->arch, line));
+}
+
+static void
+dir_def(yasm_object *object, yasm_valparamhead *valparams,
+        yasm_valparamhead *objext_valparams, unsigned long line)
+{
+    yasm_objfmt_coff *objfmt_coff = (yasm_objfmt_coff *)object->objfmt;
+    yasm_valparam *vp;
+    const char *symname;
+    yasm_symrec *sym;
+    coff_symrec_data *sym_data;
+
+    if (objfmt_coff->def_sym) {
+        yasm_warn_set(YASM_WARN_GENERAL,
+                      N_(".def pseudo-op used inside of .def/.endef; ignored"));
+        return;
+    }
+
+    vp = yasm_vps_first(valparams);
+    symname = yasm_vp_id(vp);
+    if (!symname) {
+        yasm_error_set(YASM_ERROR_SYNTAX,
+                       N_("argument to SAFESEH must be symbol name"));
+        return;
+    }
+
+    sym = yasm_symtab_use(object->symtab, symname, line);
+    sym_data = yasm_symrec_get_data(sym, &coff_symrec_data_cb);
+    if (!sym_data) {
+        sym_data = coff_objfmt_sym_set_data(sym, COFF_SCL_NULL, 0,
+                                            COFF_SYMTAB_AUX_NONE);
+    }
+    objfmt_coff->def_sym = sym_data;
+}
+
+static void
+dir_scl(yasm_object *object, yasm_valparamhead *valparams,
+        yasm_valparamhead *objext_valparams, unsigned long line)
+{
+    yasm_objfmt_coff *objfmt_coff = (yasm_objfmt_coff *)object->objfmt;
+    yasm_intnum *intn = NULL;
+
+    if (!objfmt_coff->def_sym) {
+        yasm_warn_set(YASM_WARN_GENERAL,
+                      N_("%s pseudo-op used outside of .def/.endef; ignored"),
+                      ".scl");
+        return;
+    }
+
+    if (yasm_dir_helper_intn(object, yasm_vps_first(valparams), line,
+                             &intn, 0) < 0)
+        return;
+    if (!intn)
+        return;
+    objfmt_coff->def_sym->sclass = yasm_intnum_get_uint(intn);
+    yasm_intnum_destroy(intn);
+}
+
+static void
+dir_type(yasm_object *object, yasm_valparamhead *valparams,
+         yasm_valparamhead *objext_valparams, unsigned long line)
+{
+    yasm_objfmt_coff *objfmt_coff = (yasm_objfmt_coff *)object->objfmt;
+    yasm_intnum *intn = NULL;
+
+    if (!objfmt_coff->def_sym) {
+        yasm_warn_set(YASM_WARN_GENERAL,
+                      N_("%s pseudo-op used outside of .def/.endef; ignored"),
+                      ".type");
+        return;
+    }
+
+    if (yasm_dir_helper_intn(object, yasm_vps_first(valparams), line,
+                             &intn, 0) < 0)
+        return;
+    if (!intn)
+        return;
+    objfmt_coff->def_sym->type = yasm_intnum_get_uint(intn);
+    yasm_intnum_destroy(intn);
+}
+
+static void
+dir_endef(yasm_object *object, yasm_valparamhead *valparams,
+          yasm_valparamhead *objext_valparams, unsigned long line)
+{
+    yasm_objfmt_coff *objfmt_coff = (yasm_objfmt_coff *)object->objfmt;
+    if (!objfmt_coff->def_sym) {
+        yasm_warn_set(YASM_WARN_GENERAL,
+                      N_(".endef pseudo-op used before .def; ignored"));
+        return;
+    }
+    objfmt_coff->def_sym = NULL;
+}
+
+static void
 dir_proc_frame(yasm_object *object, /*@null@*/ yasm_valparamhead *valparams,
                yasm_valparamhead *objext_valparams, unsigned long line)
 {
@@ -2194,6 +2343,11 @@ static const char *coff_objfmt_dbgfmt_keywords[] = {
 static const yasm_directive coff_objfmt_directives[] = {
     { ".ident",         "gas",  dir_ident,      YASM_DIR_ANY },
     { "ident",          "nasm", dir_ident,      YASM_DIR_ANY },
+    { ".def",           "gas",  dir_def,        YASM_DIR_ID_REQUIRED },
+    { ".endef",         "gas",  dir_endef,      YASM_DIR_ANY },
+    { ".scl",           "gas",  dir_scl,        YASM_DIR_ARG_REQUIRED },
+    { ".type",          "gas",  dir_type,       YASM_DIR_ARG_REQUIRED },
+    { ".secrel32",      "gas",  dir_secrel32,   YASM_DIR_ARG_REQUIRED },
     { NULL, NULL, NULL, 0 }
 };
 
@@ -2228,6 +2382,11 @@ static const char *winXX_objfmt_dbgfmt_keywords[] = {
 static const yasm_directive win32_objfmt_directives[] = {
     { ".ident",         "gas",  dir_ident,      YASM_DIR_ANY },
     { "ident",          "nasm", dir_ident,      YASM_DIR_ANY },
+    { ".def",           "gas",  dir_def,        YASM_DIR_ID_REQUIRED },
+    { ".endef",         "gas",  dir_endef,      YASM_DIR_ANY },
+    { ".scl",           "gas",  dir_scl,        YASM_DIR_ARG_REQUIRED },
+    { ".type",          "gas",  dir_type,       YASM_DIR_ARG_REQUIRED },
+    { ".secrel32",      "gas",  dir_secrel32,   YASM_DIR_ARG_REQUIRED },
     { ".export",        "gas",  dir_export,     YASM_DIR_ID_REQUIRED },
     { "export",         "nasm", dir_export,     YASM_DIR_ID_REQUIRED },
     { ".safeseh",       "gas",  dir_safeseh,    YASM_DIR_ID_REQUIRED },
@@ -2273,6 +2432,11 @@ yasm_objfmt_module yasm_win32_LTX_objfmt = {
 static const yasm_directive win64_objfmt_directives[] = {
     { ".ident",         "gas",  dir_ident,      YASM_DIR_ANY },
     { "ident",          "nasm", dir_ident,      YASM_DIR_ANY },
+    { ".def",           "gas",  dir_def,        YASM_DIR_ID_REQUIRED },
+    { ".endef",         "gas",  dir_endef,      YASM_DIR_ANY },
+    { ".scl",           "gas",  dir_scl,        YASM_DIR_ARG_REQUIRED },
+    { ".type",          "gas",  dir_type,       YASM_DIR_ARG_REQUIRED },
+    { ".secrel32",      "gas",  dir_secrel32,   YASM_DIR_ARG_REQUIRED },
     { ".export",        "gas",  dir_export,     YASM_DIR_ID_REQUIRED },
     { "export",         "nasm", dir_export,     YASM_DIR_ID_REQUIRED },
     { ".proc_frame",    "gas",  dir_proc_frame, YASM_DIR_ID_REQUIRED },
@@ -2322,7 +2486,7 @@ yasm_objfmt_module yasm_win64_LTX_objfmt = {
     coff_objfmt_add_default_section,
     coff_objfmt_init_new_section,
     coff_objfmt_section_switch,
-    coff_objfmt_get_special_sym
+    win64_objfmt_get_special_sym
 };
 yasm_objfmt_module yasm_x64_LTX_objfmt = {
     "Win64",
@@ -2340,5 +2504,5 @@ yasm_objfmt_module yasm_x64_LTX_objfmt = {
     coff_objfmt_add_default_section,
     coff_objfmt_init_new_section,
     coff_objfmt_section_switch,
-    coff_objfmt_get_special_sym
+    win64_objfmt_get_special_sym
 };
diff --git a/modules/objfmts/coff/coff-objfmt.h b/modules/objfmts/coff/coff-objfmt.h
index cda09a7..10d88a0 100644
--- a/modules/objfmts/coff/coff-objfmt.h
+++ b/modules/objfmts/coff/coff-objfmt.h
@@ -1,4 +1,4 @@
-/* $Id: coff-objfmt.h 1825 2007-04-22 03:32:46Z peter $
+/*
  * COFF (DJGPP) object format
  *
  *  Copyright (C) 2007  Peter Johnson
diff --git a/modules/objfmts/coff/win64-except.c b/modules/objfmts/coff/win64-except.c
index b5d3f48..8c8ecbb 100644
--- a/modules/objfmts/coff/win64-except.c
+++ b/modules/objfmts/coff/win64-except.c
@@ -25,7 +25,6 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include <util.h>
-/*@unused@*/ RCSID("$Id: win64-except.c 2130 2008-10-07 05:38:11Z peter $");
 
 #include <libyasm.h>
 
@@ -48,7 +47,7 @@ static int win64_uwinfo_bc_expand(yasm_bytecode *bc, int span, long old_val,
                                   long new_val, /*@out@*/ long *neg_thres,
                                   /*@out@*/ long *pos_thres);
 static int win64_uwinfo_bc_tobytes
-    (yasm_bytecode *bc, unsigned char **bufp, void *d,
+    (yasm_bytecode *bc, unsigned char **bufp, unsigned char *bufstart, void *d,
      yasm_output_value_func output_value,
      /*@null@*/ yasm_output_reloc_func output_reloc);
 
@@ -63,7 +62,7 @@ static int win64_uwcode_bc_expand(yasm_bytecode *bc, int span, long old_val,
                                   long new_val, /*@out@*/ long *neg_thres,
                                   /*@out@*/ long *pos_thres);
 static int win64_uwcode_bc_tobytes
-    (yasm_bytecode *bc, unsigned char **bufp, void *d,
+    (yasm_bytecode *bc, unsigned char **bufp, unsigned char *bufstart, void *d,
      yasm_output_value_func output_value,
      /*@null@*/ yasm_output_reloc_func output_reloc);
 
@@ -279,7 +278,8 @@ win64_uwinfo_bc_expand(yasm_bytecode *bc, int span, long old_val, long new_val,
 }
 
 static int
-win64_uwinfo_bc_tobytes(yasm_bytecode *bc, unsigned char **bufp, void *d,
+win64_uwinfo_bc_tobytes(yasm_bytecode *bc, unsigned char **bufp,
+                        unsigned char *bufstart, void *d,
                         yasm_output_value_func output_value,
                         yasm_output_reloc_func output_reloc)
 {
@@ -295,12 +295,12 @@ win64_uwinfo_bc_tobytes(yasm_bytecode *bc, unsigned char **bufp, void *d,
         YASM_WRITE_8(buf, 1);
 
     /* Size of prolog */
-    output_value(&info->prolog_size, buf, 1, (unsigned long)(buf-*bufp),
+    output_value(&info->prolog_size, buf, 1, (unsigned long)(buf-bufstart),
                  bc, 1, d);
     buf += 1;
 
     /* Count of codes */
-    output_value(&info->codes_count, buf, 1, (unsigned long)(buf-*bufp),
+    output_value(&info->codes_count, buf, 1, (unsigned long)(buf-bufstart),
                  bc, 1, d);
     buf += 1;
 
@@ -459,7 +459,8 @@ win64_uwcode_bc_expand(yasm_bytecode *bc, int span, long old_val, long new_val,
 }
 
 static int
-win64_uwcode_bc_tobytes(yasm_bytecode *bc, unsigned char **bufp, void *d,
+win64_uwcode_bc_tobytes(yasm_bytecode *bc, unsigned char **bufp,
+                        unsigned char *bufstart, void *d,
                         yasm_output_value_func output_value,
                         yasm_output_reloc_func output_reloc)
 {
@@ -476,7 +477,7 @@ win64_uwcode_bc_tobytes(yasm_bytecode *bc, unsigned char **bufp, void *d,
         yasm_expr_create(YASM_EXPR_SUB, yasm_expr_sym(code->loc),
                          yasm_expr_sym(code->proc), bc->line),
         8);
-    output_value(&val, buf, 1, (unsigned long)(buf-*bufp), bc, 1, d);
+    output_value(&val, buf, 1, (unsigned long)(buf-bufstart), bc, 1, d);
     buf += 1;
     yasm_value_delete(&val);
 
diff --git a/modules/objfmts/dbg/dbg-objfmt.c b/modules/objfmts/dbg/dbg-objfmt.c
index 98138de..bdf403c 100644
--- a/modules/objfmts/dbg/dbg-objfmt.c
+++ b/modules/objfmts/dbg/dbg-objfmt.c
@@ -25,7 +25,6 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include <util.h>
-/*@unused@*/ RCSID("$Id: dbg-objfmt.c 2310 2010-03-28 19:28:54Z peter $");
 
 #include <libyasm.h>
 
diff --git a/modules/objfmts/elf/elf-machine.h b/modules/objfmts/elf/elf-machine.h
index 0d8933b..ea6cb4e 100644
--- a/modules/objfmts/elf/elf-machine.h
+++ b/modules/objfmts/elf/elf-machine.h
@@ -1,4 +1,4 @@
-/* $Id:$
+/*
  * ELF object machine specific format helpers
  *
  *  Copyright (C) 2004-2007  Michael Urman
@@ -99,7 +99,7 @@ struct elf_machine_handler {
     func_write_reloc write_reloc;
     func_write_proghead write_proghead;
 
-    const elf_machine_ssym *ssyms;      /* array of "special" syms */
+    elf_machine_ssym *ssyms;            /* array of "special" syms */
     const size_t num_ssyms;             /* size of array */
 
     const int bits;                     /* usually 32 or 64 */
diff --git a/modules/objfmts/elf/elf-objfmt.c b/modules/objfmts/elf/elf-objfmt.c
index f01908f..1cf725f 100644
--- a/modules/objfmts/elf/elf-objfmt.c
+++ b/modules/objfmts/elf/elf-objfmt.c
@@ -25,7 +25,6 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include <util.h>
-/*@unused@*/ RCSID("$Id: elf-objfmt.c 2310 2010-03-28 19:28:54Z peter $");
 
 /* Notes
  *
diff --git a/modules/objfmts/elf/elf-x86-amd64.c b/modules/objfmts/elf/elf-x86-amd64.c
index 3882fa5..3ba376a 100644
--- a/modules/objfmts/elf/elf-x86-amd64.c
+++ b/modules/objfmts/elf/elf-x86-amd64.c
@@ -26,7 +26,6 @@
  */
 
 #include <util.h>
-/*@unused@*/ RCSID("$Id: elf-x86-amd64.c 2210 2009-07-22 05:51:35Z peter $");
 
 #include <libyasm.h>
 #define YASM_OBJFMT_ELF_INTERNAL
diff --git a/modules/objfmts/elf/elf-x86-x86.c b/modules/objfmts/elf/elf-x86-x86.c
index afbf73e..d79ec6e 100644
--- a/modules/objfmts/elf/elf-x86-x86.c
+++ b/modules/objfmts/elf/elf-x86-x86.c
@@ -26,14 +26,13 @@
  */
 
 #include <util.h>
-/*@unused@*/ RCSID("$Id: elf-x86-x86.c 2321 2010-05-15 07:45:48Z peter $");
 
 #include <libyasm.h>
 #define YASM_OBJFMT_ELF_INTERNAL
 #include "elf.h"
 #include "elf-machine.h"
 
-static const elf_machine_ssym elf_x86_x86_ssyms[] = {
+static elf_machine_ssym elf_x86_x86_ssyms[] = {
     {"plt",         ELF_SSYM_SYM_RELATIVE,  R_386_PLT32,        32},
     {"gotoff",      0,                      R_386_GOTOFF,       32},
     /* special one for NASM */
diff --git a/modules/objfmts/elf/elf.c b/modules/objfmts/elf/elf.c
index e0b28a1..7adf7ea 100644
--- a/modules/objfmts/elf/elf.c
+++ b/modules/objfmts/elf/elf.c
@@ -26,7 +26,6 @@
  */
 
 #include <util.h>
-/*@unused@*/ RCSID("$Id: elf.c 2206 2009-07-21 06:48:42Z peter $");
 
 #include <libyasm.h>
 #define YASM_OBJFMT_ELF_INTERNAL
diff --git a/modules/objfmts/elf/elf.h b/modules/objfmts/elf/elf.h
index 9c04c1f..fce629a 100644
--- a/modules/objfmts/elf/elf.h
+++ b/modules/objfmts/elf/elf.h
@@ -1,4 +1,4 @@
-/* $Id: elf.h 2208 2009-07-22 05:45:03Z peter $
+/*
  * ELF object format helpers
  *
  *  Copyright (C) 2003-2007  Michael Urman
diff --git a/modules/objfmts/macho/macho-objfmt.c b/modules/objfmts/macho/macho-objfmt.c
index 96b17c4..1b00918 100644
--- a/modules/objfmts/macho/macho-objfmt.c
+++ b/modules/objfmts/macho/macho-objfmt.c
@@ -91,7 +91,6 @@
 */
 
 #include <util.h>
-/*@unused@*/ RCSID("$Id: macho-objfmt.c 2345 2010-08-01 01:27:40Z peter $");
 
 #include <libyasm.h>
 
diff --git a/modules/objfmts/rdf/rdf-objfmt.c b/modules/objfmts/rdf/rdf-objfmt.c
index e9d44a7..d081fc5 100644
--- a/modules/objfmts/rdf/rdf-objfmt.c
+++ b/modules/objfmts/rdf/rdf-objfmt.c
@@ -25,7 +25,6 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include <util.h>
-/*@unused@*/ RCSID("$Id: rdf-objfmt.c 2310 2010-03-28 19:28:54Z peter $");
 
 #include <libyasm.h>
 
diff --git a/modules/objfmts/xdf/xdf-objfmt.c b/modules/objfmts/xdf/xdf-objfmt.c
index 7d4ca76..aac6e77 100644
--- a/modules/objfmts/xdf/xdf-objfmt.c
+++ b/modules/objfmts/xdf/xdf-objfmt.c
@@ -25,7 +25,6 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include <util.h>
-/*@unused@*/ RCSID("$Id: xdf-objfmt.c 2310 2010-03-28 19:28:54Z peter $");
 
 #include <libyasm.h>
 
diff --git a/modules/objfmts/yasm_objfmts.xml b/modules/objfmts/yasm_objfmts.xml
index 0224645..13811a0 100644
--- a/modules/objfmts/yasm_objfmts.xml
+++ b/modules/objfmts/yasm_objfmts.xml
@@ -2,8 +2,6 @@
 <!DOCTYPE refentry PUBLIC "-//OASIS//DTD DocBook XML V4.1.2//EN"
           "http://www.oasis-open.org/docbook/xml/4.1.2/docbookx.dtd">
 
-<!-- $Id: yasm_objfmts.xml 1796 2007-02-24 23:33:27Z peter $ -->     
-
 <refentry id="yasm_objfmts">
 
  <refentryinfo>
diff --git a/modules/parsers/gas/gas-parse-intel.c b/modules/parsers/gas/gas-parse-intel.c
index 673472a..9d412fc 100644
--- a/modules/parsers/gas/gas-parse-intel.c
+++ b/modules/parsers/gas/gas-parse-intel.c
@@ -28,7 +28,6 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include <util.h>
-RCSID("$Id: gas-parse-intel.c 2279 2010-01-19 07:57:43Z peter $");
 
 #include <libyasm.h>
 
diff --git a/modules/parsers/gas/gas-parse.c b/modules/parsers/gas/gas-parse.c
index 13189f4..56fb854 100644
--- a/modules/parsers/gas/gas-parse.c
+++ b/modules/parsers/gas/gas-parse.c
@@ -28,7 +28,6 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include <util.h>
-RCSID("$Id: gas-parse.c 2279 2010-01-19 07:57:43Z peter $");
 
 #include <libyasm.h>
 
diff --git a/modules/parsers/gas/gas-parser.c b/modules/parsers/gas/gas-parser.c
index e901683..088bcda 100644
--- a/modules/parsers/gas/gas-parser.c
+++ b/modules/parsers/gas/gas-parser.c
@@ -28,7 +28,6 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include <util.h>
-/*@unused@*/ RCSID("$Id: gas-parser.c 2279 2010-01-19 07:57:43Z peter $");
 
 #include <libyasm.h>
 
diff --git a/modules/parsers/gas/gas-parser.h b/modules/parsers/gas/gas-parser.h
index ba734e1..99659e9 100644
--- a/modules/parsers/gas/gas-parser.h
+++ b/modules/parsers/gas/gas-parser.h
@@ -1,4 +1,4 @@
-/* $Id: gas-parser.h 2279 2010-01-19 07:57:43Z peter $
+/*
  * GAS-compatible parser header file
  *
  *  Copyright (C) 2005-2007  Peter Johnson
diff --git a/modules/parsers/gas/gas-token.re b/modules/parsers/gas/gas-token.re
index f4924ef..1a8673d 100644
--- a/modules/parsers/gas/gas-token.re
+++ b/modules/parsers/gas/gas-token.re
@@ -28,7 +28,6 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include <util.h>
-RCSID("$Id: gas-token.re 2266 2010-01-03 22:02:30Z peter $");
 
 #include <libyasm.h>
 
@@ -523,8 +522,8 @@ stringconst_scan:
     SCANINIT();
 
     /*!re2c
-        /* Handle escaped double-quote by copying and continuing */
-        "\\\""      {
+        /* Handle escaped character by copying both and continuing. */
+        "\\".   {
             if (cursor == s->eof) {
                 yasm_error_set(YASM_ERROR_SYNTAX,
                                N_("unexpected end of file in string"));
@@ -532,7 +531,8 @@ stringconst_scan:
                 lvalp->str.len = count;
                 RETURN(STRING);
             }
-            strbuf_append(count++, cursor, s, '"');
+            strbuf_append(count++, cursor, s, '\\');
+            strbuf_append(count++, cursor, s, s->tok[1]);
             goto stringconst_scan;
         }
 
diff --git a/modules/parsers/nasm/nasm-parse.c b/modules/parsers/nasm/nasm-parse.c
index 8eab90e..44d3b5d 100644
--- a/modules/parsers/nasm/nasm-parse.c
+++ b/modules/parsers/nasm/nasm-parse.c
@@ -25,7 +25,6 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include <util.h>
-RCSID("$Id: nasm-parse.c 2323 2010-05-16 03:37:00Z peter $");
 
 #include <libyasm.h>
 
diff --git a/modules/parsers/nasm/nasm-parser-struct.h b/modules/parsers/nasm/nasm-parser-struct.h
index 3cdfa25..b922351 100644
--- a/modules/parsers/nasm/nasm-parser-struct.h
+++ b/modules/parsers/nasm/nasm-parser-struct.h
@@ -1,4 +1,4 @@
-/* $Id: nasm-parser-struct.h 2277 2010-01-19 07:03:15Z peter $
+/*
  * NASM-compatible parser struct header file
  *
  *  Copyright (C) 2002-2007  Peter Johnson
diff --git a/modules/parsers/nasm/nasm-parser.c b/modules/parsers/nasm/nasm-parser.c
index 263ee58..bd16692 100644
--- a/modules/parsers/nasm/nasm-parser.c
+++ b/modules/parsers/nasm/nasm-parser.c
@@ -25,7 +25,6 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include <util.h>
-/*@unused@*/ RCSID("$Id: nasm-parser.c 2277 2010-01-19 07:03:15Z peter $");
 
 #include <libyasm.h>
 
diff --git a/modules/parsers/nasm/nasm-parser.h b/modules/parsers/nasm/nasm-parser.h
index 7b31af5..dc19cfb 100644
--- a/modules/parsers/nasm/nasm-parser.h
+++ b/modules/parsers/nasm/nasm-parser.h
@@ -1,4 +1,4 @@
-/* $Id: nasm-parser.h 2277 2010-01-19 07:03:15Z peter $
+/*
  * NASM-compatible parser header file
  *
  *  Copyright (C) 2002-2007  Peter Johnson
diff --git a/modules/parsers/nasm/nasm-std.mac b/modules/parsers/nasm/nasm-std.mac
index 3c9223a..bb6e5c4 100644
--- a/modules/parsers/nasm/nasm-std.mac
+++ b/modules/parsers/nasm/nasm-std.mac
@@ -25,14 +25,14 @@
 	  __SECT__
 %endmacro
 
-%imacro struc 1.nolist
+%imacro struc 1-2.nolist 0
 %push struc
 %define %$strucname %1
-[absolute 0]
+[absolute %2]
 %$strucname:			; allow definition of `.member' to work sanely
 %endmacro 
 %imacro endstruc 0.nolist
-%{$strucname}_size:
+%{$strucname}_size EQU $ - %$strucname
 %pop
 __SECT__
 %endmacro
diff --git a/modules/parsers/nasm/nasm-token.re b/modules/parsers/nasm/nasm-token.re
index 9627724..dba7137 100644
--- a/modules/parsers/nasm/nasm-token.re
+++ b/modules/parsers/nasm/nasm-token.re
@@ -27,7 +27,6 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include <util.h>
-RCSID("$Id: nasm-token.re 2277 2010-01-19 07:03:15Z peter $");
 
 #include <libyasm.h>
 
diff --git a/modules/preprocs/nasm/genversion.c b/modules/preprocs/nasm/genversion.c
index 3d2fe30..164b4d6 100644
--- a/modules/preprocs/nasm/genversion.c
+++ b/modules/preprocs/nasm/genversion.c
@@ -1,4 +1,4 @@
-/* $Id: genversion.c 2082 2008-05-09 06:46:02Z peter $
+/*
  *
  * Generate version.mac
  *
@@ -36,14 +36,19 @@ int
 main(int argc, char *argv[])
 {
     FILE *out;
-    int major, minor, subminor;
+    int major, minor, subminor, patchlevel, matched;
 
     if (argc != 2) {
         fprintf(stderr, "Usage: %s <outfile>\n", argv[0]);
         return EXIT_FAILURE;
     }
 
-    if (sscanf(PACKAGE_INTVER, "%d.%d.%d", &major, &minor, &subminor) != 3) {
+    matched = sscanf(PACKAGE_VERSION, "%d.%d.%d.%d", &major, &minor, &subminor,
+                     &patchlevel);
+
+    if (matched == 3)
+        patchlevel = 0;
+    else if (matched != 4) {
         fprintf(stderr, "Version tokenizing error\n");
         return EXIT_FAILURE;
     }
@@ -61,17 +66,15 @@ main(int argc, char *argv[])
     fprintf(out, "%%define __YASM_MAJOR__ %d\n", major);
     fprintf(out, "%%define __YASM_MINOR__ %d\n", minor);
     fprintf(out, "%%define __YASM_SUBMINOR__ %d\n", subminor);
-    if (!isdigit(PACKAGE_BUILD[0]))
-        fprintf(out, "%%define __YASM_BUILD__ 0\n");
-    else
-        fprintf(out, "%%define __YASM_BUILD__ %d\n", atoi(PACKAGE_BUILD));
+    fprintf(out, "%%define __YASM_BUILD__ %d\n", patchlevel);
+    fprintf(out, "%%define __YASM_PATCHLEVEL__ %d\n", patchlevel);
 
     /* Version id (hex number) */
-    fprintf(out, "%%define __YASM_VERSION_ID__ 0%02x%02x%02x00h\n", major,
-            minor, subminor);
+    fprintf(out, "%%define __YASM_VERSION_ID__ 0%02x%02x%02x%02xh\n", major,
+            minor, subminor, patchlevel);
 
-    /* Version string - version sans build */
-    fprintf(out, "%%define __YASM_VER__ \"%s\"\n", PACKAGE_INTVER);
+    /* Version string */
+    fprintf(out, "%%define __YASM_VER__ \"%s\"\n", PACKAGE_VERSION);
     fclose(out);
 
     return EXIT_SUCCESS;
diff --git a/modules/preprocs/nasm/nasm-pp.c b/modules/preprocs/nasm/nasm-pp.c
index b892a64..06eaa9a 100644
--- a/modules/preprocs/nasm/nasm-pp.c
+++ b/modules/preprocs/nasm/nasm-pp.c
@@ -5307,6 +5307,7 @@ make_tok_num(Token * tok, yasm_intnum *val)
 {
     tok->text = yasm_intnum_get_str(val);
     tok->type = TOK_NUMBER;
+    yasm_intnum_destroy(val);
 }
 
 Preproc nasmpp = {
diff --git a/modules/preprocs/nasm/nasm-preproc.c b/modules/preprocs/nasm/nasm-preproc.c
index 8dfe156..0b364b1 100644
--- a/modules/preprocs/nasm/nasm-preproc.c
+++ b/modules/preprocs/nasm/nasm-preproc.c
@@ -25,7 +25,6 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include <util.h>
-/*@unused@*/ RCSID("$Id: nasm-preproc.c 2185 2009-03-24 06:33:32Z peter $");
 
 #include <libyasm.h>
 
diff --git a/modules/preprocs/raw/raw-preproc.c b/modules/preprocs/raw/raw-preproc.c
index bcbc90c..15fd783 100644
--- a/modules/preprocs/raw/raw-preproc.c
+++ b/modules/preprocs/raw/raw-preproc.c
@@ -25,7 +25,6 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include <util.h>
-/*@unused@*/ RCSID("$Id: raw-preproc.c 2172 2009-01-27 06:38:14Z peter $");
 
 #include <libyasm.h>
 
diff --git a/test_hd.c b/test_hd.c
index 9f48afb..8ae5cab 100644
--- a/test_hd.c
+++ b/test_hd.c
@@ -1,4 +1,4 @@
-/* $Id: test_hd.c 1827 2007-04-22 05:09:49Z peter $
+/*
  *
  * Simple hexidecimal dump, two hex digits per line.
  *
diff --git a/tools/Makefile.inc b/tools/Makefile.inc
index 939bf30..dbc67fc 100644
--- a/tools/Makefile.inc
+++ b/tools/Makefile.inc
@@ -1,5 +1,3 @@
-# $Id: Makefile.inc 2084 2008-05-09 07:08:17Z peter $
-
 EXTRA_DIST += tools/re2c/Makefile.inc
 EXTRA_DIST += tools/genmacro/Makefile.inc
 EXTRA_DIST += tools/genperf/Makefile.inc
diff --git a/tools/genmacro/Makefile.inc b/tools/genmacro/Makefile.inc
index 89b33b1..722f95d 100644
--- a/tools/genmacro/Makefile.inc
+++ b/tools/genmacro/Makefile.inc
@@ -1,5 +1,3 @@
-# $Id: Makefile.inc 2234 2009-10-31 21:52:42Z peter $
-
 # These utility programs have to be built for BUILD host in cross-build.
 # This makes things rather non-standard automake
 
diff --git a/tools/genmacro/genmacro.c b/tools/genmacro/genmacro.c
index e25e5a7..8e702b8 100644
--- a/tools/genmacro/genmacro.c
+++ b/tools/genmacro/genmacro.c
@@ -1,4 +1,4 @@
-/* $Id: genmacro.c 2084 2008-05-09 07:08:17Z peter $
+/*
  *
  * C version of NASM's macros.pl
  *
diff --git a/tools/genperf/Makefile.inc b/tools/genperf/Makefile.inc
index 460a5f1..135da6b 100644
--- a/tools/genperf/Makefile.inc
+++ b/tools/genperf/Makefile.inc
@@ -1,5 +1,3 @@
-# $Id: Makefile.inc 2234 2009-10-31 21:52:42Z peter $
-
 # These utility programs have to be built for BUILD host in cross-build.
 # This makes things rather non-standard automake
 
diff --git a/tools/genperf/genperf.c b/tools/genperf/genperf.c
index 86d8af6..c3cfa76 100644
--- a/tools/genperf/genperf.c
+++ b/tools/genperf/genperf.c
@@ -1,4 +1,4 @@
-/* $Id: genperf.c 2235 2009-11-03 05:15:37Z peter $
+/*
  *
  * Generate Minimal Perfect Hash (genperf)
  *
diff --git a/tools/genperf/perfect.c b/tools/genperf/perfect.c
index 076e006..7cd6867 100644
--- a/tools/genperf/perfect.c
+++ b/tools/genperf/perfect.c
@@ -1,6 +1,4 @@
-/* Modified for use with yasm by Peter Johnson.
- * $Id: perfect.c 1942 2007-09-11 02:11:19Z peter $
- */
+/* Modified for use with yasm by Peter Johnson. */
 /*
 ------------------------------------------------------------------------------
 perfect.c: code to generate code for a hash for perfect hashing.
diff --git a/tools/re2c/Makefile.inc b/tools/re2c/Makefile.inc
index 9b1f43f..edb89a5 100644
--- a/tools/re2c/Makefile.inc
+++ b/tools/re2c/Makefile.inc
@@ -1,5 +1,3 @@
-# $Id: Makefile.inc 2234 2009-10-31 21:52:42Z peter $
-
 # These utility programs have to be built for BUILD host in cross-build.
 # This makes things rather non-standard automake
 
diff --git a/util.h b/util.h
index fa69c27..634aa32 100644
--- a/util.h
+++ b/util.h
@@ -1,4 +1,4 @@
-/* $Id: util.h 2273 2010-01-13 04:44:28Z peter $
+/*
  * YASM utility functions.
  *
  * Includes standard headers and defines prototypes for replacement functions
@@ -119,18 +119,6 @@
 
 #include <libyasm/compat-queue.h>
 
-#ifdef HAVE_SYS_CDEFS_H
-# include <sys/cdefs.h>
-#endif
-
-#ifdef __RCSID
-# define RCSID(s)       __RCSID(s)
-#elif defined(__GNUC__) && defined(__ELF__)
-# define RCSID(s)       __asm__(".ident\t\"" s "\"")
-#else
-# define RCSID(s)       static const char rcsid[] = s
-#endif
-
 #ifdef WITH_DMALLOC
 # include <dmalloc.h>
 # define yasm__xstrdup(str)             xstrdup(str)
diff --git a/x86insn_gas.gperf b/x86insn_gas.gperf
index 370bb9c..bc84beb 100644
--- a/x86insn_gas.gperf
+++ b/x86insn_gas.gperf
@@ -1,4 +1,4 @@
-/* Generated by gen_x86_insn.py r2346, do not edit */
+/* Generated by gen_x86_insn.py rHEAD, do not edit */
 %ignore-case
 %language=ANSI-C
 %compare-strncmp
@@ -21,10 +21,9 @@ adcw,	arith_insn,	22,	SUF_W,	0x10,	0x02,	0,	0,	0,	0,	0
 add,	arith_insn,	22,	SUF_Z,	0x00,	0x00,	0,	0,	0,	0,	0
 addb,	arith_insn,	22,	SUF_B,	0x00,	0x00,	0,	0,	0,	0,	0
 addl,	arith_insn,	22,	SUF_L,	0x00,	0x00,	0,	0,	CPU_386,	0,	0
-addq,	arith_insn,	22,	SUF_Q,	0x00,	0x00,	0,	ONLY_64,	0,	0,	0
-addw,	arith_insn,	22,	SUF_W,	0x00,	0x00,	0,	0,	0,	0,	0
 addpd,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0x58,	0,	0,	CPU_SSE2,	0,	0
 addps,	xmm_xmm128_insn,	2,	SUF_Z,	0x00,	0x58,	0,	0,	CPU_SSE,	0,	0
+addq,	arith_insn,	22,	SUF_Q,	0x00,	0x00,	0,	ONLY_64,	0,	0,	0
 addr16,	NULL,	X86_ADDRSIZE>>8,	0x10,	0,	0,	0,	0,	0,	0,	0
 addr32,	NULL,	X86_ADDRSIZE>>8,	0x20,	0,	0,	0,	0,	0,	0,	0
 addr64,	NULL,	X86_ADDRSIZE>>8,	0x40,	0,	0,	0,	ONLY_64,	0,	0,	0
@@ -32,6 +31,7 @@ addsd,	xmm_xmm64_insn,	4,	SUF_Z,	0xF2,	0x58,	0,	0,	CPU_SSE2,	0,	0
 addss,	xmm_xmm32_insn,	4,	SUF_Z,	0xF3,	0x58,	0,	0,	CPU_SSE,	0,	0
 addsubpd,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0xD0,	0,	0,	CPU_SSE3,	0,	0
 addsubps,	xmm_xmm128_insn,	2,	SUF_Z,	0xF2,	0xD0,	0,	0,	CPU_SSE3,	0,	0
+addw,	arith_insn,	22,	SUF_W,	0x00,	0x00,	0,	0,	0,	0,	0
 adword,	NULL,	X86_ADDRSIZE>>8,	0x20,	0,	0,	0,	0,	0,	0,	0
 aesdec,	aes_insn,	2,	SUF_Z,	0x38,	0xDE,	0,	0,	CPU_AVX,	0,	0
 aesdeclast,	aes_insn,	2,	SUF_Z,	0x38,	0xDF,	0,	0,	CPU_AVX,	0,	0
@@ -42,20 +42,35 @@ aeskeygenassist,	aes_imm_insn,	1,	SUF_Z,	0x3A,	0xDF,	0,	0,	CPU_AES,	0,	0
 and,	arith_insn,	22,	SUF_Z,	0x20,	0x04,	0,	0,	0,	0,	0
 andb,	arith_insn,	22,	SUF_B,	0x20,	0x04,	0,	0,	0,	0,	0
 andl,	arith_insn,	22,	SUF_L,	0x20,	0x04,	0,	0,	CPU_386,	0,	0
-andq,	arith_insn,	22,	SUF_Q,	0x20,	0x04,	0,	ONLY_64,	0,	0,	0
-andw,	arith_insn,	22,	SUF_W,	0x20,	0x04,	0,	0,	0,	0,	0
+andn,	vex_gpr_reg_nds_rm_0F_insn,	2,	SUF_Z,	0x00,	0x38,	0xF2,	ONLY_AVX,	CPU_BMI1,	0,	0
+andnl,	vex_gpr_reg_nds_rm_0F_insn,	2,	SUF_L,	0x00,	0x38,	0xF2,	ONLY_AVX,	CPU_BMI1,	0,	0
 andnpd,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0x55,	0,	0,	CPU_SSE2,	0,	0
 andnps,	xmm_xmm128_insn,	2,	SUF_Z,	0x00,	0x55,	0,	0,	CPU_SSE,	0,	0
+andnq,	vex_gpr_reg_nds_rm_0F_insn,	2,	SUF_Q,	0x00,	0x38,	0xF2,	ONLY_64|ONLY_AVX,	CPU_BMI1,	0,	0
 andpd,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0x54,	0,	0,	CPU_SSE2,	0,	0
 andps,	xmm_xmm128_insn,	2,	SUF_Z,	0x00,	0x54,	0,	0,	CPU_SSE,	0,	0
+andq,	arith_insn,	22,	SUF_Q,	0x20,	0x04,	0,	ONLY_64,	0,	0,	0
+andw,	arith_insn,	22,	SUF_W,	0x20,	0x04,	0,	0,	0,	0,	0
 aqword,	NULL,	X86_ADDRSIZE>>8,	0x40,	0,	0,	0,	ONLY_64,	0,	0,	0
 arpl,	arpl_insn,	1,	SUF_Z,	0,	0,	0,	NOT_64,	CPU_286,	CPU_Prot,	0
 arplw,	arpl_insn,	1,	SUF_W,	0,	0,	0,	NOT_64,	CPU_286,	CPU_Prot,	0
 aword,	NULL,	X86_ADDRSIZE>>8,	0x10,	0,	0,	0,	0,	0,	0,	0
+bextr,	vex_gpr_reg_rm_nds_0F_insn,	2,	SUF_Z,	0x00,	0x38,	0xF7,	ONLY_AVX,	CPU_BMI1,	0,	0
+bextrl,	vex_gpr_reg_rm_nds_0F_insn,	2,	SUF_L,	0x00,	0x38,	0xF7,	ONLY_AVX,	CPU_BMI1,	0,	0
+bextrq,	vex_gpr_reg_rm_nds_0F_insn,	2,	SUF_Q,	0x00,	0x38,	0xF7,	ONLY_64|ONLY_AVX,	CPU_BMI1,	0,	0
 blendpd,	sse4imm_insn,	2,	SUF_Z,	0x0D,	0,	0,	0,	CPU_SSE41,	0,	0
 blendps,	sse4imm_insn,	2,	SUF_Z,	0x0C,	0,	0,	0,	CPU_SSE41,	0,	0
 blendvpd,	sse4xmm0_insn,	2,	SUF_Z,	0x15,	0,	0,	0,	CPU_SSE41,	0,	0
 blendvps,	sse4xmm0_insn,	2,	SUF_Z,	0x14,	0,	0,	0,	CPU_SSE41,	0,	0
+blsi,	vex_gpr_ndd_rm_0F38_regext_insn,	2,	SUF_Z,	0x00,	0xF3,	0x03,	ONLY_AVX,	CPU_BMI1,	0,	0
+blsil,	vex_gpr_ndd_rm_0F38_regext_insn,	2,	SUF_L,	0x00,	0xF3,	0x03,	ONLY_64|ONLY_AVX,	CPU_BMI1,	0,	0
+blsiw,	vex_gpr_ndd_rm_0F38_regext_insn,	2,	SUF_W,	0x00,	0xF3,	0x03,	ONLY_AVX,	CPU_BMI1,	0,	0
+blsmsk,	vex_gpr_ndd_rm_0F38_regext_insn,	2,	SUF_Z,	0x00,	0xF3,	0x02,	ONLY_AVX,	CPU_BMI1,	0,	0
+blsmskl,	vex_gpr_ndd_rm_0F38_regext_insn,	2,	SUF_L,	0x00,	0xF3,	0x02,	ONLY_64|ONLY_AVX,	CPU_BMI1,	0,	0
+blsmskw,	vex_gpr_ndd_rm_0F38_regext_insn,	2,	SUF_W,	0x00,	0xF3,	0x02,	ONLY_AVX,	CPU_BMI1,	0,	0
+blsr,	vex_gpr_ndd_rm_0F38_regext_insn,	2,	SUF_Z,	0x00,	0xF3,	0x01,	ONLY_AVX,	CPU_BMI1,	0,	0
+blsrl,	vex_gpr_ndd_rm_0F38_regext_insn,	2,	SUF_L,	0x00,	0xF3,	0x01,	ONLY_64|ONLY_AVX,	CPU_BMI1,	0,	0
+blsrw,	vex_gpr_ndd_rm_0F38_regext_insn,	2,	SUF_W,	0x00,	0xF3,	0x01,	ONLY_AVX,	CPU_BMI1,	0,	0
 bound,	bound_insn,	2,	SUF_Z,	0,	0,	0,	NOT_64,	CPU_186,	0,	0
 boundl,	bound_insn,	2,	SUF_L,	0,	0,	0,	NOT_64,	CPU_386,	0,	0
 boundw,	bound_insn,	2,	SUF_W,	0,	0,	0,	NOT_64,	CPU_186,	0,	0
@@ -71,13 +86,12 @@ bswap,	bswap_insn,	2,	SUF_Z,	0,	0,	0,	0,	CPU_486,	0,	0
 bswapl,	bswap_insn,	2,	SUF_L,	0,	0,	0,	0,	CPU_486,	0,	0
 bswapq,	bswap_insn,	2,	SUF_Q,	0,	0,	0,	ONLY_64,	0,	0,	0
 bt,	bittest_insn,	6,	SUF_Z,	0xA3,	0x04,	0,	0,	CPU_386,	0,	0
-btl,	bittest_insn,	6,	SUF_L,	0xA3,	0x04,	0,	0,	CPU_386,	0,	0
-btq,	bittest_insn,	6,	SUF_Q,	0xA3,	0x04,	0,	ONLY_64,	CPU_386,	0,	0
-btw,	bittest_insn,	6,	SUF_W,	0xA3,	0x04,	0,	0,	CPU_386,	0,	0
 btc,	bittest_insn,	6,	SUF_Z,	0xBB,	0x07,	0,	0,	CPU_386,	0,	0
 btcl,	bittest_insn,	6,	SUF_L,	0xBB,	0x07,	0,	0,	CPU_386,	0,	0
 btcq,	bittest_insn,	6,	SUF_Q,	0xBB,	0x07,	0,	ONLY_64,	CPU_386,	0,	0
 btcw,	bittest_insn,	6,	SUF_W,	0xBB,	0x07,	0,	0,	CPU_386,	0,	0
+btl,	bittest_insn,	6,	SUF_L,	0xA3,	0x04,	0,	0,	CPU_386,	0,	0
+btq,	bittest_insn,	6,	SUF_Q,	0xA3,	0x04,	0,	ONLY_64,	CPU_386,	0,	0
 btr,	bittest_insn,	6,	SUF_Z,	0xB3,	0x06,	0,	0,	CPU_386,	0,	0
 btrl,	bittest_insn,	6,	SUF_L,	0xB3,	0x06,	0,	0,	CPU_386,	0,	0
 btrq,	bittest_insn,	6,	SUF_Q,	0xB3,	0x06,	0,	ONLY_64,	CPU_386,	0,	0
@@ -86,6 +100,10 @@ bts,	bittest_insn,	6,	SUF_Z,	0xAB,	0x05,	0,	0,	CPU_386,	0,	0
 btsl,	bittest_insn,	6,	SUF_L,	0xAB,	0x05,	0,	0,	CPU_386,	0,	0
 btsq,	bittest_insn,	6,	SUF_Q,	0xAB,	0x05,	0,	ONLY_64,	CPU_386,	0,	0
 btsw,	bittest_insn,	6,	SUF_W,	0xAB,	0x05,	0,	0,	CPU_386,	0,	0
+btw,	bittest_insn,	6,	SUF_W,	0xA3,	0x04,	0,	0,	CPU_386,	0,	0
+bzhi,	vex_gpr_reg_rm_nds_0F_insn,	2,	SUF_Z,	0x00,	0x38,	0xF5,	ONLY_AVX,	CPU_BMI2,	0,	0
+bzhil,	vex_gpr_reg_rm_nds_0F_insn,	2,	SUF_L,	0x00,	0x38,	0xF5,	ONLY_AVX,	CPU_BMI2,	0,	0
+bzhiq,	vex_gpr_reg_rm_nds_0F_insn,	2,	SUF_Q,	0x00,	0x38,	0xF5,	ONLY_64|ONLY_AVX,	CPU_BMI2,	0,	0
 call,	call_insn,	30,	SUF_Z,	0,	0,	0,	0,	0,	0,	0
 calll,	call_insn,	30,	SUF_L,	0,	0,	0,	0,	CPU_386,	0,	0
 callq,	call_insn,	30,	SUF_Q,	0,	0,	0,	ONLY_64,	0,	0,	0
@@ -104,21 +122,21 @@ cltq,	onebyte_insn,	1,	SUF_Z,	0x98,	0x40,	0,	ONLY_64,	0,	0,	0
 clts,	twobyte_insn,	1,	SUF_Z,	0x0F,	0x06,	0,	0,	CPU_286,	CPU_Priv,	0
 cmc,	onebyte_insn,	1,	SUF_Z,	0xF5,	0,	0,	0,	0,	0,	0
 cmova,	cmovcc_insn,	3,	SUF_Z,	0x07,	0,	0,	0,	CPU_686,	0,	0
-cmoval,	cmovcc_insn,	3,	SUF_L,	0x07,	0,	0,	0,	CPU_686,	0,	0
-cmovaq,	cmovcc_insn,	3,	SUF_Q,	0x07,	0,	0,	ONLY_64,	CPU_686,	0,	0
-cmovaw,	cmovcc_insn,	3,	SUF_W,	0x07,	0,	0,	0,	CPU_686,	0,	0
 cmovae,	cmovcc_insn,	3,	SUF_Z,	0x03,	0,	0,	0,	CPU_686,	0,	0
 cmovael,	cmovcc_insn,	3,	SUF_L,	0x03,	0,	0,	0,	CPU_686,	0,	0
 cmovaeq,	cmovcc_insn,	3,	SUF_Q,	0x03,	0,	0,	ONLY_64,	CPU_686,	0,	0
 cmovaew,	cmovcc_insn,	3,	SUF_W,	0x03,	0,	0,	0,	CPU_686,	0,	0
+cmoval,	cmovcc_insn,	3,	SUF_L,	0x07,	0,	0,	0,	CPU_686,	0,	0
+cmovaq,	cmovcc_insn,	3,	SUF_Q,	0x07,	0,	0,	ONLY_64,	CPU_686,	0,	0
+cmovaw,	cmovcc_insn,	3,	SUF_W,	0x07,	0,	0,	0,	CPU_686,	0,	0
 cmovb,	cmovcc_insn,	3,	SUF_Z,	0x02,	0,	0,	0,	CPU_686,	0,	0
-cmovbl,	cmovcc_insn,	3,	SUF_L,	0x02,	0,	0,	0,	CPU_686,	0,	0
-cmovbq,	cmovcc_insn,	3,	SUF_Q,	0x02,	0,	0,	ONLY_64,	CPU_686,	0,	0
-cmovbw,	cmovcc_insn,	3,	SUF_W,	0x02,	0,	0,	0,	CPU_686,	0,	0
 cmovbe,	cmovcc_insn,	3,	SUF_Z,	0x06,	0,	0,	0,	CPU_686,	0,	0
 cmovbel,	cmovcc_insn,	3,	SUF_L,	0x06,	0,	0,	0,	CPU_686,	0,	0
 cmovbeq,	cmovcc_insn,	3,	SUF_Q,	0x06,	0,	0,	ONLY_64,	CPU_686,	0,	0
 cmovbew,	cmovcc_insn,	3,	SUF_W,	0x06,	0,	0,	0,	CPU_686,	0,	0
+cmovbl,	cmovcc_insn,	3,	SUF_L,	0x02,	0,	0,	0,	CPU_686,	0,	0
+cmovbq,	cmovcc_insn,	3,	SUF_Q,	0x02,	0,	0,	ONLY_64,	CPU_686,	0,	0
+cmovbw,	cmovcc_insn,	3,	SUF_W,	0x02,	0,	0,	0,	CPU_686,	0,	0
 cmovc,	cmovcc_insn,	3,	SUF_Z,	0x02,	0,	0,	0,	CPU_686,	0,	0
 cmovcl,	cmovcc_insn,	3,	SUF_L,	0x02,	0,	0,	0,	CPU_686,	0,	0
 cmovcq,	cmovcc_insn,	3,	SUF_Q,	0x02,	0,	0,	ONLY_64,	CPU_686,	0,	0
@@ -128,37 +146,37 @@ cmovel,	cmovcc_insn,	3,	SUF_L,	0x04,	0,	0,	0,	CPU_686,	0,	0
 cmoveq,	cmovcc_insn,	3,	SUF_Q,	0x04,	0,	0,	ONLY_64,	CPU_686,	0,	0
 cmovew,	cmovcc_insn,	3,	SUF_W,	0x04,	0,	0,	0,	CPU_686,	0,	0
 cmovg,	cmovcc_insn,	3,	SUF_Z,	0x0F,	0,	0,	0,	CPU_686,	0,	0
-cmovgl,	cmovcc_insn,	3,	SUF_L,	0x0F,	0,	0,	0,	CPU_686,	0,	0
-cmovgq,	cmovcc_insn,	3,	SUF_Q,	0x0F,	0,	0,	ONLY_64,	CPU_686,	0,	0
-cmovgw,	cmovcc_insn,	3,	SUF_W,	0x0F,	0,	0,	0,	CPU_686,	0,	0
 cmovge,	cmovcc_insn,	3,	SUF_Z,	0x0D,	0,	0,	0,	CPU_686,	0,	0
 cmovgel,	cmovcc_insn,	3,	SUF_L,	0x0D,	0,	0,	0,	CPU_686,	0,	0
 cmovgeq,	cmovcc_insn,	3,	SUF_Q,	0x0D,	0,	0,	ONLY_64,	CPU_686,	0,	0
 cmovgew,	cmovcc_insn,	3,	SUF_W,	0x0D,	0,	0,	0,	CPU_686,	0,	0
+cmovgl,	cmovcc_insn,	3,	SUF_L,	0x0F,	0,	0,	0,	CPU_686,	0,	0
+cmovgq,	cmovcc_insn,	3,	SUF_Q,	0x0F,	0,	0,	ONLY_64,	CPU_686,	0,	0
+cmovgw,	cmovcc_insn,	3,	SUF_W,	0x0F,	0,	0,	0,	CPU_686,	0,	0
 cmovl,	cmovcc_insn,	3,	SUF_Z,	0x0C,	0,	0,	0,	CPU_686,	0,	0
-cmovll,	cmovcc_insn,	3,	SUF_L,	0x0C,	0,	0,	0,	CPU_686,	0,	0
-cmovlq,	cmovcc_insn,	3,	SUF_Q,	0x0C,	0,	0,	ONLY_64,	CPU_686,	0,	0
-cmovlw,	cmovcc_insn,	3,	SUF_W,	0x0C,	0,	0,	0,	CPU_686,	0,	0
 cmovle,	cmovcc_insn,	3,	SUF_Z,	0x0E,	0,	0,	0,	CPU_686,	0,	0
 cmovlel,	cmovcc_insn,	3,	SUF_L,	0x0E,	0,	0,	0,	CPU_686,	0,	0
 cmovleq,	cmovcc_insn,	3,	SUF_Q,	0x0E,	0,	0,	ONLY_64,	CPU_686,	0,	0
 cmovlew,	cmovcc_insn,	3,	SUF_W,	0x0E,	0,	0,	0,	CPU_686,	0,	0
+cmovll,	cmovcc_insn,	3,	SUF_L,	0x0C,	0,	0,	0,	CPU_686,	0,	0
+cmovlq,	cmovcc_insn,	3,	SUF_Q,	0x0C,	0,	0,	ONLY_64,	CPU_686,	0,	0
+cmovlw,	cmovcc_insn,	3,	SUF_W,	0x0C,	0,	0,	0,	CPU_686,	0,	0
 cmovna,	cmovcc_insn,	3,	SUF_Z,	0x06,	0,	0,	0,	CPU_686,	0,	0
-cmovnal,	cmovcc_insn,	3,	SUF_L,	0x06,	0,	0,	0,	CPU_686,	0,	0
-cmovnaq,	cmovcc_insn,	3,	SUF_Q,	0x06,	0,	0,	ONLY_64,	CPU_686,	0,	0
-cmovnaw,	cmovcc_insn,	3,	SUF_W,	0x06,	0,	0,	0,	CPU_686,	0,	0
 cmovnae,	cmovcc_insn,	3,	SUF_Z,	0x02,	0,	0,	0,	CPU_686,	0,	0
 cmovnael,	cmovcc_insn,	3,	SUF_L,	0x02,	0,	0,	0,	CPU_686,	0,	0
 cmovnaeq,	cmovcc_insn,	3,	SUF_Q,	0x02,	0,	0,	ONLY_64,	CPU_686,	0,	0
 cmovnaew,	cmovcc_insn,	3,	SUF_W,	0x02,	0,	0,	0,	CPU_686,	0,	0
+cmovnal,	cmovcc_insn,	3,	SUF_L,	0x06,	0,	0,	0,	CPU_686,	0,	0
+cmovnaq,	cmovcc_insn,	3,	SUF_Q,	0x06,	0,	0,	ONLY_64,	CPU_686,	0,	0
+cmovnaw,	cmovcc_insn,	3,	SUF_W,	0x06,	0,	0,	0,	CPU_686,	0,	0
 cmovnb,	cmovcc_insn,	3,	SUF_Z,	0x03,	0,	0,	0,	CPU_686,	0,	0
-cmovnbl,	cmovcc_insn,	3,	SUF_L,	0x03,	0,	0,	0,	CPU_686,	0,	0
-cmovnbq,	cmovcc_insn,	3,	SUF_Q,	0x03,	0,	0,	ONLY_64,	CPU_686,	0,	0
-cmovnbw,	cmovcc_insn,	3,	SUF_W,	0x03,	0,	0,	0,	CPU_686,	0,	0
 cmovnbe,	cmovcc_insn,	3,	SUF_Z,	0x07,	0,	0,	0,	CPU_686,	0,	0
 cmovnbel,	cmovcc_insn,	3,	SUF_L,	0x07,	0,	0,	0,	CPU_686,	0,	0
 cmovnbeq,	cmovcc_insn,	3,	SUF_Q,	0x07,	0,	0,	ONLY_64,	CPU_686,	0,	0
 cmovnbew,	cmovcc_insn,	3,	SUF_W,	0x07,	0,	0,	0,	CPU_686,	0,	0
+cmovnbl,	cmovcc_insn,	3,	SUF_L,	0x03,	0,	0,	0,	CPU_686,	0,	0
+cmovnbq,	cmovcc_insn,	3,	SUF_Q,	0x03,	0,	0,	ONLY_64,	CPU_686,	0,	0
+cmovnbw,	cmovcc_insn,	3,	SUF_W,	0x03,	0,	0,	0,	CPU_686,	0,	0
 cmovnc,	cmovcc_insn,	3,	SUF_Z,	0x03,	0,	0,	0,	CPU_686,	0,	0
 cmovncl,	cmovcc_insn,	3,	SUF_L,	0x03,	0,	0,	0,	CPU_686,	0,	0
 cmovncq,	cmovcc_insn,	3,	SUF_Q,	0x03,	0,	0,	ONLY_64,	CPU_686,	0,	0
@@ -168,21 +186,21 @@ cmovnel,	cmovcc_insn,	3,	SUF_L,	0x05,	0,	0,	0,	CPU_686,	0,	0
 cmovneq,	cmovcc_insn,	3,	SUF_Q,	0x05,	0,	0,	ONLY_64,	CPU_686,	0,	0
 cmovnew,	cmovcc_insn,	3,	SUF_W,	0x05,	0,	0,	0,	CPU_686,	0,	0
 cmovng,	cmovcc_insn,	3,	SUF_Z,	0x0E,	0,	0,	0,	CPU_686,	0,	0
-cmovngl,	cmovcc_insn,	3,	SUF_L,	0x0E,	0,	0,	0,	CPU_686,	0,	0
-cmovngq,	cmovcc_insn,	3,	SUF_Q,	0x0E,	0,	0,	ONLY_64,	CPU_686,	0,	0
-cmovngw,	cmovcc_insn,	3,	SUF_W,	0x0E,	0,	0,	0,	CPU_686,	0,	0
 cmovnge,	cmovcc_insn,	3,	SUF_Z,	0x0C,	0,	0,	0,	CPU_686,	0,	0
 cmovngel,	cmovcc_insn,	3,	SUF_L,	0x0C,	0,	0,	0,	CPU_686,	0,	0
 cmovngeq,	cmovcc_insn,	3,	SUF_Q,	0x0C,	0,	0,	ONLY_64,	CPU_686,	0,	0
 cmovngew,	cmovcc_insn,	3,	SUF_W,	0x0C,	0,	0,	0,	CPU_686,	0,	0
+cmovngl,	cmovcc_insn,	3,	SUF_L,	0x0E,	0,	0,	0,	CPU_686,	0,	0
+cmovngq,	cmovcc_insn,	3,	SUF_Q,	0x0E,	0,	0,	ONLY_64,	CPU_686,	0,	0
+cmovngw,	cmovcc_insn,	3,	SUF_W,	0x0E,	0,	0,	0,	CPU_686,	0,	0
 cmovnl,	cmovcc_insn,	3,	SUF_Z,	0x0D,	0,	0,	0,	CPU_686,	0,	0
-cmovnll,	cmovcc_insn,	3,	SUF_L,	0x0D,	0,	0,	0,	CPU_686,	0,	0
-cmovnlq,	cmovcc_insn,	3,	SUF_Q,	0x0D,	0,	0,	ONLY_64,	CPU_686,	0,	0
-cmovnlw,	cmovcc_insn,	3,	SUF_W,	0x0D,	0,	0,	0,	CPU_686,	0,	0
 cmovnle,	cmovcc_insn,	3,	SUF_Z,	0x0F,	0,	0,	0,	CPU_686,	0,	0
 cmovnlel,	cmovcc_insn,	3,	SUF_L,	0x0F,	0,	0,	0,	CPU_686,	0,	0
 cmovnleq,	cmovcc_insn,	3,	SUF_Q,	0x0F,	0,	0,	ONLY_64,	CPU_686,	0,	0
 cmovnlew,	cmovcc_insn,	3,	SUF_W,	0x0F,	0,	0,	0,	CPU_686,	0,	0
+cmovnll,	cmovcc_insn,	3,	SUF_L,	0x0D,	0,	0,	0,	CPU_686,	0,	0
+cmovnlq,	cmovcc_insn,	3,	SUF_Q,	0x0D,	0,	0,	ONLY_64,	CPU_686,	0,	0
+cmovnlw,	cmovcc_insn,	3,	SUF_W,	0x0D,	0,	0,	0,	CPU_686,	0,	0
 cmovno,	cmovcc_insn,	3,	SUF_Z,	0x01,	0,	0,	0,	CPU_686,	0,	0
 cmovnol,	cmovcc_insn,	3,	SUF_L,	0x01,	0,	0,	0,	CPU_686,	0,	0
 cmovnoq,	cmovcc_insn,	3,	SUF_Q,	0x01,	0,	0,	ONLY_64,	CPU_686,	0,	0
@@ -204,17 +222,17 @@ cmovol,	cmovcc_insn,	3,	SUF_L,	0x00,	0,	0,	0,	CPU_686,	0,	0
 cmovoq,	cmovcc_insn,	3,	SUF_Q,	0x00,	0,	0,	ONLY_64,	CPU_686,	0,	0
 cmovow,	cmovcc_insn,	3,	SUF_W,	0x00,	0,	0,	0,	CPU_686,	0,	0
 cmovp,	cmovcc_insn,	3,	SUF_Z,	0x0A,	0,	0,	0,	CPU_686,	0,	0
-cmovpl,	cmovcc_insn,	3,	SUF_L,	0x0A,	0,	0,	0,	CPU_686,	0,	0
-cmovpq,	cmovcc_insn,	3,	SUF_Q,	0x0A,	0,	0,	ONLY_64,	CPU_686,	0,	0
-cmovpw,	cmovcc_insn,	3,	SUF_W,	0x0A,	0,	0,	0,	CPU_686,	0,	0
 cmovpe,	cmovcc_insn,	3,	SUF_Z,	0x0A,	0,	0,	0,	CPU_686,	0,	0
 cmovpel,	cmovcc_insn,	3,	SUF_L,	0x0A,	0,	0,	0,	CPU_686,	0,	0
 cmovpeq,	cmovcc_insn,	3,	SUF_Q,	0x0A,	0,	0,	ONLY_64,	CPU_686,	0,	0
 cmovpew,	cmovcc_insn,	3,	SUF_W,	0x0A,	0,	0,	0,	CPU_686,	0,	0
+cmovpl,	cmovcc_insn,	3,	SUF_L,	0x0A,	0,	0,	0,	CPU_686,	0,	0
 cmovpo,	cmovcc_insn,	3,	SUF_Z,	0x0B,	0,	0,	0,	CPU_686,	0,	0
 cmovpol,	cmovcc_insn,	3,	SUF_L,	0x0B,	0,	0,	0,	CPU_686,	0,	0
 cmovpoq,	cmovcc_insn,	3,	SUF_Q,	0x0B,	0,	0,	ONLY_64,	CPU_686,	0,	0
 cmovpow,	cmovcc_insn,	3,	SUF_W,	0x0B,	0,	0,	0,	CPU_686,	0,	0
+cmovpq,	cmovcc_insn,	3,	SUF_Q,	0x0A,	0,	0,	ONLY_64,	CPU_686,	0,	0
+cmovpw,	cmovcc_insn,	3,	SUF_W,	0x0A,	0,	0,	0,	CPU_686,	0,	0
 cmovs,	cmovcc_insn,	3,	SUF_Z,	0x08,	0,	0,	0,	CPU_686,	0,	0
 cmovsl,	cmovcc_insn,	3,	SUF_L,	0x08,	0,	0,	0,	CPU_686,	0,	0
 cmovsq,	cmovcc_insn,	3,	SUF_Q,	0x08,	0,	0,	ONLY_64,	CPU_686,	0,	0
@@ -225,13 +243,11 @@ cmovzq,	cmovcc_insn,	3,	SUF_Q,	0x04,	0,	0,	ONLY_64,	CPU_686,	0,	0
 cmovzw,	cmovcc_insn,	3,	SUF_W,	0x04,	0,	0,	0,	CPU_686,	0,	0
 cmp,	arith_insn,	22,	SUF_Z,	0x38,	0x07,	0,	0,	0,	0,	0
 cmpb,	arith_insn,	22,	SUF_B,	0x38,	0x07,	0,	0,	0,	0,	0
-cmpl,	arith_insn,	22,	SUF_L,	0x38,	0x07,	0,	0,	CPU_386,	0,	0
-cmpq,	arith_insn,	22,	SUF_Q,	0x38,	0x07,	0,	ONLY_64,	0,	0,	0
-cmpw,	arith_insn,	22,	SUF_W,	0x38,	0x07,	0,	0,	0,	0,	0
 cmpeqpd,	ssecmp_128_insn,	3,	SUF_Z,	0x00,	0x66,	0,	0,	CPU_SSE,	0,	0
 cmpeqps,	ssecmp_128_insn,	3,	SUF_Z,	0x00,	0,	0,	0,	CPU_SSE,	0,	0
 cmpeqsd,	ssecmp_64_insn,	4,	SUF_Z,	0x00,	0xF2,	0,	0,	CPU_SSE2,	0,	0
 cmpeqss,	ssecmp_32_insn,	4,	SUF_Z,	0x00,	0xF3,	0,	0,	CPU_SSE,	0,	0
+cmpl,	arith_insn,	22,	SUF_L,	0x38,	0x07,	0,	0,	CPU_386,	0,	0
 cmplepd,	ssecmp_128_insn,	3,	SUF_Z,	0x02,	0x66,	0,	0,	CPU_SSE,	0,	0
 cmpleps,	ssecmp_128_insn,	3,	SUF_Z,	0x02,	0,	0,	0,	CPU_SSE,	0,	0
 cmplesd,	ssecmp_64_insn,	4,	SUF_Z,	0x02,	0xF2,	0,	0,	CPU_SSE2,	0,	0
@@ -258,6 +274,7 @@ cmpordsd,	ssecmp_64_insn,	4,	SUF_Z,	0x07,	0xF2,	0,	0,	CPU_SSE2,	0,	0
 cmpordss,	ssecmp_32_insn,	4,	SUF_Z,	0x07,	0xF3,	0,	0,	CPU_SSE,	0,	0
 cmppd,	xmm_xmm128_imm_insn,	1,	SUF_Z,	0x66,	0xC2,	0,	0,	CPU_SSE2,	0,	0
 cmpps,	xmm_xmm128_imm_insn,	1,	SUF_Z,	0x00,	0xC2,	0,	0,	CPU_SSE,	0,	0
+cmpq,	arith_insn,	22,	SUF_Q,	0x38,	0x07,	0,	ONLY_64,	0,	0,	0
 cmpsb,	onebyte_insn,	1,	SUF_Z,	0xA6,	0x00,	0,	0,	0,	0,	0
 cmpsd,	cmpsd_insn,	5,	SUF_Z,	0,	0,	0,	0,	0,	0,	0
 cmpsl,	onebyte_insn,	1,	SUF_Z,	0xA7,	0x20,	0,	0,	CPU_386,	0,	0
@@ -268,6 +285,7 @@ cmpunordpd,	ssecmp_128_insn,	3,	SUF_Z,	0x03,	0x66,	0,	0,	CPU_SSE,	0,	0
 cmpunordps,	ssecmp_128_insn,	3,	SUF_Z,	0x03,	0,	0,	0,	CPU_SSE,	0,	0
 cmpunordsd,	ssecmp_64_insn,	4,	SUF_Z,	0x03,	0xF2,	0,	0,	CPU_SSE2,	0,	0
 cmpunordss,	ssecmp_32_insn,	4,	SUF_Z,	0x03,	0xF3,	0,	0,	CPU_SSE,	0,	0
+cmpw,	arith_insn,	22,	SUF_W,	0x38,	0x07,	0,	0,	0,	0,	0
 cmpxchg,	cmpxchgxadd_insn,	4,	SUF_Z,	0xB0,	0,	0,	0,	CPU_486,	0,	0
 cmpxchg16b,	cmpxchg16b_insn,	1,	SUF_Z,	0,	0,	0,	ONLY_64,	0,	0,	0
 cmpxchg8b,	cmpxchg8b_insn,	1,	SUF_Z,	0,	0,	0,	0,	CPU_586,	0,	0
@@ -337,12 +355,12 @@ decw,	incdec_insn,	6,	SUF_W,	0x48,	0x01,	0,	0,	0,	0,	0
 div,	div_insn,	8,	SUF_Z,	0x06,	0,	0,	0,	0,	0,	0
 divb,	div_insn,	8,	SUF_B,	0x06,	0,	0,	0,	0,	0,	0
 divl,	div_insn,	8,	SUF_L,	0x06,	0,	0,	0,	CPU_386,	0,	0
-divq,	div_insn,	8,	SUF_Q,	0x06,	0,	0,	ONLY_64,	0,	0,	0
-divw,	div_insn,	8,	SUF_W,	0x06,	0,	0,	0,	0,	0,	0
 divpd,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0x5E,	0,	0,	CPU_SSE2,	0,	0
 divps,	xmm_xmm128_insn,	2,	SUF_Z,	0x00,	0x5E,	0,	0,	CPU_SSE,	0,	0
+divq,	div_insn,	8,	SUF_Q,	0x06,	0,	0,	ONLY_64,	0,	0,	0
 divsd,	xmm_xmm64_insn,	4,	SUF_Z,	0xF2,	0x5E,	0,	0,	CPU_SSE2,	0,	0
 divss,	xmm_xmm32_insn,	4,	SUF_Z,	0xF3,	0x5E,	0,	0,	CPU_SSE,	0,	0
+divw,	div_insn,	8,	SUF_W,	0x06,	0,	0,	0,	0,	0,	0
 dppd,	sse4imm_insn,	2,	SUF_Z,	0x41,	0,	0,	0,	CPU_SSE41,	0,	0
 dpps,	sse4imm_insn,	2,	SUF_Z,	0x40,	0,	0,	0,	CPU_SSE41,	0,	0
 dword,	NULL,	X86_OPERSIZE>>8,	0x20,	0,	0,	0,	0,	0,	0,	0
@@ -357,8 +375,8 @@ f2xm1,	twobyte_insn,	1,	SUF_Z,	0xD9,	0xF0,	0,	0,	CPU_FPU,	0,	0
 fabs,	twobyte_insn,	1,	SUF_Z,	0xD9,	0xE1,	0,	0,	CPU_FPU,	0,	0
 fadd,	farith_insn,	7,	SUF_Z,	0xC0,	0xC0,	0x00,	0,	CPU_FPU,	0,	0
 faddl,	farith_insn,	7,	SUF_L,	0xC0,	0xC0,	0x00,	0,	CPU_FPU,	0,	0
-fadds,	farith_insn,	7,	SUF_S,	0xC0,	0xC0,	0x00,	0,	CPU_FPU,	0,	0
 faddp,	farithp_insn,	3,	SUF_Z,	0xC0,	0,	0,	0,	CPU_FPU,	0,	0
+fadds,	farith_insn,	7,	SUF_S,	0xC0,	0xC0,	0x00,	0,	CPU_FPU,	0,	0
 fbld,	fbldstp_insn,	1,	SUF_Z,	0x04,	0,	0,	0,	CPU_FPU,	0,	0
 fbstp,	fbldstp_insn,	1,	SUF_Z,	0x06,	0,	0,	0,	CPU_FPU,	0,	0
 fchs,	twobyte_insn,	1,	SUF_Z,	0xD9,	0xE0,	0,	0,	CPU_FPU,	0,	0
@@ -372,24 +390,24 @@ fcmovne,	fcmovcc_insn,	1,	SUF_Z,	0xDB,	0xC8,	0,	0,	CPU_686,	CPU_FPU,	0
 fcmovnu,	fcmovcc_insn,	1,	SUF_Z,	0xDB,	0xD8,	0,	0,	CPU_686,	CPU_FPU,	0
 fcmovu,	fcmovcc_insn,	1,	SUF_Z,	0xDA,	0xD8,	0,	0,	CPU_686,	CPU_FPU,	0
 fcom,	fcom_insn,	6,	SUF_Z,	0xD0,	0x02,	0,	0,	CPU_FPU,	0,	0
-fcoml,	fcom_insn,	6,	SUF_L,	0xD0,	0x02,	0,	0,	CPU_FPU,	0,	0
-fcoms,	fcom_insn,	6,	SUF_S,	0xD0,	0x02,	0,	0,	CPU_FPU,	0,	0
 fcomi,	fcom2_insn,	2,	SUF_Z,	0xDB,	0xF0,	0,	0,	CPU_686,	CPU_FPU,	0
 fcomip,	fcom2_insn,	2,	SUF_Z,	0xDF,	0xF0,	0,	0,	CPU_686,	CPU_FPU,	0
+fcoml,	fcom_insn,	6,	SUF_L,	0xD0,	0x02,	0,	0,	CPU_FPU,	0,	0
 fcomp,	fcom_insn,	6,	SUF_Z,	0xD8,	0x03,	0,	0,	CPU_FPU,	0,	0
 fcompl,	fcom_insn,	6,	SUF_L,	0xD8,	0x03,	0,	0,	CPU_FPU,	0,	0
-fcomps,	fcom_insn,	6,	SUF_S,	0xD8,	0x03,	0,	0,	CPU_FPU,	0,	0
 fcompp,	twobyte_insn,	1,	SUF_Z,	0xDE,	0xD9,	0,	0,	CPU_FPU,	0,	0
+fcomps,	fcom_insn,	6,	SUF_S,	0xD8,	0x03,	0,	0,	CPU_FPU,	0,	0
+fcoms,	fcom_insn,	6,	SUF_S,	0xD0,	0x02,	0,	0,	CPU_FPU,	0,	0
 fcos,	twobyte_insn,	1,	SUF_Z,	0xD9,	0xFF,	0,	0,	CPU_286,	CPU_FPU,	0
 fdecstp,	twobyte_insn,	1,	SUF_Z,	0xD9,	0xF6,	0,	0,	CPU_FPU,	0,	0
 fdiv,	farith_insn,	7,	SUF_Z,	0xF8,	0xF0,	0x06,	0,	CPU_FPU,	0,	0
 fdivl,	farith_insn,	7,	SUF_L,	0xF8,	0xF0,	0x06,	0,	CPU_FPU,	0,	0
-fdivs,	farith_insn,	7,	SUF_S,	0xF8,	0xF0,	0x06,	0,	CPU_FPU,	0,	0
 fdivp,	farithp_insn,	3,	SUF_Z,	0xF0,	0,	0,	0,	CPU_FPU,	0,	0
 fdivr,	farith_insn,	7,	SUF_Z,	0xF0,	0xF8,	0x07,	0,	CPU_FPU,	0,	0
 fdivrl,	farith_insn,	7,	SUF_L,	0xF0,	0xF8,	0x07,	0,	CPU_FPU,	0,	0
-fdivrs,	farith_insn,	7,	SUF_S,	0xF0,	0xF8,	0x07,	0,	CPU_FPU,	0,	0
 fdivrp,	farithp_insn,	3,	SUF_Z,	0xF8,	0,	0,	0,	CPU_FPU,	0,	0
+fdivrs,	farith_insn,	7,	SUF_S,	0xF0,	0xF8,	0x07,	0,	CPU_FPU,	0,	0
+fdivs,	farith_insn,	7,	SUF_S,	0xF8,	0xF0,	0x06,	0,	CPU_FPU,	0,	0
 femms,	twobyte_insn,	1,	SUF_Z,	0x0F,	0x0E,	0,	0,	CPU_3DNow,	0,	0
 ffree,	ffree_insn,	1,	SUF_Z,	0xDD,	0,	0,	0,	CPU_FPU,	0,	0
 ffreep,	ffree_insn,	1,	SUF_Z,	0xDF,	0,	0,	0,	CPU_686,	CPU_FPU,	CPU_Undoc
@@ -398,21 +416,21 @@ fiaddl,	fiarith_insn,	2,	SUF_L,	0x00,	0xDA,	0,	0,	CPU_FPU,	0,	0
 fiadds,	fiarith_insn,	2,	SUF_S,	0x00,	0xDA,	0,	0,	CPU_FPU,	0,	0
 ficom,	fiarith_insn,	2,	SUF_Z,	0x02,	0xDA,	0,	0,	CPU_FPU,	0,	0
 ficoml,	fiarith_insn,	2,	SUF_L,	0x02,	0xDA,	0,	0,	CPU_FPU,	0,	0
-ficoms,	fiarith_insn,	2,	SUF_S,	0x02,	0xDA,	0,	0,	CPU_FPU,	0,	0
 ficomp,	fiarith_insn,	2,	SUF_Z,	0x03,	0xDA,	0,	0,	CPU_FPU,	0,	0
 ficompl,	fiarith_insn,	2,	SUF_L,	0x03,	0xDA,	0,	0,	CPU_FPU,	0,	0
 ficomps,	fiarith_insn,	2,	SUF_S,	0x03,	0xDA,	0,	0,	CPU_FPU,	0,	0
+ficoms,	fiarith_insn,	2,	SUF_S,	0x02,	0xDA,	0,	0,	CPU_FPU,	0,	0
 fidiv,	fiarith_insn,	2,	SUF_Z,	0x06,	0xDA,	0,	0,	CPU_FPU,	0,	0
 fidivl,	fiarith_insn,	2,	SUF_L,	0x06,	0xDA,	0,	0,	CPU_FPU,	0,	0
-fidivs,	fiarith_insn,	2,	SUF_S,	0x06,	0xDA,	0,	0,	CPU_FPU,	0,	0
 fidivr,	fiarith_insn,	2,	SUF_Z,	0x07,	0xDA,	0,	0,	CPU_FPU,	0,	0
 fidivrl,	fiarith_insn,	2,	SUF_L,	0x07,	0xDA,	0,	0,	CPU_FPU,	0,	0
 fidivrs,	fiarith_insn,	2,	SUF_S,	0x07,	0xDA,	0,	0,	CPU_FPU,	0,	0
+fidivs,	fiarith_insn,	2,	SUF_S,	0x06,	0xDA,	0,	0,	CPU_FPU,	0,	0
 fild,	fildstp_insn,	4,	SUF_Z,	0x00,	0x02,	0x05,	0,	CPU_FPU,	0,	0
 fildl,	fildstp_insn,	4,	SUF_L,	0x00,	0x02,	0x05,	0,	CPU_FPU,	0,	0
+fildll,	fbldstp_insn,	1,	SUF_Z,	0x05,	0,	0,	0,	CPU_FPU,	0,	0
 fildq,	fildstp_insn,	4,	SUF_Q,	0x00,	0x02,	0x05,	0,	CPU_FPU,	0,	0
 filds,	fildstp_insn,	4,	SUF_S,	0x00,	0x02,	0x05,	0,	CPU_FPU,	0,	0
-fildll,	fbldstp_insn,	1,	SUF_Z,	0x05,	0,	0,	0,	CPU_FPU,	0,	0
 fimul,	fiarith_insn,	2,	SUF_Z,	0x01,	0xDA,	0,	0,	CPU_FPU,	0,	0
 fimull,	fiarith_insn,	2,	SUF_L,	0x01,	0xDA,	0,	0,	CPU_FPU,	0,	0
 fimuls,	fiarith_insn,	2,	SUF_S,	0x01,	0xDA,	0,	0,	CPU_FPU,	0,	0
@@ -420,54 +438,54 @@ fincstp,	twobyte_insn,	1,	SUF_Z,	0xD9,	0xF7,	0,	0,	CPU_FPU,	0,	0
 finit,	threebyte_insn,	1,	SUF_Z,	0x9B,	0xDB,	0xE3,	0,	CPU_FPU,	0,	0
 fist,	fiarith_insn,	2,	SUF_Z,	0x02,	0xDB,	0,	0,	CPU_FPU,	0,	0
 fistl,	fiarith_insn,	2,	SUF_L,	0x02,	0xDB,	0,	0,	CPU_FPU,	0,	0
-fists,	fiarith_insn,	2,	SUF_S,	0x02,	0xDB,	0,	0,	CPU_FPU,	0,	0
 fistp,	fildstp_insn,	4,	SUF_Z,	0x03,	0x02,	0x07,	0,	CPU_FPU,	0,	0
 fistpl,	fildstp_insn,	4,	SUF_L,	0x03,	0x02,	0x07,	0,	CPU_FPU,	0,	0
+fistpll,	fbldstp_insn,	1,	SUF_Z,	0x07,	0,	0,	0,	CPU_FPU,	0,	0
 fistpq,	fildstp_insn,	4,	SUF_Q,	0x03,	0x02,	0x07,	0,	CPU_FPU,	0,	0
 fistps,	fildstp_insn,	4,	SUF_S,	0x03,	0x02,	0x07,	0,	CPU_FPU,	0,	0
-fistpll,	fbldstp_insn,	1,	SUF_Z,	0x07,	0,	0,	0,	CPU_FPU,	0,	0
+fists,	fiarith_insn,	2,	SUF_S,	0x02,	0xDB,	0,	0,	CPU_FPU,	0,	0
 fisttp,	fildstp_insn,	4,	SUF_Z,	0x01,	0x00,	0x01,	0,	CPU_SSE3,	0,	0
 fisttpl,	fildstp_insn,	4,	SUF_L,	0x01,	0x00,	0x01,	0,	CPU_SSE3,	0,	0
+fisttpll,	fildstp_insn,	4,	SUF_Q,	0x07,	0,	0,	0,	CPU_SSE3,	0,	0
 fisttpq,	fildstp_insn,	4,	SUF_Q,	0x01,	0x00,	0x01,	0,	CPU_SSE3,	0,	0
 fisttps,	fildstp_insn,	4,	SUF_S,	0x01,	0x00,	0x01,	0,	CPU_SSE3,	0,	0
-fisttpll,	fildstp_insn,	4,	SUF_Z,	0x07,	0,	0,	0,	CPU_SSE3,	0,	0
 fisub,	fiarith_insn,	2,	SUF_Z,	0x04,	0xDA,	0,	0,	CPU_FPU,	0,	0
 fisubl,	fiarith_insn,	2,	SUF_L,	0x04,	0xDA,	0,	0,	CPU_FPU,	0,	0
-fisubs,	fiarith_insn,	2,	SUF_S,	0x04,	0xDA,	0,	0,	CPU_FPU,	0,	0
 fisubr,	fiarith_insn,	2,	SUF_Z,	0x05,	0xDA,	0,	0,	CPU_FPU,	0,	0
 fisubrl,	fiarith_insn,	2,	SUF_L,	0x05,	0xDA,	0,	0,	CPU_FPU,	0,	0
 fisubrs,	fiarith_insn,	2,	SUF_S,	0x05,	0xDA,	0,	0,	CPU_FPU,	0,	0
+fisubs,	fiarith_insn,	2,	SUF_S,	0x04,	0xDA,	0,	0,	CPU_FPU,	0,	0
 fld,	fld_insn,	4,	SUF_Z,	0,	0,	0,	0,	CPU_FPU,	0,	0
 fld1,	twobyte_insn,	1,	SUF_Z,	0xD9,	0xE8,	0,	0,	CPU_FPU,	0,	0
-fldl,	fld_insn,	4,	SUF_L,	0,	0,	0,	0,	CPU_FPU,	0,	0
-flds,	fld_insn,	4,	SUF_S,	0,	0,	0,	0,	CPU_FPU,	0,	0
 fldcw,	fldnstcw_insn,	1,	SUF_Z,	0x05,	0,	0,	0,	CPU_FPU,	0,	0
 fldcww,	fldnstcw_insn,	1,	SUF_W,	0x05,	0,	0,	0,	CPU_FPU,	0,	0
 fldenv,	onebytemem_insn,	1,	SUF_Z,	0x04,	0xD9,	0,	0,	CPU_FPU,	0,	0
-fldenvl,	onebytemem_insn,	1,	SUF_Z,	0x04,	0xD9,	0,	0,	CPU_FPU,	0,	0
-fldenvs,	onebytemem_insn,	1,	SUF_Z,	0x04,	0xD9,	0,	0,	CPU_FPU,	0,	0
+fldenvl,	onebytemem_insn,	1,	SUF_L,	0x04,	0xD9,	0,	0,	CPU_FPU,	0,	0
+fldenvs,	onebytemem_insn,	1,	SUF_S,	0x04,	0xD9,	0,	0,	CPU_FPU,	0,	0
+fldl,	fld_insn,	4,	SUF_L,	0,	0,	0,	0,	CPU_FPU,	0,	0
 fldl2e,	twobyte_insn,	1,	SUF_Z,	0xD9,	0xEA,	0,	0,	CPU_FPU,	0,	0
 fldl2t,	twobyte_insn,	1,	SUF_Z,	0xD9,	0xE9,	0,	0,	CPU_FPU,	0,	0
 fldlg2,	twobyte_insn,	1,	SUF_Z,	0xD9,	0xEC,	0,	0,	CPU_FPU,	0,	0
 fldln2,	twobyte_insn,	1,	SUF_Z,	0xD9,	0xED,	0,	0,	CPU_FPU,	0,	0
 fldpi,	twobyte_insn,	1,	SUF_Z,	0xD9,	0xEB,	0,	0,	CPU_FPU,	0,	0
+flds,	fld_insn,	4,	SUF_S,	0,	0,	0,	0,	CPU_FPU,	0,	0
 fldt,	fldstpt_insn,	1,	SUF_Z,	0x05,	0,	0,	0,	CPU_FPU,	0,	0
 fldz,	twobyte_insn,	1,	SUF_Z,	0xD9,	0xEE,	0,	0,	CPU_FPU,	0,	0
 fmul,	farith_insn,	7,	SUF_Z,	0xC8,	0xC8,	0x01,	0,	CPU_FPU,	0,	0
 fmull,	farith_insn,	7,	SUF_L,	0xC8,	0xC8,	0x01,	0,	CPU_FPU,	0,	0
-fmuls,	farith_insn,	7,	SUF_S,	0xC8,	0xC8,	0x01,	0,	CPU_FPU,	0,	0
 fmulp,	farithp_insn,	3,	SUF_Z,	0xC8,	0,	0,	0,	CPU_FPU,	0,	0
+fmuls,	farith_insn,	7,	SUF_S,	0xC8,	0xC8,	0x01,	0,	CPU_FPU,	0,	0
 fnclex,	twobyte_insn,	1,	SUF_Z,	0xDB,	0xE2,	0,	0,	CPU_FPU,	0,	0
 fninit,	twobyte_insn,	1,	SUF_Z,	0xDB,	0xE3,	0,	0,	CPU_FPU,	0,	0
 fnop,	twobyte_insn,	1,	SUF_Z,	0xD9,	0xD0,	0,	0,	CPU_FPU,	0,	0
 fnsave,	onebytemem_insn,	1,	SUF_Z,	0x06,	0xDD,	0,	0,	CPU_FPU,	0,	0
-fnsavel,	onebytemem_insn,	1,	SUF_Z,	0x06,	0xDD,	0,	0,	CPU_FPU,	0,	0
-fnsaves,	onebytemem_insn,	1,	SUF_Z,	0x06,	0xDD,	0,	0,	CPU_FPU,	0,	0
+fnsavel,	onebytemem_insn,	1,	SUF_L,	0x06,	0xDD,	0,	0,	CPU_FPU,	0,	0
+fnsaves,	onebytemem_insn,	1,	SUF_S,	0x06,	0xDD,	0,	0,	CPU_FPU,	0,	0
 fnstcw,	fldnstcw_insn,	1,	SUF_Z,	0x07,	0,	0,	0,	CPU_FPU,	0,	0
 fnstcww,	fldnstcw_insn,	1,	SUF_W,	0x07,	0,	0,	0,	CPU_FPU,	0,	0
 fnstenv,	onebytemem_insn,	1,	SUF_Z,	0x06,	0xD9,	0,	0,	CPU_FPU,	0,	0
-fnstenvl,	onebytemem_insn,	1,	SUF_Z,	0x06,	0xD9,	0,	0,	CPU_FPU,	0,	0
-fnstenvs,	onebytemem_insn,	1,	SUF_Z,	0x06,	0xD9,	0,	0,	CPU_FPU,	0,	0
+fnstenvl,	onebytemem_insn,	1,	SUF_L,	0x06,	0xD9,	0,	0,	CPU_FPU,	0,	0
+fnstenvs,	onebytemem_insn,	1,	SUF_S,	0x06,	0xD9,	0,	0,	CPU_FPU,	0,	0
 fnstsw,	fnstsw_insn,	2,	SUF_Z,	0,	0,	0,	0,	CPU_FPU,	0,	0
 fnstsww,	fnstsw_insn,	2,	SUF_W,	0,	0,	0,	0,	CPU_FPU,	0,	0
 fpatan,	twobyte_insn,	1,	SUF_Z,	0xD9,	0xF3,	0,	0,	CPU_FPU,	0,	0
@@ -476,38 +494,38 @@ fprem1,	twobyte_insn,	1,	SUF_Z,	0xD9,	0xF5,	0,	0,	CPU_286,	CPU_FPU,	0
 fptan,	twobyte_insn,	1,	SUF_Z,	0xD9,	0xF2,	0,	0,	CPU_FPU,	0,	0
 frndint,	twobyte_insn,	1,	SUF_Z,	0xD9,	0xFC,	0,	0,	CPU_FPU,	0,	0
 frstor,	onebytemem_insn,	1,	SUF_Z,	0x04,	0xDD,	0,	0,	CPU_FPU,	0,	0
-frstorl,	onebytemem_insn,	1,	SUF_Z,	0x04,	0xDD,	0,	0,	CPU_FPU,	0,	0
-frstors,	onebytemem_insn,	1,	SUF_Z,	0x04,	0xDD,	0,	0,	CPU_FPU,	0,	0
+frstorl,	onebytemem_insn,	1,	SUF_L,	0x04,	0xDD,	0,	0,	CPU_FPU,	0,	0
+frstors,	onebytemem_insn,	1,	SUF_S,	0x04,	0xDD,	0,	0,	CPU_FPU,	0,	0
 fsave,	twobytemem_insn,	1,	SUF_Z,	0x06,	0x9B,	0xDD,	0,	CPU_FPU,	0,	0
-fsavel,	twobytemem_insn,	1,	SUF_Z,	0x06,	0x9B,	0xDD,	0,	CPU_FPU,	0,	0
-fsaves,	twobytemem_insn,	1,	SUF_Z,	0x06,	0x9B,	0xDD,	0,	CPU_FPU,	0,	0
+fsavel,	twobytemem_insn,	1,	SUF_L,	0x06,	0x9B,	0xDD,	0,	CPU_FPU,	0,	0
+fsaves,	twobytemem_insn,	1,	SUF_S,	0x06,	0x9B,	0xDD,	0,	CPU_FPU,	0,	0
 fscale,	twobyte_insn,	1,	SUF_Z,	0xD9,	0xFD,	0,	0,	CPU_FPU,	0,	0
 fsetpm,	twobyte_insn,	1,	SUF_Z,	0xDB,	0xE4,	0,	0,	CPU_286,	CPU_FPU,	CPU_Obs
 fsin,	twobyte_insn,	1,	SUF_Z,	0xD9,	0xFE,	0,	0,	CPU_286,	CPU_FPU,	0
 fsincos,	twobyte_insn,	1,	SUF_Z,	0xD9,	0xFB,	0,	0,	CPU_286,	CPU_FPU,	0
 fsqrt,	twobyte_insn,	1,	SUF_Z,	0xD9,	0xFA,	0,	0,	CPU_FPU,	0,	0
 fst,	fst_insn,	3,	SUF_Z,	0,	0,	0,	0,	CPU_FPU,	0,	0
-fstl,	fst_insn,	3,	SUF_L,	0,	0,	0,	0,	CPU_FPU,	0,	0
-fsts,	fst_insn,	3,	SUF_S,	0,	0,	0,	0,	CPU_FPU,	0,	0
 fstcw,	fstcw_insn,	1,	SUF_Z,	0,	0,	0,	0,	CPU_FPU,	0,	0
 fstcww,	fstcw_insn,	1,	SUF_W,	0,	0,	0,	0,	CPU_FPU,	0,	0
 fstenv,	twobytemem_insn,	1,	SUF_Z,	0x06,	0x9B,	0xD9,	0,	CPU_FPU,	0,	0
-fstenvl,	twobytemem_insn,	1,	SUF_Z,	0x06,	0x9B,	0xD9,	0,	CPU_FPU,	0,	0
-fstenvs,	twobytemem_insn,	1,	SUF_Z,	0x06,	0x9B,	0xD9,	0,	CPU_FPU,	0,	0
+fstenvl,	twobytemem_insn,	1,	SUF_L,	0x06,	0x9B,	0xD9,	0,	CPU_FPU,	0,	0
+fstenvs,	twobytemem_insn,	1,	SUF_S,	0x06,	0x9B,	0xD9,	0,	CPU_FPU,	0,	0
+fstl,	fst_insn,	3,	SUF_L,	0,	0,	0,	0,	CPU_FPU,	0,	0
 fstp,	fstp_insn,	4,	SUF_Z,	0,	0,	0,	0,	CPU_FPU,	0,	0
 fstpl,	fstp_insn,	4,	SUF_L,	0,	0,	0,	0,	CPU_FPU,	0,	0
 fstps,	fstp_insn,	4,	SUF_S,	0,	0,	0,	0,	CPU_FPU,	0,	0
 fstpt,	fldstpt_insn,	1,	SUF_Z,	0x07,	0,	0,	0,	CPU_FPU,	0,	0
+fsts,	fst_insn,	3,	SUF_S,	0,	0,	0,	0,	CPU_FPU,	0,	0
 fstsw,	fstsw_insn,	2,	SUF_Z,	0,	0,	0,	0,	CPU_FPU,	0,	0
 fstsww,	fstsw_insn,	2,	SUF_W,	0,	0,	0,	0,	CPU_FPU,	0,	0
 fsub,	farith_insn,	7,	SUF_Z,	0xE8,	0xE0,	0x04,	0,	CPU_FPU,	0,	0
 fsubl,	farith_insn,	7,	SUF_L,	0xE8,	0xE0,	0x04,	0,	CPU_FPU,	0,	0
-fsubs,	farith_insn,	7,	SUF_S,	0xE8,	0xE0,	0x04,	0,	CPU_FPU,	0,	0
 fsubp,	farithp_insn,	3,	SUF_Z,	0xE0,	0,	0,	0,	CPU_FPU,	0,	0
 fsubr,	farith_insn,	7,	SUF_Z,	0xE0,	0xE8,	0x05,	0,	CPU_FPU,	0,	0
 fsubrl,	farith_insn,	7,	SUF_L,	0xE0,	0xE8,	0x05,	0,	CPU_FPU,	0,	0
-fsubrs,	farith_insn,	7,	SUF_S,	0xE0,	0xE8,	0x05,	0,	CPU_FPU,	0,	0
 fsubrp,	farithp_insn,	3,	SUF_Z,	0xE8,	0,	0,	0,	CPU_FPU,	0,	0
+fsubrs,	farith_insn,	7,	SUF_S,	0xE0,	0xE8,	0x05,	0,	CPU_FPU,	0,	0
+fsubs,	farith_insn,	7,	SUF_S,	0xE8,	0xE0,	0x04,	0,	CPU_FPU,	0,	0
 ftst,	twobyte_insn,	1,	SUF_Z,	0xD9,	0xE4,	0,	0,	CPU_FPU,	0,	0
 fucom,	fcom2_insn,	2,	SUF_Z,	0xDD,	0xE0,	0,	0,	CPU_286,	CPU_FPU,	0
 fucomi,	fcom2_insn,	2,	SUF_Z,	0xDB,	0xE8,	0,	0,	CPU_686,	CPU_FPU,	0
@@ -518,9 +536,9 @@ fwait,	onebyte_insn,	1,	SUF_Z,	0x9B,	0,	0,	0,	CPU_FPU,	0,	0
 fxam,	twobyte_insn,	1,	SUF_Z,	0xD9,	0xE5,	0,	0,	CPU_FPU,	0,	0
 fxch,	fxch_insn,	4,	SUF_Z,	0,	0,	0,	0,	CPU_FPU,	0,	0
 fxrstor,	twobytemem_insn,	1,	SUF_Z,	0x01,	0x0F,	0xAE,	0,	CPU_686,	CPU_FPU,	0
-fxrstorq,	twobytemem_insn,	1,	SUF_Z,	0x01,	0x0F,	0xAE,	0,	CPU_686,	CPU_FPU,	0
+fxrstorq,	twobytemem_insn,	1,	SUF_Q,	0x01,	0x0F,	0xAE,	0,	CPU_686,	CPU_FPU,	0
 fxsave,	twobytemem_insn,	1,	SUF_Z,	0x00,	0x0F,	0xAE,	0,	CPU_686,	CPU_FPU,	0
-fxsaveq,	twobytemem_insn,	1,	SUF_Z,	0x00,	0x0F,	0xAE,	0,	CPU_686,	CPU_FPU,	0
+fxsaveq,	twobytemem_insn,	1,	SUF_Q,	0x00,	0x0F,	0xAE,	0,	CPU_686,	CPU_FPU,	0
 fxtract,	twobyte_insn,	1,	SUF_Z,	0xD9,	0xF4,	0,	0,	CPU_FPU,	0,	0
 fyl2x,	twobyte_insn,	1,	SUF_Z,	0xD9,	0xF1,	0,	0,	CPU_FPU,	0,	0
 fyl2xp1,	twobyte_insn,	1,	SUF_Z,	0xD9,	0xF9,	0,	0,	CPU_FPU,	0,	0
@@ -545,13 +563,12 @@ imulq,	imul_insn,	19,	SUF_Q,	0,	0,	0,	ONLY_64,	0,	0,	0
 imulw,	imul_insn,	19,	SUF_W,	0,	0,	0,	0,	0,	0,	0
 in,	in_insn,	12,	SUF_Z,	0,	0,	0,	0,	0,	0,	0
 inb,	in_insn,	12,	SUF_B,	0,	0,	0,	0,	0,	0,	0
-inl,	in_insn,	12,	SUF_L,	0,	0,	0,	0,	CPU_386,	0,	0
-inw,	in_insn,	12,	SUF_W,	0,	0,	0,	0,	0,	0,	0
 inc,	incdec_insn,	6,	SUF_Z,	0x40,	0x00,	0,	0,	0,	0,	0
 incb,	incdec_insn,	6,	SUF_B,	0x40,	0x00,	0,	0,	0,	0,	0
 incl,	incdec_insn,	6,	SUF_L,	0x40,	0x00,	0,	0,	CPU_386,	0,	0
 incq,	incdec_insn,	6,	SUF_Q,	0x40,	0x00,	0,	ONLY_64,	0,	0,	0
 incw,	incdec_insn,	6,	SUF_W,	0x40,	0x00,	0,	0,	0,	0,	0
+inl,	in_insn,	12,	SUF_L,	0,	0,	0,	0,	CPU_386,	0,	0
 insb,	onebyte_insn,	1,	SUF_Z,	0x6C,	0x00,	0,	0,	0,	0,	0
 insertps,	insertps_insn,	4,	SUF_Z,	0,	0,	0,	0,	CPU_SSE41,	0,	0
 insertq,	insertq_insn,	2,	SUF_Z,	0,	0,	0,	0,	CPU_SSE4a,	0,	0
@@ -566,9 +583,11 @@ inveptl,	eptvpid_insn,	2,	SUF_L,	0x00,	0,	0,	NOT_64,	CPU_386,	CPU_EPTVPID,	0
 inveptq,	eptvpid_insn,	2,	SUF_Q,	0x00,	0,	0,	ONLY_64,	CPU_EPTVPID,	0,	0
 invlpg,	twobytemem_insn,	1,	SUF_Z,	0x07,	0x0F,	0x01,	0,	CPU_486,	CPU_Priv,	0
 invlpga,	invlpga_insn,	2,	SUF_Z,	0,	0,	0,	0,	CPU_SVM,	0,	0
+invpcid,	invpcid_insn,	2,	SUF_Z,	0,	0,	0,	0,	CPU_386,	CPU_INVPCID,	CPU_Priv
 invvpid,	eptvpid_insn,	2,	SUF_Z,	0x01,	0,	0,	0,	CPU_386,	CPU_EPTVPID,	0
 invvpidl,	eptvpid_insn,	2,	SUF_L,	0x01,	0,	0,	NOT_64,	CPU_386,	CPU_EPTVPID,	0
 invvpidq,	eptvpid_insn,	2,	SUF_Q,	0x01,	0,	0,	ONLY_64,	CPU_EPTVPID,	0,	0
+inw,	in_insn,	12,	SUF_W,	0,	0,	0,	0,	0,	0,	0
 iret,	onebyte_insn,	1,	SUF_Z,	0xCF,	0,	0,	0,	0,	0,	0
 iretl,	onebyte_insn,	1,	SUF_Z,	0xCF,	0x20,	0,	0,	CPU_386,	0,	0
 iretq,	onebyte_insn,	1,	SUF_Z,	0xCF,	0x40,	0,	ONLY_64,	0,	0,	0
@@ -611,10 +630,10 @@ jrcxz,	jcxz_insn,	2,	SUF_Z,	0x40,	0,	0,	ONLY_64,	0,	0,	0
 js,	jcc_insn,	9,	SUF_Z,	0x08,	0,	0,	0,	0,	0,	0
 jz,	jcc_insn,	9,	SUF_Z,	0x04,	0,	0,	0,	0,	0,	0
 lahf,	onebyte_insn,	1,	SUF_Z,	0x9F,	0,	0,	0,	0,	0,	0
-lar,	bsfr_insn,	3,	SUF_Z,	0x02,	0,	0,	0,	CPU_286,	CPU_Prot,	0
-larl,	bsfr_insn,	3,	SUF_L,	0x02,	0,	0,	0,	CPU_286,	CPU_Prot,	0
-larq,	bsfr_insn,	3,	SUF_Q,	0x02,	0,	0,	ONLY_64,	CPU_286,	CPU_Prot,	0
-larw,	bsfr_insn,	3,	SUF_W,	0x02,	0,	0,	0,	CPU_286,	CPU_Prot,	0
+lar,	larlsl_insn,	6,	SUF_Z,	0x02,	0,	0,	0,	CPU_286,	CPU_Prot,	0
+larl,	larlsl_insn,	6,	SUF_L,	0x02,	0,	0,	0,	CPU_286,	CPU_Prot,	0
+larq,	larlsl_insn,	6,	SUF_Q,	0x02,	0,	0,	ONLY_64,	CPU_286,	CPU_Prot,	0
+larw,	larlsl_insn,	6,	SUF_W,	0x02,	0,	0,	0,	CPU_286,	CPU_Prot,	0
 lcall,	ljmpcall_insn,	7,	SUF_Z,	0x03,	0x9A,	0,	0,	0,	0,	0
 lcalll,	ljmpcall_insn,	7,	SUF_L,	0x03,	0x9A,	0,	0,	CPU_386,	0,	0
 lcallq,	ljmpcall_insn,	7,	SUF_Q,	0x03,	0x9A,	0,	ONLY_64,	0,	0,	0
@@ -627,29 +646,31 @@ ldsw,	ldes_insn,	2,	SUF_W,	0xC5,	0,	0,	NOT_64,	0,	0,	0
 lea,	lea_insn,	3,	SUF_Z,	0,	0,	0,	0,	0,	0,	0
 leal,	lea_insn,	3,	SUF_L,	0,	0,	0,	0,	CPU_386,	0,	0
 leaq,	lea_insn,	3,	SUF_Q,	0,	0,	0,	ONLY_64,	0,	0,	0
-leaw,	lea_insn,	3,	SUF_W,	0,	0,	0,	0,	0,	0,	0
 leave,	onebyte_insn,	1,	SUF_Z,	0xC9,	0x00,	0x40,	0,	CPU_186,	0,	0
 leavel,	onebyte_insn,	1,	SUF_Z,	0xC9,	0x00,	0x40,	0,	CPU_186,	0,	0
 leaveq,	onebyte_insn,	1,	SUF_Z,	0xC9,	0x00,	0x40,	ONLY_64,	0,	0,	0
 leavew,	onebyte_insn,	1,	SUF_Z,	0xC9,	0x10,	0x00,	0,	CPU_186,	0,	0
+leaw,	lea_insn,	3,	SUF_W,	0,	0,	0,	0,	0,	0,	0
 les,	ldes_insn,	2,	SUF_Z,	0xC4,	0,	0,	NOT_64,	0,	0,	0
 lesl,	ldes_insn,	2,	SUF_L,	0xC4,	0,	0,	NOT_64,	CPU_386,	0,	0
 lesw,	ldes_insn,	2,	SUF_W,	0xC4,	0,	0,	NOT_64,	0,	0,	0
 lfence,	threebyte_insn,	1,	SUF_Z,	0x0F,	0xAE,	0xE8,	0,	CPU_P3,	0,	0
-lfs,	lfgss_insn,	2,	SUF_Z,	0xB4,	0,	0,	0,	CPU_386,	0,	0
-lfsl,	lfgss_insn,	2,	SUF_L,	0xB4,	0,	0,	0,	CPU_386,	0,	0
-lfsw,	lfgss_insn,	2,	SUF_W,	0xB4,	0,	0,	0,	CPU_386,	0,	0
+lfs,	lfgss_insn,	3,	SUF_Z,	0xB4,	0,	0,	0,	CPU_386,	0,	0
+lfsl,	lfgss_insn,	3,	SUF_L,	0xB4,	0,	0,	0,	CPU_386,	0,	0
+lfsq,	lfgss_insn,	3,	SUF_Q,	0xB4,	0,	0,	ONLY_64,	CPU_386,	0,	0
+lfsw,	lfgss_insn,	3,	SUF_W,	0xB4,	0,	0,	0,	CPU_386,	0,	0
 lgdt,	twobytemem_insn,	1,	SUF_Z,	0x02,	0x0F,	0x01,	0,	CPU_286,	CPU_Priv,	0
-lgdtl,	twobytemem_insn,	1,	SUF_Z,	0x02,	0x0F,	0x01,	0,	CPU_286,	CPU_Priv,	0
-lgdtq,	twobytemem_insn,	1,	SUF_Z,	0x02,	0x0F,	0x01,	0,	CPU_286,	CPU_Priv,	0
-lgdtw,	twobytemem_insn,	1,	SUF_Z,	0x02,	0x0F,	0x01,	0,	CPU_286,	CPU_Priv,	0
-lgs,	lfgss_insn,	2,	SUF_Z,	0xB5,	0,	0,	0,	CPU_386,	0,	0
-lgsl,	lfgss_insn,	2,	SUF_L,	0xB5,	0,	0,	0,	CPU_386,	0,	0
-lgsw,	lfgss_insn,	2,	SUF_W,	0xB5,	0,	0,	0,	CPU_386,	0,	0
+lgdtl,	twobytemem_insn,	1,	SUF_L,	0x02,	0x0F,	0x01,	0,	CPU_286,	CPU_Priv,	0
+lgdtq,	twobytemem_insn,	1,	SUF_Q,	0x02,	0x0F,	0x01,	0,	CPU_286,	CPU_Priv,	0
+lgdtw,	twobytemem_insn,	1,	SUF_W,	0x02,	0x0F,	0x01,	0,	CPU_286,	CPU_Priv,	0
+lgs,	lfgss_insn,	3,	SUF_Z,	0xB5,	0,	0,	0,	CPU_386,	0,	0
+lgsl,	lfgss_insn,	3,	SUF_L,	0xB5,	0,	0,	0,	CPU_386,	0,	0
+lgsq,	lfgss_insn,	3,	SUF_Q,	0xB5,	0,	0,	ONLY_64,	CPU_386,	0,	0
+lgsw,	lfgss_insn,	3,	SUF_W,	0xB5,	0,	0,	0,	CPU_386,	0,	0
 lidt,	twobytemem_insn,	1,	SUF_Z,	0x03,	0x0F,	0x01,	0,	CPU_286,	CPU_Priv,	0
-lidtl,	twobytemem_insn,	1,	SUF_Z,	0x03,	0x0F,	0x01,	0,	CPU_286,	CPU_Priv,	0
-lidtq,	twobytemem_insn,	1,	SUF_Z,	0x03,	0x0F,	0x01,	0,	CPU_286,	CPU_Priv,	0
-lidtw,	twobytemem_insn,	1,	SUF_Z,	0x03,	0x0F,	0x01,	0,	CPU_286,	CPU_Priv,	0
+lidtl,	twobytemem_insn,	1,	SUF_L,	0x03,	0x0F,	0x01,	0,	CPU_286,	CPU_Priv,	0
+lidtq,	twobytemem_insn,	1,	SUF_Q,	0x03,	0x0F,	0x01,	0,	CPU_286,	CPU_Priv,	0
+lidtw,	twobytemem_insn,	1,	SUF_W,	0x03,	0x0F,	0x01,	0,	CPU_286,	CPU_Priv,	0
 ljmp,	ljmpcall_insn,	7,	SUF_Z,	0x05,	0xEA,	0,	0,	0,	0,	0
 ljmpl,	ljmpcall_insn,	7,	SUF_L,	0x05,	0xEA,	0,	0,	CPU_386,	0,	0
 ljmpq,	ljmpcall_insn,	7,	SUF_Q,	0x05,	0xEA,	0,	ONLY_64,	0,	0,	0
@@ -686,22 +707,23 @@ loopzl,	loopl_insn,	4,	SUF_Z,	0x01,	0x20,	0,	0,	0,	0,	0
 loopzq,	loopq_insn,	4,	SUF_Z,	0x01,	0x40,	0,	ONLY_64,	0,	0,	0
 loopzw,	loopw_insn,	4,	SUF_Z,	0x01,	0x10,	0,	NOT_64,	0,	0,	0
 lret,	retnf_insn,	6,	SUF_Z,	0xCA,	0,	0,	0,	0,	0,	0
-lretl,	retnf_insn,	6,	SUF_Z,	0xCA,	0,	0,	0,	0,	0,	0
-lretq,	retnf_insn,	6,	SUF_Z,	0xCA,	0x40,	0,	ONLY_64,	0,	0,	0
-lretw,	retnf_insn,	6,	SUF_Z,	0xCA,	0x10,	0,	0,	0,	0,	0
-lsl,	bsfr_insn,	3,	SUF_Z,	0x03,	0,	0,	0,	CPU_286,	CPU_Prot,	0
-lsll,	bsfr_insn,	3,	SUF_L,	0x03,	0,	0,	0,	CPU_286,	CPU_Prot,	0
-lslq,	bsfr_insn,	3,	SUF_Q,	0x03,	0,	0,	ONLY_64,	CPU_286,	CPU_Prot,	0
-lslw,	bsfr_insn,	3,	SUF_W,	0x03,	0,	0,	0,	CPU_286,	CPU_Prot,	0
-lss,	lfgss_insn,	2,	SUF_Z,	0xB2,	0,	0,	0,	CPU_386,	0,	0
-lssl,	lfgss_insn,	2,	SUF_L,	0xB2,	0,	0,	0,	CPU_386,	0,	0
-lssw,	lfgss_insn,	2,	SUF_W,	0xB2,	0,	0,	0,	CPU_386,	0,	0
+lretl,	retnf_insn,	6,	SUF_L,	0xCA,	0,	0,	0,	0,	0,	0
+lretq,	retnf_insn,	6,	SUF_Q,	0xCA,	0x40,	0,	ONLY_64,	0,	0,	0
+lretw,	retnf_insn,	6,	SUF_W,	0xCA,	0x10,	0,	0,	0,	0,	0
+lsl,	larlsl_insn,	6,	SUF_Z,	0x03,	0,	0,	0,	CPU_286,	CPU_Prot,	0
+lsll,	larlsl_insn,	6,	SUF_L,	0x03,	0,	0,	0,	CPU_286,	CPU_Prot,	0
+lslq,	larlsl_insn,	6,	SUF_Q,	0x03,	0,	0,	ONLY_64,	CPU_286,	CPU_Prot,	0
+lslw,	larlsl_insn,	6,	SUF_W,	0x03,	0,	0,	0,	CPU_286,	CPU_Prot,	0
+lss,	lfgss_insn,	3,	SUF_Z,	0xB2,	0,	0,	0,	CPU_386,	0,	0
+lssl,	lfgss_insn,	3,	SUF_L,	0xB2,	0,	0,	0,	CPU_386,	0,	0
+lssq,	lfgss_insn,	3,	SUF_Q,	0xB2,	0,	0,	ONLY_64,	CPU_386,	0,	0
+lssw,	lfgss_insn,	3,	SUF_W,	0xB2,	0,	0,	0,	CPU_386,	0,	0
 ltr,	prot286_insn,	1,	SUF_Z,	0x03,	0x00,	0,	0,	CPU_286,	CPU_Priv,	CPU_Prot
 ltrw,	prot286_insn,	1,	SUF_W,	0x03,	0x00,	0,	0,	CPU_286,	CPU_Priv,	CPU_Prot
-lzcnt,	cnt_insn,	3,	SUF_Z,	0xBD,	0,	0,	0,	CPU_686,	CPU_AMD,	0
-lzcntl,	cnt_insn,	3,	SUF_L,	0xBD,	0,	0,	0,	CPU_686,	CPU_AMD,	0
-lzcntq,	cnt_insn,	3,	SUF_Q,	0xBD,	0,	0,	ONLY_64,	CPU_686,	CPU_AMD,	0
-lzcntw,	cnt_insn,	3,	SUF_W,	0xBD,	0,	0,	0,	CPU_686,	CPU_AMD,	0
+lzcnt,	cnt_insn,	3,	SUF_Z,	0xBD,	0,	0,	0,	CPU_LZCNT,	0,	0
+lzcntl,	cnt_insn,	3,	SUF_L,	0xBD,	0,	0,	0,	CPU_LZCNT,	0,	0
+lzcntq,	cnt_insn,	3,	SUF_Q,	0xBD,	0,	0,	ONLY_64,	CPU_LZCNT,	0,	0
+lzcntw,	cnt_insn,	3,	SUF_W,	0xBD,	0,	0,	0,	CPU_LZCNT,	0,	0
 maskmovdqu,	maskmovdqu_insn,	1,	SUF_Z,	0,	0,	0,	0,	CPU_SSE2,	0,	0
 maskmovq,	maskmovq_insn,	1,	SUF_Z,	0,	0,	0,	0,	CPU_MMX,	CPU_P3,	0
 maxpd,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0x5F,	0,	0,	CPU_SSE2,	0,	0
@@ -716,10 +738,6 @@ minss,	xmm_xmm32_insn,	4,	SUF_Z,	0xF3,	0x5D,	0,	0,	CPU_SSE,	0,	0
 monitor,	threebyte_insn,	1,	SUF_Z,	0x0F,	0x01,	0xC8,	0,	CPU_SSE3,	0,	0
 montmul,	padlock_insn,	1,	SUF_Z,	0xC0,	0xF3,	0xA6,	0,	CPU_PadLock,	0,	0
 mov,	mov_insn,	69,	SUF_Z,	0,	0,	0,	0,	0,	0,	0
-movb,	mov_insn,	69,	SUF_B,	0,	0,	0,	0,	0,	0,	0
-movl,	mov_insn,	69,	SUF_L,	0,	0,	0,	0,	CPU_386,	0,	0
-movq,	mov_insn,	69,	SUF_Q,	0,	0,	0,	0,	0,	0,	0
-movw,	mov_insn,	69,	SUF_W,	0,	0,	0,	0,	0,	0,	0
 movabs,	movabs_insn,	9,	SUF_Z,	0,	0,	0,	ONLY_64,	0,	0,	0
 movabsb,	movabs_insn,	9,	SUF_B,	0,	0,	0,	ONLY_64,	0,	0,	0
 movabsl,	movabs_insn,	9,	SUF_L,	0,	0,	0,	ONLY_64,	0,	0,	0
@@ -727,6 +745,7 @@ movabsq,	movabs_insn,	9,	SUF_Q,	0,	0,	0,	ONLY_64,	0,	0,	0
 movabsw,	movabs_insn,	9,	SUF_W,	0,	0,	0,	ONLY_64,	0,	0,	0
 movapd,	movau_insn,	6,	SUF_Z,	0x66,	0x28,	0x01,	0,	CPU_SSE2,	0,	0
 movaps,	movau_insn,	6,	SUF_Z,	0x00,	0x28,	0x01,	0,	CPU_SSE,	0,	0
+movb,	mov_insn,	69,	SUF_B,	0,	0,	0,	0,	0,	0,	0
 movbe,	movbe_insn,	6,	SUF_Z,	0,	0,	0,	0,	CPU_MOVBE,	0,	0
 movd,	movd_insn,	8,	SUF_Z,	0,	0,	0,	0,	CPU_386,	CPU_MMX,	0
 movddup,	xmm_xmm64_insn,	4,	SUF_Z,	0xF2,	0x12,	0,	0,	CPU_SSE3,	0,	0
@@ -736,6 +755,7 @@ movdqu,	movau_insn,	6,	SUF_Z,	0xF3,	0x6F,	0x10,	0,	CPU_SSE2,	0,	0
 movhlps,	movhllhps_insn,	2,	SUF_Z,	0x12,	0,	0,	0,	CPU_SSE,	0,	0
 movhpd,	movhlp_insn,	3,	SUF_Z,	0x66,	0x16,	0,	0,	CPU_SSE2,	0,	0
 movhps,	movhlp_insn,	3,	SUF_Z,	0x00,	0x16,	0,	0,	CPU_SSE,	0,	0
+movl,	mov_insn,	69,	SUF_L,	0,	0,	0,	0,	CPU_386,	0,	0
 movlhps,	movhllhps_insn,	2,	SUF_Z,	0x16,	0,	0,	0,	CPU_SSE,	0,	0
 movlpd,	movhlp_insn,	3,	SUF_Z,	0x66,	0x12,	0,	0,	CPU_SSE2,	0,	0
 movlps,	movhlp_insn,	3,	SUF_Z,	0x00,	0x12,	0,	0,	CPU_SSE,	0,	0
@@ -746,7 +766,7 @@ movmskps,	movmsk_insn,	4,	SUF_Z,	0,	0,	0,	0,	CPU_386,	CPU_SSE,	0
 movmskpsl,	movmsk_insn,	4,	SUF_L,	0,	0,	0,	0,	CPU_386,	CPU_SSE,	0
 movmskpsq,	movmsk_insn,	4,	SUF_Q,	0,	0,	0,	ONLY_64,	CPU_SSE,	0,	0
 movntdq,	movnt_insn,	2,	SUF_Z,	0x66,	0xE7,	0,	0,	CPU_SSE2,	0,	0
-movntdqa,	movntdqa_insn,	1,	SUF_Z,	0,	0,	0,	0,	CPU_SSE41,	0,	0
+movntdqa,	movntdqa_insn,	2,	SUF_Z,	0,	0,	0,	0,	CPU_SSE41,	0,	0
 movnti,	movnti_insn,	2,	SUF_Z,	0,	0,	0,	0,	CPU_P4,	0,	0
 movntil,	movnti_insn,	2,	SUF_L,	0,	0,	0,	0,	CPU_P4,	0,	0
 movntiq,	movnti_insn,	2,	SUF_Q,	0,	0,	0,	ONLY_64,	CPU_P4,	0,	0
@@ -755,31 +775,33 @@ movntps,	movnt_insn,	2,	SUF_Z,	0x00,	0x2B,	0,	0,	CPU_SSE,	0,	0
 movntq,	movntq_insn,	1,	SUF_Z,	0,	0,	0,	0,	CPU_SSE,	0,	0
 movntsd,	movntsd_insn,	1,	SUF_Z,	0,	0,	0,	0,	CPU_SSE4a,	0,	0
 movntss,	movntss_insn,	1,	SUF_Z,	0,	0,	0,	0,	CPU_SSE4a,	0,	0
+movq,	mov_insn,	69,	SUF_Q,	0,	0,	0,	0,	0,	0,	0
 movq2dq,	movq2dq_insn,	1,	SUF_Z,	0,	0,	0,	0,	CPU_SSE2,	0,	0
 movsb,	onebyte_insn,	1,	SUF_Z,	0xA4,	0x00,	0,	0,	0,	0,	0
-movsbl,	movszx_insn,	5,	SUF_Z,	0xBE,	0,	0,	0,	CPU_386,	0,	0
-movsbq,	movszx_insn,	5,	SUF_Z,	0xBE,	0,	0,	ONLY_64,	CPU_386,	0,	0
-movsbw,	movszx_insn,	5,	SUF_Z,	0xBE,	0,	0,	0,	CPU_386,	0,	0
+movsbl,	movszx_insn,	5,	SUF_B,	0xBE,	0,	0,	0,	CPU_386,	0,	0
+movsbq,	movszx_insn,	5,	SUF_B,	0xBE,	0,	0,	ONLY_64,	CPU_386,	0,	0
+movsbw,	movszx_insn,	5,	SUF_B,	0xBE,	0,	0,	0,	CPU_386,	0,	0
 movsd,	movsd_insn,	5,	SUF_Z,	0,	0,	0,	0,	CPU_386,	0,	0
 movshdup,	xmm_xmm128_insn,	2,	SUF_Z,	0xF3,	0x16,	0,	0,	CPU_SSE3,	0,	0
 movsl,	onebyte_insn,	1,	SUF_Z,	0xA5,	0x20,	0,	0,	CPU_386,	0,	0
 movsldup,	xmm_xmm128_insn,	2,	SUF_Z,	0xF3,	0x12,	0,	0,	CPU_SSE3,	0,	0
-movslq,	movsxd_insn,	1,	SUF_Z,	0,	0,	0,	ONLY_64,	0,	0,	0
+movslq,	movsxd_insn,	1,	SUF_L,	0,	0,	0,	ONLY_64,	0,	0,	0
 movsq,	onebyte_insn,	1,	SUF_Z,	0xA5,	0x40,	0,	ONLY_64,	0,	0,	0
 movss,	movss_insn,	4,	SUF_Z,	0,	0,	0,	0,	CPU_SSE,	0,	0
 movsw,	onebyte_insn,	1,	SUF_Z,	0xA5,	0x10,	0,	0,	0,	0,	0
-movswl,	movszx_insn,	5,	SUF_Z,	0xBE,	0,	0,	0,	CPU_386,	0,	0
-movswq,	movszx_insn,	5,	SUF_Z,	0xBE,	0,	0,	ONLY_64,	CPU_386,	0,	0
+movswl,	movszx_insn,	5,	SUF_W,	0xBE,	0,	0,	0,	CPU_386,	0,	0
+movswq,	movszx_insn,	5,	SUF_W,	0xBE,	0,	0,	ONLY_64,	CPU_386,	0,	0
 movsx,	movszx_insn,	5,	SUF_Z,	0xBE,	0,	0,	0,	CPU_386,	0,	0
 movsxb,	movszx_insn,	5,	SUF_B,	0xBE,	0,	0,	0,	CPU_386,	0,	0
 movsxw,	movszx_insn,	5,	SUF_W,	0xBE,	0,	0,	0,	CPU_386,	0,	0
 movupd,	movau_insn,	6,	SUF_Z,	0x66,	0x10,	0x01,	0,	CPU_SSE2,	0,	0
 movups,	movau_insn,	6,	SUF_Z,	0x00,	0x10,	0x01,	0,	CPU_SSE,	0,	0
-movzbl,	movszx_insn,	5,	SUF_Z,	0xB6,	0,	0,	0,	CPU_386,	0,	0
-movzbq,	movszx_insn,	5,	SUF_Z,	0xB6,	0,	0,	ONLY_64,	CPU_386,	0,	0
-movzbw,	movszx_insn,	5,	SUF_Z,	0xB6,	0,	0,	0,	CPU_386,	0,	0
-movzwl,	movszx_insn,	5,	SUF_Z,	0xB6,	0,	0,	0,	CPU_386,	0,	0
-movzwq,	movszx_insn,	5,	SUF_Z,	0xB6,	0,	0,	ONLY_64,	CPU_386,	0,	0
+movw,	mov_insn,	69,	SUF_W,	0,	0,	0,	0,	0,	0,	0
+movzbl,	movszx_insn,	5,	SUF_B,	0xB6,	0,	0,	0,	CPU_386,	0,	0
+movzbq,	movszx_insn,	5,	SUF_B,	0xB6,	0,	0,	ONLY_64,	CPU_386,	0,	0
+movzbw,	movszx_insn,	5,	SUF_B,	0xB6,	0,	0,	0,	CPU_386,	0,	0
+movzwl,	movszx_insn,	5,	SUF_W,	0xB6,	0,	0,	0,	CPU_386,	0,	0
+movzwq,	movszx_insn,	5,	SUF_W,	0xB6,	0,	0,	ONLY_64,	CPU_386,	0,	0
 movzx,	movszx_insn,	5,	SUF_Z,	0xB6,	0,	0,	0,	CPU_386,	0,	0
 movzxb,	movszx_insn,	5,	SUF_B,	0xB6,	0,	0,	0,	CPU_386,	0,	0
 movzxw,	movszx_insn,	5,	SUF_W,	0xB6,	0,	0,	0,	CPU_386,	0,	0
@@ -787,12 +809,15 @@ mpsadbw,	sse4imm_insn,	2,	SUF_Z,	0x42,	0,	0,	0,	CPU_SSE41,	0,	0
 mul,	f6_insn,	4,	SUF_Z,	0x04,	0,	0,	0,	0,	0,	0
 mulb,	f6_insn,	4,	SUF_B,	0x04,	0,	0,	0,	0,	0,	0
 mull,	f6_insn,	4,	SUF_L,	0x04,	0,	0,	0,	CPU_386,	0,	0
-mulq,	f6_insn,	4,	SUF_Q,	0x04,	0,	0,	ONLY_64,	0,	0,	0
-mulw,	f6_insn,	4,	SUF_W,	0x04,	0,	0,	0,	0,	0,	0
 mulpd,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0x59,	0,	0,	CPU_SSE2,	0,	0
 mulps,	xmm_xmm128_insn,	2,	SUF_Z,	0x00,	0x59,	0,	0,	CPU_SSE,	0,	0
+mulq,	f6_insn,	4,	SUF_Q,	0x04,	0,	0,	ONLY_64,	0,	0,	0
 mulsd,	xmm_xmm64_insn,	4,	SUF_Z,	0xF2,	0x59,	0,	0,	CPU_SSE2,	0,	0
 mulss,	xmm_xmm32_insn,	4,	SUF_Z,	0xF3,	0x59,	0,	0,	CPU_SSE,	0,	0
+mulw,	f6_insn,	4,	SUF_W,	0x04,	0,	0,	0,	0,	0,	0
+mulx,	vex_gpr_reg_nds_rm_0F_insn,	2,	SUF_Z,	0xF2,	0x38,	0xF6,	ONLY_AVX,	CPU_BMI2,	0,	0
+mulxl,	vex_gpr_reg_nds_rm_0F_insn,	2,	SUF_L,	0xF2,	0x38,	0xF6,	ONLY_AVX,	CPU_BMI2,	0,	0
+mulxq,	vex_gpr_reg_nds_rm_0F_insn,	2,	SUF_Q,	0xF2,	0x38,	0xF6,	ONLY_64|ONLY_AVX,	CPU_BMI2,	0,	0
 mwait,	threebyte_insn,	1,	SUF_Z,	0x0F,	0x01,	0xC9,	0,	CPU_SSE3,	0,	0
 neg,	f6_insn,	4,	SUF_Z,	0x03,	0,	0,	0,	0,	0,	0
 negb,	f6_insn,	4,	SUF_B,	0x03,	0,	0,	0,	0,	0,	0
@@ -808,20 +833,20 @@ notw,	f6_insn,	4,	SUF_W,	0x02,	0,	0,	0,	0,	0,	0
 or,	arith_insn,	22,	SUF_Z,	0x08,	0x01,	0,	0,	0,	0,	0
 orb,	arith_insn,	22,	SUF_B,	0x08,	0x01,	0,	0,	0,	0,	0
 orl,	arith_insn,	22,	SUF_L,	0x08,	0x01,	0,	0,	CPU_386,	0,	0
-orq,	arith_insn,	22,	SUF_Q,	0x08,	0x01,	0,	ONLY_64,	0,	0,	0
-orw,	arith_insn,	22,	SUF_W,	0x08,	0x01,	0,	0,	0,	0,	0
 orpd,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0x56,	0,	0,	CPU_SSE2,	0,	0
 orps,	xmm_xmm128_insn,	2,	SUF_Z,	0x00,	0x56,	0,	0,	CPU_SSE,	0,	0
+orq,	arith_insn,	22,	SUF_Q,	0x08,	0x01,	0,	ONLY_64,	0,	0,	0
+orw,	arith_insn,	22,	SUF_W,	0x08,	0x01,	0,	0,	0,	0,	0
 out,	out_insn,	12,	SUF_Z,	0,	0,	0,	0,	0,	0,	0
 outb,	out_insn,	12,	SUF_B,	0,	0,	0,	0,	0,	0,	0
 outl,	out_insn,	12,	SUF_L,	0,	0,	0,	0,	CPU_386,	0,	0
-outw,	out_insn,	12,	SUF_W,	0,	0,	0,	0,	0,	0,	0
 outsb,	onebyte_insn,	1,	SUF_Z,	0x6E,	0x00,	0,	0,	0,	0,	0
 outsl,	onebyte_insn,	1,	SUF_Z,	0x6F,	0x20,	0,	0,	CPU_386,	0,	0
 outsw,	onebyte_insn,	1,	SUF_Z,	0x6F,	0x10,	0,	0,	0,	0,	0
-pabsb,	ssse3_insn,	3,	SUF_Z,	0x1C,	0,	0,	0,	CPU_SSSE3,	0,	0
-pabsd,	ssse3_insn,	3,	SUF_Z,	0x1E,	0,	0,	0,	CPU_SSSE3,	0,	0
-pabsw,	ssse3_insn,	3,	SUF_Z,	0x1D,	0,	0,	0,	CPU_SSSE3,	0,	0
+outw,	out_insn,	12,	SUF_W,	0,	0,	0,	0,	0,	0,	0
+pabsb,	ssse3_insn,	5,	SUF_Z,	0x1C,	0,	0,	0,	CPU_SSSE3,	0,	0
+pabsd,	ssse3_insn,	5,	SUF_Z,	0x1E,	0,	0,	0,	CPU_SSSE3,	0,	0
+pabsw,	ssse3_insn,	5,	SUF_Z,	0x1D,	0,	0,	0,	CPU_SSSE3,	0,	0
 packssdw,	mmxsse2_insn,	2,	SUF_Z,	0x6B,	0,	0,	0,	CPU_MMX,	0,	0
 packsswb,	mmxsse2_insn,	2,	SUF_Z,	0x63,	0,	0,	0,	CPU_MMX,	0,	0
 packusdw,	sse4_insn,	2,	SUF_Z,	0x2B,	0,	0,	0,	CPU_SSE41,	0,	0
@@ -862,7 +887,13 @@ pcmpgtq,	sse4_insn,	2,	SUF_Z,	0x37,	0,	0,	0,	CPU_SSE41,	0,	0
 pcmpgtw,	mmxsse2_insn,	2,	SUF_Z,	0x65,	0,	0,	0,	CPU_MMX,	0,	0
 pcmpistri,	sse4pcmpstr_insn,	1,	SUF_Z,	0x63,	0,	0,	0,	CPU_SSE42,	0,	0
 pcmpistrm,	sse4pcmpstr_insn,	1,	SUF_Z,	0x62,	0,	0,	0,	CPU_SSE42,	0,	0
+pdep,	vex_gpr_reg_nds_rm_0F_insn,	2,	SUF_Z,	0xF2,	0x38,	0xF5,	ONLY_AVX,	CPU_BMI2,	0,	0
+pdepl,	vex_gpr_reg_nds_rm_0F_insn,	2,	SUF_L,	0xF2,	0x38,	0xF5,	ONLY_AVX,	CPU_BMI2,	0,	0
+pdepq,	vex_gpr_reg_nds_rm_0F_insn,	2,	SUF_Q,	0xF2,	0x38,	0xF5,	ONLY_64|ONLY_AVX,	CPU_BMI2,	0,	0
 pdistib,	cyrixmmx_insn,	1,	SUF_Z,	0x54,	0,	0,	0,	CPU_Cyrix,	CPU_MMX,	0
+pext,	vex_gpr_reg_nds_rm_0F_insn,	2,	SUF_Z,	0xF3,	0x38,	0xF5,	ONLY_AVX,	CPU_BMI2,	0,	0
+pextl,	vex_gpr_reg_nds_rm_0F_insn,	2,	SUF_L,	0xF3,	0x38,	0xF5,	ONLY_AVX,	CPU_BMI2,	0,	0
+pextq,	vex_gpr_reg_nds_rm_0F_insn,	2,	SUF_Q,	0xF3,	0x38,	0xF5,	ONLY_64|ONLY_AVX,	CPU_BMI2,	0,	0
 pextrb,	pextrb_insn,	3,	SUF_Z,	0,	0,	0,	0,	CPU_SSE41,	0,	0
 pextrd,	pextrd_insn,	1,	SUF_Z,	0,	0,	0,	0,	CPU_386,	CPU_SSE41,	0
 pextrq,	pextrq_insn,	1,	SUF_Z,	0,	0,	0,	ONLY_64,	CPU_SSE41,	0,	0
@@ -888,13 +919,13 @@ pfrsqit1,	now3d_insn,	1,	SUF_Z,	0xA7,	0,	0,	0,	CPU_3DNow,	0,	0
 pfrsqrt,	now3d_insn,	1,	SUF_Z,	0x97,	0,	0,	0,	CPU_3DNow,	0,	0
 pfsub,	now3d_insn,	1,	SUF_Z,	0x9A,	0,	0,	0,	CPU_3DNow,	0,	0
 pfsubr,	now3d_insn,	1,	SUF_Z,	0xAA,	0,	0,	0,	CPU_3DNow,	0,	0
-phaddd,	ssse3_insn,	3,	SUF_Z,	0x02,	0,	0,	0,	CPU_SSSE3,	0,	0
-phaddsw,	ssse3_insn,	3,	SUF_Z,	0x03,	0,	0,	0,	CPU_SSSE3,	0,	0
-phaddw,	ssse3_insn,	3,	SUF_Z,	0x01,	0,	0,	0,	CPU_SSSE3,	0,	0
+phaddd,	ssse3_insn,	5,	SUF_Z,	0x02,	0,	0,	0,	CPU_SSSE3,	0,	0
+phaddsw,	ssse3_insn,	5,	SUF_Z,	0x03,	0,	0,	0,	CPU_SSSE3,	0,	0
+phaddw,	ssse3_insn,	5,	SUF_Z,	0x01,	0,	0,	0,	CPU_SSSE3,	0,	0
 phminposuw,	sse4_insn,	2,	SUF_Z,	0x41,	0,	0,	0,	CPU_SSE41,	0,	0
-phsubd,	ssse3_insn,	3,	SUF_Z,	0x06,	0,	0,	0,	CPU_SSSE3,	0,	0
-phsubsw,	ssse3_insn,	3,	SUF_Z,	0x07,	0,	0,	0,	CPU_SSSE3,	0,	0
-phsubw,	ssse3_insn,	3,	SUF_Z,	0x05,	0,	0,	0,	CPU_SSSE3,	0,	0
+phsubd,	ssse3_insn,	5,	SUF_Z,	0x06,	0,	0,	0,	CPU_SSSE3,	0,	0
+phsubsw,	ssse3_insn,	5,	SUF_Z,	0x07,	0,	0,	0,	CPU_SSSE3,	0,	0
+phsubw,	ssse3_insn,	5,	SUF_Z,	0x05,	0,	0,	0,	CPU_SSSE3,	0,	0
 pi2fd,	now3d_insn,	1,	SUF_Z,	0x0D,	0,	0,	0,	CPU_3DNow,	0,	0
 pi2fw,	now3d_insn,	1,	SUF_Z,	0x0C,	0,	0,	0,	CPU_3DNow,	CPU_Athlon,	0
 pinsrb,	pinsrb_insn,	4,	SUF_Z,	0,	0,	0,	0,	CPU_SSE41,	0,	0
@@ -904,7 +935,7 @@ pinsrw,	pinsrw_insn,	9,	SUF_Z,	0,	0,	0,	0,	CPU_MMX,	CPU_P3,	0
 pinsrwl,	pinsrw_insn,	9,	SUF_L,	0,	0,	0,	0,	CPU_MMX,	CPU_P3,	0
 pinsrwq,	pinsrw_insn,	9,	SUF_Q,	0,	0,	0,	ONLY_64,	CPU_MMX,	CPU_P3,	0
 pmachriw,	pmachriw_insn,	1,	SUF_Z,	0,	0,	0,	0,	CPU_Cyrix,	CPU_MMX,	0
-pmaddubsw,	ssse3_insn,	3,	SUF_Z,	0x04,	0,	0,	0,	CPU_SSSE3,	0,	0
+pmaddubsw,	ssse3_insn,	5,	SUF_Z,	0x04,	0,	0,	0,	CPU_SSSE3,	0,	0
 pmaddwd,	mmxsse2_insn,	2,	SUF_Z,	0xF5,	0,	0,	0,	CPU_MMX,	0,	0
 pmagw,	cyrixmmx_insn,	1,	SUF_Z,	0x52,	0,	0,	0,	CPU_Cyrix,	CPU_MMX,	0
 pmaxsb,	sse4_insn,	2,	SUF_Z,	0x3C,	0,	0,	0,	CPU_SSE41,	0,	0
@@ -919,24 +950,24 @@ pminsw,	mmxsse2_insn,	2,	SUF_Z,	0xEA,	0,	0,	0,	CPU_MMX,	CPU_P3,	0
 pminub,	mmxsse2_insn,	2,	SUF_Z,	0xDA,	0,	0,	0,	CPU_MMX,	CPU_P3,	0
 pminud,	sse4_insn,	2,	SUF_Z,	0x3B,	0,	0,	0,	CPU_SSE41,	0,	0
 pminuw,	sse4_insn,	2,	SUF_Z,	0x3A,	0,	0,	0,	CPU_SSE41,	0,	0
-pmovmskb,	pmovmskb_insn,	4,	SUF_Z,	0,	0,	0,	0,	CPU_MMX,	CPU_P3,	0
-pmovmskbl,	pmovmskb_insn,	4,	SUF_L,	0,	0,	0,	0,	CPU_MMX,	CPU_P3,	0
-pmovmskbq,	pmovmskb_insn,	4,	SUF_Q,	0,	0,	0,	ONLY_64,	CPU_MMX,	CPU_P3,	0
-pmovsxbd,	sse4m32_insn,	2,	SUF_Z,	0x21,	0,	0,	0,	CPU_SSE41,	0,	0
-pmovsxbq,	sse4m16_insn,	2,	SUF_Z,	0x22,	0,	0,	0,	CPU_SSE41,	0,	0
-pmovsxbw,	sse4m64_insn,	2,	SUF_Z,	0x20,	0,	0,	0,	CPU_SSE41,	0,	0
-pmovsxdq,	sse4m64_insn,	2,	SUF_Z,	0x25,	0,	0,	0,	CPU_SSE41,	0,	0
-pmovsxwd,	sse4m64_insn,	2,	SUF_Z,	0x23,	0,	0,	0,	CPU_SSE41,	0,	0
-pmovsxwq,	sse4m32_insn,	2,	SUF_Z,	0x24,	0,	0,	0,	CPU_SSE41,	0,	0
-pmovzxbd,	sse4m32_insn,	2,	SUF_Z,	0x31,	0,	0,	0,	CPU_SSE41,	0,	0
-pmovzxbq,	sse4m16_insn,	2,	SUF_Z,	0x32,	0,	0,	0,	CPU_SSE41,	0,	0
-pmovzxbw,	sse4m64_insn,	2,	SUF_Z,	0x30,	0,	0,	0,	CPU_SSE41,	0,	0
-pmovzxdq,	sse4m64_insn,	2,	SUF_Z,	0x35,	0,	0,	0,	CPU_SSE41,	0,	0
-pmovzxwd,	sse4m64_insn,	2,	SUF_Z,	0x33,	0,	0,	0,	CPU_SSE41,	0,	0
-pmovzxwq,	sse4m32_insn,	2,	SUF_Z,	0x34,	0,	0,	0,	CPU_SSE41,	0,	0
+pmovmskb,	pmovmskb_insn,	6,	SUF_Z,	0,	0,	0,	0,	CPU_MMX,	CPU_P3,	0
+pmovmskbl,	pmovmskb_insn,	6,	SUF_L,	0,	0,	0,	0,	CPU_MMX,	CPU_P3,	0
+pmovmskbq,	pmovmskb_insn,	6,	SUF_Q,	0,	0,	0,	ONLY_64,	CPU_MMX,	CPU_P3,	0
+pmovsxbd,	sse4m32_insn,	4,	SUF_Z,	0x21,	0,	0,	0,	CPU_SSE41,	0,	0
+pmovsxbq,	sse4m16_insn,	4,	SUF_Z,	0x22,	0,	0,	0,	CPU_SSE41,	0,	0
+pmovsxbw,	sse4m64_insn,	4,	SUF_Z,	0x20,	0,	0,	0,	CPU_SSE41,	0,	0
+pmovsxdq,	sse4m64_insn,	4,	SUF_Z,	0x25,	0,	0,	0,	CPU_SSE41,	0,	0
+pmovsxwd,	sse4m64_insn,	4,	SUF_Z,	0x23,	0,	0,	0,	CPU_SSE41,	0,	0
+pmovsxwq,	sse4m32_insn,	4,	SUF_Z,	0x24,	0,	0,	0,	CPU_SSE41,	0,	0
+pmovzxbd,	sse4m32_insn,	4,	SUF_Z,	0x31,	0,	0,	0,	CPU_SSE41,	0,	0
+pmovzxbq,	sse4m16_insn,	4,	SUF_Z,	0x32,	0,	0,	0,	CPU_SSE41,	0,	0
+pmovzxbw,	sse4m64_insn,	4,	SUF_Z,	0x30,	0,	0,	0,	CPU_SSE41,	0,	0
+pmovzxdq,	sse4m64_insn,	4,	SUF_Z,	0x35,	0,	0,	0,	CPU_SSE41,	0,	0
+pmovzxwd,	sse4m64_insn,	4,	SUF_Z,	0x33,	0,	0,	0,	CPU_SSE41,	0,	0
+pmovzxwq,	sse4m32_insn,	4,	SUF_Z,	0x34,	0,	0,	0,	CPU_SSE41,	0,	0
 pmuldq,	sse4_insn,	2,	SUF_Z,	0x28,	0,	0,	0,	CPU_SSE41,	0,	0
 pmulhriw,	cyrixmmx_insn,	1,	SUF_Z,	0x5D,	0,	0,	0,	CPU_Cyrix,	CPU_MMX,	0
-pmulhrsw,	ssse3_insn,	3,	SUF_Z,	0x0B,	0,	0,	0,	CPU_SSSE3,	0,	0
+pmulhrsw,	ssse3_insn,	5,	SUF_Z,	0x0B,	0,	0,	0,	CPU_SSSE3,	0,	0
 pmulhrwa,	now3d_insn,	1,	SUF_Z,	0xB7,	0,	0,	0,	CPU_3DNow,	0,	0
 pmulhrwc,	cyrixmmx_insn,	1,	SUF_Z,	0x59,	0,	0,	0,	CPU_Cyrix,	CPU_MMX,	0
 pmulhuw,	mmxsse2_insn,	2,	SUF_Z,	0xE4,	0,	0,	0,	CPU_MMX,	CPU_P3,	0
@@ -948,10 +979,7 @@ pmvgezb,	cyrixmmx_insn,	1,	SUF_Z,	0x5C,	0,	0,	0,	CPU_Cyrix,	CPU_MMX,	0
 pmvlzb,	cyrixmmx_insn,	1,	SUF_Z,	0x5B,	0,	0,	0,	CPU_Cyrix,	CPU_MMX,	0
 pmvnzb,	cyrixmmx_insn,	1,	SUF_Z,	0x5A,	0,	0,	0,	CPU_Cyrix,	CPU_MMX,	0
 pmvzb,	cyrixmmx_insn,	1,	SUF_Z,	0x58,	0,	0,	0,	CPU_Cyrix,	CPU_MMX,	0
-pop,	pop_insn,	21,	SUF_Z,	0,	0,	0,	0,	0,	0,	0
-popl,	pop_insn,	21,	SUF_L,	0,	0,	0,	NOT_64,	CPU_386,	0,	0
-popq,	pop_insn,	21,	SUF_Q,	0,	0,	0,	ONLY_64,	0,	0,	0
-popw,	pop_insn,	21,	SUF_W,	0,	0,	0,	0,	0,	0,	0
+pop,	pop_insn,	23,	SUF_Z,	0,	0,	0,	0,	0,	0,	0
 popa,	onebyte_insn,	1,	SUF_Z,	0x61,	0x00,	0,	NOT_64,	CPU_186,	0,	0
 popal,	onebyte_insn,	1,	SUF_Z,	0x61,	0x20,	0,	NOT_64,	CPU_386,	0,	0
 popaw,	onebyte_insn,	1,	SUF_Z,	0x61,	0x10,	0,	NOT_64,	CPU_186,	0,	0
@@ -963,6 +991,9 @@ popf,	onebyte_insn,	1,	SUF_Z,	0x9D,	0x00,	0x40,	0,	0,	0,	0
 popfl,	onebyte_insn,	1,	SUF_Z,	0x9D,	0x20,	0,	NOT_64,	CPU_386,	0,	0
 popfq,	onebyte_insn,	1,	SUF_Z,	0x9D,	0x40,	0x40,	ONLY_64,	0,	0,	0
 popfw,	onebyte_insn,	1,	SUF_Z,	0x9D,	0x10,	0x40,	0,	0,	0,	0
+popl,	pop_insn,	23,	SUF_L,	0,	0,	0,	NOT_64,	CPU_386,	0,	0
+popq,	pop_insn,	23,	SUF_Q,	0,	0,	0,	ONLY_64,	0,	0,	0
+popw,	pop_insn,	23,	SUF_W,	0,	0,	0,	0,	0,	0,	0
 por,	mmxsse2_insn,	2,	SUF_Z,	0xEB,	0,	0,	0,	CPU_MMX,	0,	0
 prefetch,	twobytemem_insn,	1,	SUF_Z,	0x00,	0x0F,	0x0D,	0,	CPU_3DNow,	0,	0
 prefetchnta,	twobytemem_insn,	1,	SUF_Z,	0x00,	0x0F,	0x18,	0,	CPU_P3,	0,	0
@@ -971,22 +1002,22 @@ prefetcht1,	twobytemem_insn,	1,	SUF_Z,	0x02,	0x0F,	0x18,	0,	CPU_P3,	0,	0
 prefetcht2,	twobytemem_insn,	1,	SUF_Z,	0x03,	0x0F,	0x18,	0,	CPU_P3,	0,	0
 prefetchw,	twobytemem_insn,	1,	SUF_Z,	0x01,	0x0F,	0x0D,	0,	CPU_3DNow,	0,	0
 psadbw,	mmxsse2_insn,	2,	SUF_Z,	0xF6,	0,	0,	0,	CPU_MMX,	CPU_P3,	0
-pshufb,	ssse3_insn,	3,	SUF_Z,	0x00,	0,	0,	0,	CPU_SSSE3,	0,	0
+pshufb,	ssse3_insn,	5,	SUF_Z,	0x00,	0,	0,	0,	CPU_SSSE3,	0,	0
 pshufd,	xmm_xmm128_imm_insn,	1,	SUF_Z,	0x66,	0x70,	0,	0,	CPU_SSE2,	0,	0
 pshufhw,	xmm_xmm128_imm_insn,	1,	SUF_Z,	0xF3,	0x70,	0,	0,	CPU_SSE2,	0,	0
 pshuflw,	xmm_xmm128_imm_insn,	1,	SUF_Z,	0xF2,	0x70,	0,	0,	CPU_SSE2,	0,	0
 pshufw,	pshufw_insn,	1,	SUF_Z,	0,	0,	0,	0,	CPU_MMX,	CPU_P3,	0
-psignb,	ssse3_insn,	3,	SUF_Z,	0x08,	0,	0,	0,	CPU_SSSE3,	0,	0
-psignd,	ssse3_insn,	3,	SUF_Z,	0x0A,	0,	0,	0,	CPU_SSSE3,	0,	0
-psignw,	ssse3_insn,	3,	SUF_Z,	0x09,	0,	0,	0,	CPU_SSSE3,	0,	0
+psignb,	ssse3_insn,	5,	SUF_Z,	0x08,	0,	0,	0,	CPU_SSSE3,	0,	0
+psignd,	ssse3_insn,	5,	SUF_Z,	0x0A,	0,	0,	0,	CPU_SSSE3,	0,	0
+psignw,	ssse3_insn,	5,	SUF_Z,	0x09,	0,	0,	0,	CPU_SSSE3,	0,	0
 pslld,	pshift_insn,	4,	SUF_Z,	0xF2,	0x72,	0x06,	0,	CPU_MMX,	0,	0
-pslldq,	pslrldq_insn,	2,	SUF_Z,	0x07,	0,	0,	0,	CPU_SSE2,	0,	0
+pslldq,	pslrldq_insn,	4,	SUF_Z,	0x07,	0,	0,	0,	CPU_SSE2,	0,	0
 psllq,	pshift_insn,	4,	SUF_Z,	0xF3,	0x73,	0x06,	0,	CPU_MMX,	0,	0
 psllw,	pshift_insn,	4,	SUF_Z,	0xF1,	0x71,	0x06,	0,	CPU_MMX,	0,	0
 psrad,	pshift_insn,	4,	SUF_Z,	0xE2,	0x72,	0x04,	0,	CPU_MMX,	0,	0
 psraw,	pshift_insn,	4,	SUF_Z,	0xE1,	0x71,	0x04,	0,	CPU_MMX,	0,	0
 psrld,	pshift_insn,	4,	SUF_Z,	0xD2,	0x72,	0x02,	0,	CPU_MMX,	0,	0
-psrldq,	pslrldq_insn,	2,	SUF_Z,	0x03,	0,	0,	0,	CPU_SSE2,	0,	0
+psrldq,	pslrldq_insn,	4,	SUF_Z,	0x03,	0,	0,	0,	CPU_SSE2,	0,	0
 psrlq,	pshift_insn,	4,	SUF_Z,	0xD3,	0x73,	0x02,	0,	CPU_MMX,	0,	0
 psrlw,	pshift_insn,	4,	SUF_Z,	0xD1,	0x71,	0x02,	0,	CPU_MMX,	0,	0
 psubb,	mmxsse2_insn,	2,	SUF_Z,	0xF8,	0,	0,	0,	CPU_MMX,	0,	0
@@ -1008,10 +1039,7 @@ punpcklbw,	mmxsse2_insn,	2,	SUF_Z,	0x60,	0,	0,	0,	CPU_MMX,	0,	0
 punpckldq,	mmxsse2_insn,	2,	SUF_Z,	0x62,	0,	0,	0,	CPU_MMX,	0,	0
 punpcklqdq,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0x6C,	0,	0,	CPU_SSE2,	0,	0
 punpcklwd,	mmxsse2_insn,	2,	SUF_Z,	0x61,	0,	0,	0,	CPU_MMX,	0,	0
-push,	push_insn,	33,	SUF_Z,	0,	0,	0,	0,	0,	0,	0
-pushl,	push_insn,	33,	SUF_L,	0,	0,	0,	0,	CPU_386,	0,	0
-pushq,	push_insn,	33,	SUF_Q,	0,	0,	0,	ONLY_64,	0,	0,	0
-pushw,	push_insn,	33,	SUF_W,	0,	0,	0,	0,	0,	0,	0
+push,	push_insn,	35,	SUF_Z,	0,	0,	0,	0,	0,	0,	0
 pusha,	onebyte_insn,	1,	SUF_Z,	0x60,	0x00,	0,	NOT_64,	CPU_186,	0,	0
 pushal,	onebyte_insn,	1,	SUF_Z,	0x60,	0x20,	0,	NOT_64,	CPU_386,	0,	0
 pushaw,	onebyte_insn,	1,	SUF_Z,	0x60,	0x10,	0,	NOT_64,	CPU_186,	0,	0
@@ -1019,6 +1047,9 @@ pushf,	onebyte_insn,	1,	SUF_Z,	0x9C,	0x00,	0x40,	0,	0,	0,	0
 pushfl,	onebyte_insn,	1,	SUF_Z,	0x9C,	0x20,	0,	NOT_64,	CPU_386,	0,	0
 pushfq,	onebyte_insn,	1,	SUF_Z,	0x9C,	0x40,	0x40,	ONLY_64,	0,	0,	0
 pushfw,	onebyte_insn,	1,	SUF_Z,	0x9C,	0x10,	0x40,	0,	0,	0,	0
+pushl,	push_insn,	35,	SUF_L,	0,	0,	0,	0,	CPU_386,	0,	0
+pushq,	push_insn,	35,	SUF_Q,	0,	0,	0,	ONLY_64,	0,	0,	0
+pushw,	push_insn,	35,	SUF_W,	0,	0,	0,	0,	0,	0,	0
 pxor,	mmxsse2_insn,	2,	SUF_Z,	0xEF,	0,	0,	0,	CPU_MMX,	0,	0
 qword,	NULL,	X86_OPERSIZE>>8,	0x40,	0,	0,	0,	ONLY_64,	0,	0,	0
 rcl,	shift_insn,	16,	SUF_Z,	0x02,	0,	0,	0,	0,	0,	0
@@ -1076,6 +1107,9 @@ rorb,	shift_insn,	16,	SUF_B,	0x01,	0,	0,	0,	0,	0,	0
 rorl,	shift_insn,	16,	SUF_L,	0x01,	0,	0,	0,	CPU_386,	0,	0
 rorq,	shift_insn,	16,	SUF_Q,	0x01,	0,	0,	ONLY_64,	0,	0,	0
 rorw,	shift_insn,	16,	SUF_W,	0x01,	0,	0,	0,	0,	0,	0
+rorx,	vex_gpr_reg_rm_0F_imm8_insn,	2,	SUF_Z,	0xF2,	0x3A,	0xF0,	ONLY_AVX,	CPU_BMI2,	0,	0
+rorxl,	vex_gpr_reg_rm_0F_imm8_insn,	2,	SUF_L,	0xF2,	0x3A,	0xF0,	ONLY_64|ONLY_AVX,	CPU_BMI2,	0,	0
+rorxw,	vex_gpr_reg_rm_0F_imm8_insn,	2,	SUF_W,	0xF2,	0x3A,	0xF0,	ONLY_AVX,	CPU_BMI2,	0,	0
 roundpd,	sse4imm_insn,	2,	SUF_Z,	0x09,	0,	0,	0,	CPU_SSE41,	0,	0
 roundps,	sse4imm_insn,	2,	SUF_Z,	0x08,	0,	0,	0,	CPU_SSE41,	0,	0
 roundsd,	sse4m64imm_insn,	4,	SUF_Z,	0x0B,	0,	0,	0,	CPU_SSE41,	0,	0
@@ -1089,15 +1123,18 @@ rsts,	cyrixsmm_insn,	1,	SUF_Z,	0x7D,	0,	0,	0,	CPU_486,	CPU_Cyrix,	CPU_SMM
 sahf,	onebyte_insn,	1,	SUF_Z,	0x9E,	0,	0,	0,	0,	0,	0
 sal,	shift_insn,	16,	SUF_Z,	0x04,	0,	0,	0,	0,	0,	0
 salb,	shift_insn,	16,	SUF_B,	0x04,	0,	0,	0,	0,	0,	0
+salc,	onebyte_insn,	1,	SUF_Z,	0xD6,	0,	0,	NOT_64,	CPU_Undoc,	0,	0
 sall,	shift_insn,	16,	SUF_L,	0x04,	0,	0,	0,	CPU_386,	0,	0
 salq,	shift_insn,	16,	SUF_Q,	0x04,	0,	0,	ONLY_64,	0,	0,	0
 salw,	shift_insn,	16,	SUF_W,	0x04,	0,	0,	0,	0,	0,	0
-salc,	onebyte_insn,	1,	SUF_Z,	0xD6,	0,	0,	NOT_64,	CPU_Undoc,	0,	0
 sar,	shift_insn,	16,	SUF_Z,	0x07,	0,	0,	0,	0,	0,	0
 sarb,	shift_insn,	16,	SUF_B,	0x07,	0,	0,	0,	0,	0,	0
 sarl,	shift_insn,	16,	SUF_L,	0x07,	0,	0,	0,	CPU_386,	0,	0
 sarq,	shift_insn,	16,	SUF_Q,	0x07,	0,	0,	ONLY_64,	0,	0,	0
 sarw,	shift_insn,	16,	SUF_W,	0x07,	0,	0,	0,	0,	0,	0
+sarx,	vex_gpr_reg_rm_nds_0F_insn,	2,	SUF_Z,	0xF3,	0x38,	0xF7,	ONLY_AVX,	CPU_BMI2,	0,	0
+sarxl,	vex_gpr_reg_rm_nds_0F_insn,	2,	SUF_L,	0xF3,	0x38,	0xF7,	ONLY_AVX,	CPU_BMI2,	0,	0
+sarxq,	vex_gpr_reg_rm_nds_0F_insn,	2,	SUF_Q,	0xF3,	0x38,	0xF7,	ONLY_64|ONLY_AVX,	CPU_BMI2,	0,	0
 sbb,	arith_insn,	22,	SUF_Z,	0x18,	0x03,	0,	0,	0,	0,	0
 sbbb,	arith_insn,	22,	SUF_B,	0x18,	0x03,	0,	0,	0,	0,	0
 sbbl,	arith_insn,	22,	SUF_L,	0x18,	0x03,	0,	0,	CPU_386,	0,	0
@@ -1169,33 +1206,39 @@ setz,	setcc_insn,	1,	SUF_Z,	0x04,	0,	0,	0,	CPU_386,	0,	0
 setzb,	setcc_insn,	1,	SUF_B,	0x04,	0,	0,	0,	CPU_386,	0,	0
 sfence,	threebyte_insn,	1,	SUF_Z,	0x0F,	0xAE,	0xF8,	0,	CPU_P3,	0,	0
 sgdt,	twobytemem_insn,	1,	SUF_Z,	0x00,	0x0F,	0x01,	0,	CPU_286,	CPU_Priv,	0
-sgdtl,	twobytemem_insn,	1,	SUF_Z,	0x00,	0x0F,	0x01,	0,	CPU_286,	CPU_Priv,	0
-sgdtq,	twobytemem_insn,	1,	SUF_Z,	0x00,	0x0F,	0x01,	0,	CPU_286,	CPU_Priv,	0
-sgdtw,	twobytemem_insn,	1,	SUF_Z,	0x00,	0x0F,	0x01,	0,	CPU_286,	CPU_Priv,	0
+sgdtl,	twobytemem_insn,	1,	SUF_L,	0x00,	0x0F,	0x01,	0,	CPU_286,	CPU_Priv,	0
+sgdtq,	twobytemem_insn,	1,	SUF_Q,	0x00,	0x0F,	0x01,	0,	CPU_286,	CPU_Priv,	0
+sgdtw,	twobytemem_insn,	1,	SUF_W,	0x00,	0x0F,	0x01,	0,	CPU_286,	CPU_Priv,	0
 shl,	shift_insn,	16,	SUF_Z,	0x04,	0,	0,	0,	0,	0,	0
 shlb,	shift_insn,	16,	SUF_B,	0x04,	0,	0,	0,	0,	0,	0
-shll,	shift_insn,	16,	SUF_L,	0x04,	0,	0,	0,	CPU_386,	0,	0
-shlq,	shift_insn,	16,	SUF_Q,	0x04,	0,	0,	ONLY_64,	0,	0,	0
-shlw,	shift_insn,	16,	SUF_W,	0x04,	0,	0,	0,	0,	0,	0
 shld,	shlrd_insn,	9,	SUF_Z,	0xA4,	0,	0,	0,	CPU_386,	0,	0
 shldl,	shlrd_insn,	9,	SUF_L,	0xA4,	0,	0,	0,	CPU_386,	0,	0
 shldq,	shlrd_insn,	9,	SUF_Q,	0xA4,	0,	0,	ONLY_64,	CPU_386,	0,	0
 shldw,	shlrd_insn,	9,	SUF_W,	0xA4,	0,	0,	0,	CPU_386,	0,	0
+shll,	shift_insn,	16,	SUF_L,	0x04,	0,	0,	0,	CPU_386,	0,	0
+shlq,	shift_insn,	16,	SUF_Q,	0x04,	0,	0,	ONLY_64,	0,	0,	0
+shlw,	shift_insn,	16,	SUF_W,	0x04,	0,	0,	0,	0,	0,	0
+shlx,	vex_gpr_reg_rm_nds_0F_insn,	2,	SUF_Z,	0x66,	0x38,	0xF7,	ONLY_AVX,	CPU_BMI2,	0,	0
+shlxl,	vex_gpr_reg_rm_nds_0F_insn,	2,	SUF_L,	0x66,	0x38,	0xF7,	ONLY_AVX,	CPU_BMI2,	0,	0
+shlxq,	vex_gpr_reg_rm_nds_0F_insn,	2,	SUF_Q,	0x66,	0x38,	0xF7,	ONLY_64|ONLY_AVX,	CPU_BMI2,	0,	0
 shr,	shift_insn,	16,	SUF_Z,	0x05,	0,	0,	0,	0,	0,	0
 shrb,	shift_insn,	16,	SUF_B,	0x05,	0,	0,	0,	0,	0,	0
-shrl,	shift_insn,	16,	SUF_L,	0x05,	0,	0,	0,	CPU_386,	0,	0
-shrq,	shift_insn,	16,	SUF_Q,	0x05,	0,	0,	ONLY_64,	0,	0,	0
-shrw,	shift_insn,	16,	SUF_W,	0x05,	0,	0,	0,	0,	0,	0
 shrd,	shlrd_insn,	9,	SUF_Z,	0xAC,	0,	0,	0,	CPU_386,	0,	0
 shrdl,	shlrd_insn,	9,	SUF_L,	0xAC,	0,	0,	0,	CPU_386,	0,	0
 shrdq,	shlrd_insn,	9,	SUF_Q,	0xAC,	0,	0,	ONLY_64,	CPU_386,	0,	0
 shrdw,	shlrd_insn,	9,	SUF_W,	0xAC,	0,	0,	0,	CPU_386,	0,	0
+shrl,	shift_insn,	16,	SUF_L,	0x05,	0,	0,	0,	CPU_386,	0,	0
+shrq,	shift_insn,	16,	SUF_Q,	0x05,	0,	0,	ONLY_64,	0,	0,	0
+shrw,	shift_insn,	16,	SUF_W,	0x05,	0,	0,	0,	0,	0,	0
+shrx,	vex_gpr_reg_rm_nds_0F_insn,	2,	SUF_Z,	0xF2,	0x38,	0xF7,	ONLY_AVX,	CPU_BMI2,	0,	0
+shrxl,	vex_gpr_reg_rm_nds_0F_insn,	2,	SUF_L,	0xF2,	0x38,	0xF7,	ONLY_AVX,	CPU_BMI2,	0,	0
+shrxq,	vex_gpr_reg_rm_nds_0F_insn,	2,	SUF_Q,	0xF2,	0x38,	0xF7,	ONLY_64|ONLY_AVX,	CPU_BMI2,	0,	0
 shufpd,	xmm_xmm128_imm_insn,	1,	SUF_Z,	0x66,	0xC6,	0,	0,	CPU_SSE2,	0,	0
 shufps,	xmm_xmm128_imm_insn,	1,	SUF_Z,	0x00,	0xC6,	0,	0,	CPU_SSE,	0,	0
 sidt,	twobytemem_insn,	1,	SUF_Z,	0x01,	0x0F,	0x01,	0,	CPU_286,	CPU_Priv,	0
-sidtl,	twobytemem_insn,	1,	SUF_Z,	0x01,	0x0F,	0x01,	0,	CPU_286,	CPU_Priv,	0
-sidtq,	twobytemem_insn,	1,	SUF_Z,	0x01,	0x0F,	0x01,	0,	CPU_286,	CPU_Priv,	0
-sidtw,	twobytemem_insn,	1,	SUF_Z,	0x01,	0x0F,	0x01,	0,	CPU_286,	CPU_Priv,	0
+sidtl,	twobytemem_insn,	1,	SUF_L,	0x01,	0x0F,	0x01,	0,	CPU_286,	CPU_Priv,	0
+sidtq,	twobytemem_insn,	1,	SUF_Q,	0x01,	0x0F,	0x01,	0,	CPU_286,	CPU_Priv,	0
+sidtw,	twobytemem_insn,	1,	SUF_W,	0x01,	0x0F,	0x01,	0,	CPU_286,	CPU_Priv,	0
 skinit,	skinit_insn,	2,	SUF_Z,	0,	0,	0,	0,	CPU_SVM,	0,	0
 sldt,	sldtmsw_insn,	6,	SUF_Z,	0x00,	0x00,	0,	0,	CPU_286,	0,	0
 sldtl,	sldtmsw_insn,	6,	SUF_L,	0x00,	0x00,	0,	0,	CPU_386,	0,	0
@@ -1236,12 +1279,12 @@ strw,	str_insn,	4,	SUF_W,	0,	0,	0,	0,	CPU_286,	CPU_Prot,	0
 sub,	arith_insn,	22,	SUF_Z,	0x28,	0x05,	0,	0,	0,	0,	0
 subb,	arith_insn,	22,	SUF_B,	0x28,	0x05,	0,	0,	0,	0,	0
 subl,	arith_insn,	22,	SUF_L,	0x28,	0x05,	0,	0,	CPU_386,	0,	0
-subq,	arith_insn,	22,	SUF_Q,	0x28,	0x05,	0,	ONLY_64,	0,	0,	0
-subw,	arith_insn,	22,	SUF_W,	0x28,	0x05,	0,	0,	0,	0,	0
 subpd,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0x5C,	0,	0,	CPU_SSE2,	0,	0
 subps,	xmm_xmm128_insn,	2,	SUF_Z,	0x00,	0x5C,	0,	0,	CPU_SSE,	0,	0
+subq,	arith_insn,	22,	SUF_Q,	0x28,	0x05,	0,	ONLY_64,	0,	0,	0
 subsd,	xmm_xmm64_insn,	4,	SUF_Z,	0xF2,	0x5C,	0,	0,	CPU_SSE2,	0,	0
 subss,	xmm_xmm32_insn,	4,	SUF_Z,	0xF3,	0x5C,	0,	0,	CPU_SSE,	0,	0
+subw,	arith_insn,	22,	SUF_W,	0x28,	0x05,	0,	0,	0,	0,	0
 svdc,	svdc_insn,	1,	SUF_Z,	0,	0,	0,	0,	CPU_486,	CPU_Cyrix,	CPU_SMM
 svldt,	cyrixsmm_insn,	1,	SUF_Z,	0x7A,	0,	0,	0,	CPU_486,	CPU_Cyrix,	CPU_SMM
 svts,	cyrixsmm_insn,	1,	SUF_Z,	0x7C,	0,	0,	0,	CPU_486,	CPU_Cyrix,	CPU_SMM
@@ -1250,13 +1293,17 @@ syscall,	twobyte_insn,	1,	SUF_Z,	0x0F,	0x05,	0,	0,	CPU_686,	CPU_AMD,	0
 sysenter,	twobyte_insn,	1,	SUF_Z,	0x0F,	0x34,	0,	NOT_64,	CPU_686,	0,	0
 sysexit,	twobyte_insn,	1,	SUF_Z,	0x0F,	0x35,	0,	NOT_64,	CPU_686,	CPU_Priv,	0
 sysret,	twobyte_insn,	1,	SUF_Z,	0x0F,	0x07,	0,	0,	CPU_686,	CPU_AMD,	CPU_Priv
-sysretl,	twobyte_insn,	1,	SUF_Z,	0x0F,	0x07,	0,	0,	CPU_686,	CPU_AMD,	CPU_Priv
-sysretq,	twobyte_insn,	1,	SUF_Z,	0x0F,	0x07,	0,	0,	CPU_686,	CPU_AMD,	CPU_Priv
+sysretl,	twobyte_insn,	1,	SUF_L,	0x0F,	0x07,	0,	0,	CPU_686,	CPU_AMD,	CPU_Priv
+sysretq,	twobyte_insn,	1,	SUF_Q,	0x0F,	0x07,	0,	0,	CPU_686,	CPU_AMD,	CPU_Priv
 test,	test_insn,	20,	SUF_Z,	0,	0,	0,	0,	0,	0,	0
 testb,	test_insn,	20,	SUF_B,	0,	0,	0,	0,	0,	0,	0
 testl,	test_insn,	20,	SUF_L,	0,	0,	0,	0,	CPU_386,	0,	0
 testq,	test_insn,	20,	SUF_Q,	0,	0,	0,	ONLY_64,	0,	0,	0
 testw,	test_insn,	20,	SUF_W,	0,	0,	0,	0,	0,	0,	0
+tzcnt,	cnt_insn,	3,	SUF_Z,	0xBC,	0,	0,	0,	CPU_BMI1,	0,	0
+tzcntl,	cnt_insn,	3,	SUF_L,	0xBC,	0,	0,	0,	CPU_BMI1,	0,	0
+tzcntq,	cnt_insn,	3,	SUF_Q,	0xBC,	0,	0,	ONLY_64,	CPU_BMI1,	0,	0
+tzcntw,	cnt_insn,	3,	SUF_W,	0xBC,	0,	0,	0,	CPU_BMI1,	0,	0
 ucomisd,	xmm_xmm64_insn,	4,	SUF_Z,	0x66,	0x2E,	0,	0,	CPU_SSE2,	0,	0
 ucomiss,	xmm_xmm32_insn,	4,	SUF_Z,	0x00,	0x2E,	0,	0,	CPU_SSE,	0,	0
 ud1,	twobyte_insn,	1,	SUF_Z,	0x0F,	0xB9,	0,	0,	CPU_286,	CPU_Undoc,	0
@@ -1266,29 +1313,30 @@ unpckhpd,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0x15,	0,	0,	CPU_SSE2,	0,	0
 unpckhps,	xmm_xmm128_insn,	2,	SUF_Z,	0x00,	0x15,	0,	0,	CPU_SSE,	0,	0
 unpcklpd,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0x14,	0,	0,	CPU_SSE2,	0,	0
 unpcklps,	xmm_xmm128_insn,	2,	SUF_Z,	0x00,	0x14,	0,	0,	CPU_SSE,	0,	0
-vaddpd,	xmm_xmm128_256_insn,	3,	SUF_Z,	0x66,	0x58,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vaddps,	xmm_xmm128_256_insn,	3,	SUF_Z,	0x00,	0x58,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vaddpd,	xmm_xmm128_256_insn,	4,	SUF_Z,	0x66,	0x58,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vaddps,	xmm_xmm128_256_insn,	4,	SUF_Z,	0x00,	0x58,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
 vaddsd,	xmm_xmm64_insn,	4,	SUF_Z,	0xF2,	0x58,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
 vaddss,	xmm_xmm32_insn,	4,	SUF_Z,	0xF3,	0x58,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vaddsubpd,	xmm_xmm128_256_insn,	3,	SUF_Z,	0x66,	0xD0,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vaddsubps,	xmm_xmm128_256_insn,	3,	SUF_Z,	0xF2,	0xD0,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vaddsubpd,	xmm_xmm128_256_insn,	4,	SUF_Z,	0x66,	0xD0,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vaddsubps,	xmm_xmm128_256_insn,	4,	SUF_Z,	0xF2,	0xD0,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
 vaesdec,	aes_insn,	2,	SUF_Z,	0x38,	0xDE,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
 vaesdeclast,	aes_insn,	2,	SUF_Z,	0x38,	0xDF,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
 vaesenc,	aes_insn,	2,	SUF_Z,	0x38,	0xDC,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
 vaesenclast,	aes_insn,	2,	SUF_Z,	0x38,	0xDD,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
 vaesimc,	aesimc_insn,	1,	SUF_Z,	0x38,	0xDB,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
 vaeskeygenassist,	aes_imm_insn,	1,	SUF_Z,	0x3A,	0xDF,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vandnpd,	xmm_xmm128_256_insn,	3,	SUF_Z,	0x66,	0x55,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vandnps,	xmm_xmm128_256_insn,	3,	SUF_Z,	0x00,	0x55,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vandpd,	xmm_xmm128_256_insn,	3,	SUF_Z,	0x66,	0x54,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vandps,	xmm_xmm128_256_insn,	3,	SUF_Z,	0x00,	0x54,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vblendpd,	sse4imm_256_insn,	3,	SUF_Z,	0x0D,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vblendps,	sse4imm_256_insn,	3,	SUF_Z,	0x0C,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vandnpd,	xmm_xmm128_256_insn,	4,	SUF_Z,	0x66,	0x55,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vandnps,	xmm_xmm128_256_insn,	4,	SUF_Z,	0x00,	0x55,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vandpd,	xmm_xmm128_256_insn,	4,	SUF_Z,	0x66,	0x54,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vandps,	xmm_xmm128_256_insn,	4,	SUF_Z,	0x00,	0x54,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vblendpd,	sse4imm_256_insn,	4,	SUF_Z,	0x0D,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vblendps,	sse4imm_256_insn,	4,	SUF_Z,	0x0C,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
 vblendvpd,	avx_sse4xmm0_insn,	2,	SUF_Z,	0x4B,	0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
 vblendvps,	avx_sse4xmm0_insn,	2,	SUF_Z,	0x4A,	0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vbroadcastf128,	vbroadcastf128_insn,	1,	SUF_Z,	0,	0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vbroadcastsd,	vbroadcastsd_insn,	1,	SUF_Z,	0,	0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vbroadcastss,	vbroadcastss_insn,	2,	SUF_Z,	0,	0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vbroadcastf128,	vbroadcastif128_insn,	1,	SUF_Z,	0x1A,	0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vbroadcasti128,	vbroadcastif128_insn,	1,	SUF_Z,	0x5A,	0,	0,	ONLY_AVX,	CPU_AVX2,	0,	0
+vbroadcastsd,	vbroadcastsd_insn,	2,	SUF_Z,	0,	0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vbroadcastss,	vbroadcastss_insn,	4,	SUF_Z,	0,	0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
 vcmpeq_ospd,	ssecmp_128_insn,	3,	SUF_Z,	0x10,	0x66,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
 vcmpeq_osps,	ssecmp_128_insn,	3,	SUF_Z,	0x10,	0x00,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
 vcmpeq_ossd,	ssecmp_64_insn,	4,	SUF_Z,	0x10,	0xF2,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
@@ -1459,17 +1507,18 @@ vcvttsd2siq,	cvt_rx_xmm64_insn,	4,	SUF_Q,	0xF2,	0x2C,	0xC0,	ONLY_AVX,	CPU_AVX,	0
 vcvttss2si,	cvt_rx_xmm32_insn,	4,	SUF_Z,	0xF3,	0x2C,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
 vcvttss2sil,	cvt_rx_xmm32_insn,	4,	SUF_L,	0xF3,	0x2C,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
 vcvttss2siq,	cvt_rx_xmm32_insn,	4,	SUF_Q,	0xF3,	0x2C,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vdivpd,	xmm_xmm128_256_insn,	3,	SUF_Z,	0x66,	0x5E,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vdivps,	xmm_xmm128_256_insn,	3,	SUF_Z,	0x00,	0x5E,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vdivpd,	xmm_xmm128_256_insn,	4,	SUF_Z,	0x66,	0x5E,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vdivps,	xmm_xmm128_256_insn,	4,	SUF_Z,	0x00,	0x5E,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
 vdivsd,	xmm_xmm64_insn,	4,	SUF_Z,	0xF2,	0x5E,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
 vdivss,	xmm_xmm32_insn,	4,	SUF_Z,	0xF3,	0x5E,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
 vdppd,	sse4imm_insn,	2,	SUF_Z,	0x41,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vdpps,	sse4imm_256_insn,	3,	SUF_Z,	0x40,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vdpps,	sse4imm_256_insn,	4,	SUF_Z,	0x40,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
 verr,	prot286_insn,	1,	SUF_Z,	0x04,	0x00,	0,	0,	CPU_286,	CPU_Prot,	0
 verrw,	prot286_insn,	1,	SUF_W,	0x04,	0x00,	0,	0,	CPU_286,	CPU_Prot,	0
 verw,	prot286_insn,	1,	SUF_Z,	0x05,	0x00,	0,	0,	CPU_286,	CPU_Prot,	0
 verww,	prot286_insn,	1,	SUF_W,	0x05,	0x00,	0,	0,	CPU_286,	CPU_Prot,	0
-vextractf128,	vextractf128_insn,	1,	SUF_Z,	0,	0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vextractf128,	vextractif128_insn,	1,	SUF_Z,	0x19,	0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vextracti128,	vextractif128_insn,	1,	SUF_Z,	0x39,	0,	0,	ONLY_AVX,	CPU_AVX2,	0,	0
 vextractps,	extractps_insn,	2,	SUF_Z,	0xC0,	0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
 vfmadd132pd,	vfma_pd_insn,	2,	SUF_Z,	0x98,	0,	0,	ONLY_AVX,	CPU_FMA,	0,	0
 vfmadd132ps,	vfma_ps_insn,	2,	SUF_Z,	0x98,	0,	0,	ONLY_AVX,	CPU_FMA,	0,	0
@@ -1555,25 +1604,30 @@ vfrczpd,	vfrc_pdps_insn,	2,	SUF_Z,	0x01,	0,	0,	0,	CPU_XOP,	0,	0
 vfrczps,	vfrc_pdps_insn,	2,	SUF_Z,	0x00,	0,	0,	0,	CPU_XOP,	0,	0
 vfrczsd,	vfrczsd_insn,	2,	SUF_Z,	0,	0,	0,	0,	CPU_XOP,	0,	0
 vfrczss,	vfrczss_insn,	2,	SUF_Z,	0,	0,	0,	0,	CPU_XOP,	0,	0
-vhaddpd,	xmm_xmm128_256_insn,	3,	SUF_Z,	0x66,	0x7C,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vhaddps,	xmm_xmm128_256_insn,	3,	SUF_Z,	0xF2,	0x7C,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vhsubpd,	xmm_xmm128_256_insn,	3,	SUF_Z,	0x66,	0x7D,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vhsubps,	xmm_xmm128_256_insn,	3,	SUF_Z,	0xF2,	0x7D,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vinsertf128,	vinsertf128_insn,	1,	SUF_Z,	0,	0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vgatherdpd,	gather_64x_64x_insn,	2,	SUF_Z,	0x92,	0,	0,	ONLY_AVX,	CPU_AVX2,	0,	0
+vgatherdps,	gather_32x_32y_insn,	2,	SUF_Z,	0x92,	0,	0,	ONLY_AVX,	CPU_AVX2,	0,	0
+vgatherqpd,	gather_64x_64y_insn,	2,	SUF_Z,	0x93,	0,	0,	ONLY_AVX,	CPU_AVX2,	0,	0
+vgatherqps,	gather_32x_32y_128_insn,	2,	SUF_Z,	0x93,	0,	0,	ONLY_AVX,	CPU_AVX2,	0,	0
+vhaddpd,	xmm_xmm128_256_insn,	4,	SUF_Z,	0x66,	0x7C,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vhaddps,	xmm_xmm128_256_insn,	4,	SUF_Z,	0xF2,	0x7C,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vhsubpd,	xmm_xmm128_256_insn,	4,	SUF_Z,	0x66,	0x7D,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vhsubps,	xmm_xmm128_256_insn,	4,	SUF_Z,	0xF2,	0x7D,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vinsertf128,	vinsertif128_insn,	1,	SUF_Z,	0x18,	0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vinserti128,	vinsertif128_insn,	1,	SUF_Z,	0x38,	0,	0,	ONLY_AVX,	CPU_AVX2,	0,	0
 vinsertps,	insertps_insn,	4,	SUF_Z,	0xC0,	0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
 vlddqu,	lddqu_insn,	2,	SUF_Z,	0xC0,	0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
 vldmxcsr,	ldstmxcsr_insn,	1,	SUF_Z,	0x02,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
 vmaskmovdqu,	maskmovdqu_insn,	1,	SUF_Z,	0xC0,	0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
 vmaskmovpd,	vmaskmov_insn,	4,	SUF_Z,	0x2D,	0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
 vmaskmovps,	vmaskmov_insn,	4,	SUF_Z,	0x2C,	0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vmaxpd,	xmm_xmm128_256_insn,	3,	SUF_Z,	0x66,	0x5F,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vmaxps,	xmm_xmm128_256_insn,	3,	SUF_Z,	0x00,	0x5F,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vmaxpd,	xmm_xmm128_256_insn,	4,	SUF_Z,	0x66,	0x5F,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vmaxps,	xmm_xmm128_256_insn,	4,	SUF_Z,	0x00,	0x5F,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
 vmaxsd,	xmm_xmm64_insn,	4,	SUF_Z,	0xF2,	0x5F,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
 vmaxss,	xmm_xmm32_insn,	4,	SUF_Z,	0xF3,	0x5F,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
 vmcall,	threebyte_insn,	1,	SUF_Z,	0x0F,	0x01,	0xC1,	0,	CPU_P4,	0,	0
 vmclear,	vmxthreebytemem_insn,	1,	SUF_Z,	0x66,	0,	0,	0,	CPU_P4,	0,	0
-vminpd,	xmm_xmm128_256_insn,	3,	SUF_Z,	0x66,	0x5D,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vminps,	xmm_xmm128_256_insn,	3,	SUF_Z,	0x00,	0x5D,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vminpd,	xmm_xmm128_256_insn,	4,	SUF_Z,	0x66,	0x5D,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vminps,	xmm_xmm128_256_insn,	4,	SUF_Z,	0x00,	0x5D,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
 vminsd,	xmm_xmm64_insn,	4,	SUF_Z,	0xF2,	0x5D,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
 vminss,	xmm_xmm32_insn,	4,	SUF_Z,	0xF3,	0x5D,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
 vmlaunch,	threebyte_insn,	1,	SUF_Z,	0x0F,	0x01,	0xC2,	0,	CPU_P4,	0,	0
@@ -1598,7 +1652,7 @@ vmovmskps,	movmsk_insn,	4,	SUF_Z,	0x00,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
 vmovmskpsl,	movmsk_insn,	4,	SUF_L,	0x00,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
 vmovmskpsq,	movmsk_insn,	4,	SUF_Q,	0x00,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
 vmovntdq,	movnt_insn,	2,	SUF_Z,	0x66,	0xE7,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vmovntdqa,	movntdqa_insn,	1,	SUF_Z,	0xC0,	0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vmovntdqa,	movntdqa_insn,	2,	SUF_Z,	0xC0,	0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
 vmovntpd,	movnt_insn,	2,	SUF_Z,	0x66,	0x2B,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
 vmovntps,	movnt_insn,	2,	SUF_Z,	0x00,	0x2B,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
 vmovq,	vmovq_insn,	5,	SUF_Z,	0,	0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
@@ -1608,7 +1662,7 @@ vmovsldup,	avx_xmm_xmm128_insn,	2,	SUF_Z,	0xF3,	0x12,	0,	ONLY_AVX,	CPU_AVX,	0,	0
 vmovss,	movss_insn,	4,	SUF_Z,	0xC0,	0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
 vmovupd,	movau_insn,	6,	SUF_Z,	0x66,	0x10,	0x01,	ONLY_AVX,	CPU_AVX,	0,	0
 vmovups,	movau_insn,	6,	SUF_Z,	0x00,	0x10,	0x01,	ONLY_AVX,	CPU_AVX,	0,	0
-vmpsadbw,	sse4imm_insn,	2,	SUF_Z,	0x42,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vmpsadbw,	sse4imm_256avx2_insn,	4,	SUF_Z,	0x42,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
 vmptrld,	vmxtwobytemem_insn,	1,	SUF_Z,	0x06,	0,	0,	0,	CPU_P4,	0,	0
 vmptrst,	vmxtwobytemem_insn,	1,	SUF_Z,	0x07,	0,	0,	0,	CPU_P4,	0,	0
 vmread,	vmxmemrd_insn,	2,	SUF_Z,	0,	0,	0,	0,	CPU_P4,	0,	0
@@ -1617,8 +1671,8 @@ vmreadq,	vmxmemrd_insn,	2,	SUF_Q,	0,	0,	0,	ONLY_64,	CPU_P4,	0,	0
 vmresume,	threebyte_insn,	1,	SUF_Z,	0x0F,	0x01,	0xC3,	0,	CPU_P4,	0,	0
 vmrun,	svm_rax_insn,	2,	SUF_Z,	0xD8,	0,	0,	0,	CPU_SVM,	0,	0
 vmsave,	svm_rax_insn,	2,	SUF_Z,	0xDB,	0,	0,	0,	CPU_SVM,	0,	0
-vmulpd,	xmm_xmm128_256_insn,	3,	SUF_Z,	0x66,	0x59,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vmulps,	xmm_xmm128_256_insn,	3,	SUF_Z,	0x00,	0x59,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vmulpd,	xmm_xmm128_256_insn,	4,	SUF_Z,	0x66,	0x59,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vmulps,	xmm_xmm128_256_insn,	4,	SUF_Z,	0x00,	0x59,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
 vmulsd,	xmm_xmm64_insn,	4,	SUF_Z,	0xF2,	0x59,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
 vmulss,	xmm_xmm32_insn,	4,	SUF_Z,	0xF3,	0x59,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
 vmwrite,	vmxmemwr_insn,	2,	SUF_Z,	0,	0,	0,	0,	CPU_P4,	0,	0
@@ -1626,46 +1680,51 @@ vmwritel,	vmxmemwr_insn,	2,	SUF_L,	0,	0,	0,	NOT_64,	CPU_P4,	0,	0
 vmwriteq,	vmxmemwr_insn,	2,	SUF_Q,	0,	0,	0,	ONLY_64,	CPU_P4,	0,	0
 vmxoff,	threebyte_insn,	1,	SUF_Z,	0x0F,	0x01,	0xC4,	0,	CPU_P4,	0,	0
 vmxon,	vmxthreebytemem_insn,	1,	SUF_Z,	0xF3,	0,	0,	0,	CPU_P4,	0,	0
-vorpd,	xmm_xmm128_256_insn,	3,	SUF_Z,	0x66,	0x56,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vorps,	xmm_xmm128_256_insn,	3,	SUF_Z,	0x00,	0x56,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpabsb,	avx_ssse3_2op_insn,	1,	SUF_Z,	0x1C,	0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpabsd,	avx_ssse3_2op_insn,	1,	SUF_Z,	0x1E,	0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpabsw,	avx_ssse3_2op_insn,	1,	SUF_Z,	0x1D,	0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpackssdw,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0x6B,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpacksswb,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0x63,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpackusdw,	ssse3_insn,	3,	SUF_Z,	0x2B,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpackuswb,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0x67,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpaddb,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0xFC,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpaddd,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0xFE,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpaddq,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0xD4,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpaddsb,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0xEC,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpaddsw,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0xED,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpaddusb,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0xDC,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpaddusw,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0xDD,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpaddw,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0xFD,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpalignr,	sse4imm_insn,	2,	SUF_Z,	0x0F,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpand,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0xDB,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpandn,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0xDF,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpavgb,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0xE0,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpavgw,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0xE3,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpblendvb,	avx_sse4xmm0_128_insn,	1,	SUF_Z,	0x4C,	0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpblendw,	sse4imm_insn,	2,	SUF_Z,	0x0E,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vorpd,	xmm_xmm128_256_insn,	4,	SUF_Z,	0x66,	0x56,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vorps,	xmm_xmm128_256_insn,	4,	SUF_Z,	0x00,	0x56,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpabsb,	avx2_ssse3_2op_insn,	2,	SUF_Z,	0x1C,	0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpabsd,	avx2_ssse3_2op_insn,	2,	SUF_Z,	0x1E,	0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpabsw,	avx2_ssse3_2op_insn,	2,	SUF_Z,	0x1D,	0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpackssdw,	xmm_xmm128_256avx2_insn,	4,	SUF_Z,	0x66,	0x6B,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpacksswb,	xmm_xmm128_256avx2_insn,	4,	SUF_Z,	0x66,	0x63,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpackusdw,	ssse3_insn,	5,	SUF_Z,	0x2B,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpackuswb,	xmm_xmm128_256avx2_insn,	4,	SUF_Z,	0x66,	0x67,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpaddb,	xmm_xmm128_256avx2_insn,	4,	SUF_Z,	0x66,	0xFC,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpaddd,	xmm_xmm128_256avx2_insn,	4,	SUF_Z,	0x66,	0xFE,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpaddq,	xmm_xmm128_256avx2_insn,	4,	SUF_Z,	0x66,	0xD4,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpaddsb,	xmm_xmm128_256avx2_insn,	4,	SUF_Z,	0x66,	0xEC,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpaddsw,	xmm_xmm128_256avx2_insn,	4,	SUF_Z,	0x66,	0xED,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpaddusb,	xmm_xmm128_256avx2_insn,	4,	SUF_Z,	0x66,	0xDC,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpaddusw,	xmm_xmm128_256avx2_insn,	4,	SUF_Z,	0x66,	0xDD,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpaddw,	xmm_xmm128_256avx2_insn,	4,	SUF_Z,	0x66,	0xFD,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpalignr,	sse4imm_256avx2_insn,	4,	SUF_Z,	0x0F,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpand,	xmm_xmm128_256avx2_insn,	4,	SUF_Z,	0x66,	0xDB,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpandn,	xmm_xmm128_256avx2_insn,	4,	SUF_Z,	0x66,	0xDF,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpavgb,	xmm_xmm128_256avx2_insn,	4,	SUF_Z,	0x66,	0xE0,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpavgw,	xmm_xmm128_256avx2_insn,	4,	SUF_Z,	0x66,	0xE3,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpblendd,	vex_66_0F3A_imm8_avx2_insn,	2,	SUF_Z,	0x02,	0,	0,	ONLY_AVX,	CPU_AVX2,	0,	0
+vpblendvb,	avx2_sse4xmm0_insn,	2,	SUF_Z,	0x4C,	0,	0,	ONLY_AVX,	CPU_AVX2,	0,	0
+vpblendw,	sse4imm_256avx2_insn,	4,	SUF_Z,	0x0E,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpbroadcastb,	vpbroadcastb_avx2_insn,	4,	SUF_Z,	0,	0,	0,	ONLY_AVX,	CPU_AVX2,	0,	0
+vpbroadcastd,	vpbroadcastd_avx2_insn,	4,	SUF_Z,	0,	0,	0,	ONLY_AVX,	CPU_AVX2,	0,	0
+vpbroadcastq,	vpbroadcastq_avx2_insn,	4,	SUF_Z,	0,	0,	0,	ONLY_AVX,	CPU_AVX2,	0,	0
+vpbroadcastw,	vpbroadcastw_avx2_insn,	4,	SUF_Z,	0,	0,	0,	ONLY_AVX,	CPU_AVX2,	0,	0
 vpclmulhqhqdq,	pclmulqdq_fixed_insn,	2,	SUF_Z,	0x11,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
 vpclmulhqlqdq,	pclmulqdq_fixed_insn,	2,	SUF_Z,	0x01,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
 vpclmullqhqdq,	pclmulqdq_fixed_insn,	2,	SUF_Z,	0x10,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
 vpclmullqlqdq,	pclmulqdq_fixed_insn,	2,	SUF_Z,	0x00,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
 vpclmulqdq,	pclmulqdq_insn,	2,	SUF_Z,	0x3A,	0x44,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
 vpcmov,	vpcmov_insn,	4,	SUF_Z,	0,	0,	0,	0,	CPU_XOP,	0,	0
-vpcmpeqb,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0x74,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpcmpeqd,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0x76,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpcmpeqq,	ssse3_insn,	3,	SUF_Z,	0x29,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpcmpeqw,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0x75,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpcmpeqb,	xmm_xmm128_256avx2_insn,	4,	SUF_Z,	0x66,	0x74,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpcmpeqd,	xmm_xmm128_256avx2_insn,	4,	SUF_Z,	0x66,	0x76,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpcmpeqq,	ssse3_insn,	5,	SUF_Z,	0x29,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpcmpeqw,	xmm_xmm128_256avx2_insn,	4,	SUF_Z,	0x66,	0x75,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
 vpcmpestri,	sse4pcmpstr_insn,	1,	SUF_Z,	0x61,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
 vpcmpestrm,	sse4pcmpstr_insn,	1,	SUF_Z,	0x60,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpcmpgtb,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0x64,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpcmpgtd,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0x66,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpcmpgtq,	ssse3_insn,	3,	SUF_Z,	0x37,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpcmpgtw,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0x65,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpcmpgtb,	xmm_xmm128_256avx2_insn,	4,	SUF_Z,	0x66,	0x64,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpcmpgtd,	xmm_xmm128_256avx2_insn,	4,	SUF_Z,	0x66,	0x66,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpcmpgtq,	ssse3_insn,	5,	SUF_Z,	0x37,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpcmpgtw,	xmm_xmm128_256avx2_insn,	4,	SUF_Z,	0x66,	0x65,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
 vpcmpistri,	sse4pcmpstr_insn,	1,	SUF_Z,	0x63,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
 vpcmpistrm,	sse4pcmpstr_insn,	1,	SUF_Z,	0x62,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
 vpcomb,	vpcom_imm_insn,	1,	SUF_Z,	0xCC,	0,	0,	0,	CPU_XOP,	0,	0
@@ -1749,35 +1808,44 @@ vpcomuq,	vpcom_imm_insn,	1,	SUF_Z,	0xEF,	0,	0,	0,	CPU_XOP,	0,	0
 vpcomuw,	vpcom_imm_insn,	1,	SUF_Z,	0xED,	0,	0,	0,	CPU_XOP,	0,	0
 vpcomw,	vpcom_imm_insn,	1,	SUF_Z,	0xCD,	0,	0,	0,	CPU_XOP,	0,	0
 vperm2f128,	vperm2f128_insn,	1,	SUF_Z,	0,	0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vperm2i128,	vperm2i128_avx2_insn,	1,	SUF_Z,	0,	0,	0,	ONLY_AVX,	CPU_AVX2,	0,	0
+vpermd,	vperm_var_avx2_insn,	1,	SUF_Z,	0x36,	0,	0,	ONLY_AVX,	CPU_AVX2,	0,	0
 vpermilpd,	vpermil_insn,	4,	SUF_Z,	0x05,	0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
 vpermilps,	vpermil_insn,	4,	SUF_Z,	0x04,	0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpermpd,	vperm_imm_avx2_insn,	1,	SUF_Z,	0x01,	0,	0,	ONLY_AVX,	CPU_AVX2,	0,	0
+vpermps,	vperm_var_avx2_insn,	1,	SUF_Z,	0x16,	0,	0,	ONLY_AVX,	CPU_AVX2,	0,	0
+vpermq,	vperm_imm_avx2_insn,	1,	SUF_Z,	0x00,	0,	0,	ONLY_AVX,	CPU_AVX2,	0,	0
 vpextrb,	pextrb_insn,	3,	SUF_Z,	0xC0,	0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
 vpextrd,	pextrd_insn,	1,	SUF_Z,	0xC0,	0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
 vpextrq,	pextrq_insn,	1,	SUF_Z,	0xC0,	0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
 vpextrw,	pextrw_insn,	7,	SUF_Z,	0xC0,	0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
 vpextrwl,	pextrw_insn,	7,	SUF_L,	0xC0,	0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
 vpextrwq,	pextrw_insn,	7,	SUF_Q,	0xC0,	0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpgatherdd,	gather_32x_32y_insn,	2,	SUF_Z,	0x90,	0,	0,	ONLY_AVX,	CPU_AVX2,	0,	0
+vpgatherdq,	gather_64x_64x_insn,	2,	SUF_Z,	0x90,	0,	0,	ONLY_AVX,	CPU_AVX2,	0,	0
+vpgatherqd,	gather_32x_32y_128_insn,	2,	SUF_Z,	0x91,	0,	0,	ONLY_AVX,	CPU_AVX2,	0,	0
+vpgatherqq,	gather_64x_64y_insn,	2,	SUF_Z,	0x91,	0,	0,	ONLY_AVX,	CPU_AVX2,	0,	0
 vphaddbd,	vphaddsub_insn,	1,	SUF_Z,	0xC2,	0,	0,	0,	CPU_XOP,	0,	0
 vphaddbq,	vphaddsub_insn,	1,	SUF_Z,	0xC3,	0,	0,	0,	CPU_XOP,	0,	0
 vphaddbw,	vphaddsub_insn,	1,	SUF_Z,	0xC1,	0,	0,	0,	CPU_XOP,	0,	0
-vphaddd,	ssse3_insn,	3,	SUF_Z,	0x02,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vphaddd,	ssse3_insn,	5,	SUF_Z,	0x02,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
 vphadddq,	vphaddsub_insn,	1,	SUF_Z,	0xCB,	0,	0,	0,	CPU_XOP,	0,	0
-vphaddsw,	ssse3_insn,	3,	SUF_Z,	0x03,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vphaddsw,	ssse3_insn,	5,	SUF_Z,	0x03,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
 vphaddubd,	vphaddsub_insn,	1,	SUF_Z,	0xD2,	0,	0,	0,	CPU_XOP,	0,	0
 vphaddubq,	vphaddsub_insn,	1,	SUF_Z,	0xD3,	0,	0,	0,	CPU_XOP,	0,	0
 vphaddubw,	vphaddsub_insn,	1,	SUF_Z,	0xD1,	0,	0,	0,	CPU_XOP,	0,	0
 vphaddudq,	vphaddsub_insn,	1,	SUF_Z,	0xD8,	0,	0,	0,	CPU_XOP,	0,	0
 vphadduwd,	vphaddsub_insn,	1,	SUF_Z,	0xD6,	0,	0,	0,	CPU_XOP,	0,	0
 vphadduwq,	vphaddsub_insn,	1,	SUF_Z,	0xD7,	0,	0,	0,	CPU_XOP,	0,	0
-vphaddw,	ssse3_insn,	3,	SUF_Z,	0x01,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vphaddw,	ssse3_insn,	5,	SUF_Z,	0x01,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
 vphaddwd,	vphaddsub_insn,	1,	SUF_Z,	0xC6,	0,	0,	0,	CPU_XOP,	0,	0
 vphaddwq,	vphaddsub_insn,	1,	SUF_Z,	0xC7,	0,	0,	0,	CPU_XOP,	0,	0
 vphminposuw,	avx_ssse3_2op_insn,	1,	SUF_Z,	0x41,	0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
 vphsubbw,	vphaddsub_insn,	1,	SUF_Z,	0xE1,	0,	0,	0,	CPU_XOP,	0,	0
-vphsubd,	ssse3_insn,	3,	SUF_Z,	0x06,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vphsubd,	ssse3_insn,	5,	SUF_Z,	0x06,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
 vphsubdq,	vphaddsub_insn,	1,	SUF_Z,	0xE3,	0,	0,	0,	CPU_XOP,	0,	0
-vphsubsw,	ssse3_insn,	3,	SUF_Z,	0x07,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vphsubw,	ssse3_insn,	3,	SUF_Z,	0x05,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vphsubsw,	ssse3_insn,	5,	SUF_Z,	0x07,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vphsubw,	ssse3_insn,	5,	SUF_Z,	0x05,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
 vphsubwd,	vphaddsub_insn,	1,	SUF_Z,	0xE2,	0,	0,	0,	CPU_XOP,	0,	0
 vpinsrb,	pinsrb_insn,	4,	SUF_Z,	0xC0,	0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
 vpinsrd,	pinsrd_insn,	2,	SUF_Z,	0xC0,	0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
@@ -1797,49 +1865,51 @@ vpmacswd,	vpma_insn,	1,	SUF_Z,	0x96,	0,	0,	0,	CPU_XOP,	0,	0
 vpmacsww,	vpma_insn,	1,	SUF_Z,	0x95,	0,	0,	0,	CPU_XOP,	0,	0
 vpmadcsswd,	vpma_insn,	1,	SUF_Z,	0xA6,	0,	0,	0,	CPU_XOP,	0,	0
 vpmadcswd,	vpma_insn,	1,	SUF_Z,	0xB6,	0,	0,	0,	CPU_XOP,	0,	0
-vpmaddubsw,	ssse3_insn,	3,	SUF_Z,	0x04,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpmaddwd,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0xF5,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpmaxsb,	ssse3_insn,	3,	SUF_Z,	0x3C,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpmaxsd,	ssse3_insn,	3,	SUF_Z,	0x3D,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpmaxsw,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0xEE,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpmaxub,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0xDE,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpmaxud,	ssse3_insn,	3,	SUF_Z,	0x3F,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpmaxuw,	ssse3_insn,	3,	SUF_Z,	0x3E,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpminsb,	ssse3_insn,	3,	SUF_Z,	0x38,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpminsd,	ssse3_insn,	3,	SUF_Z,	0x39,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpminsw,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0xEA,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpminub,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0xDA,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpminud,	ssse3_insn,	3,	SUF_Z,	0x3B,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpminuw,	ssse3_insn,	3,	SUF_Z,	0x3A,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpmovmskb,	pmovmskb_insn,	4,	SUF_Z,	0xC0,	0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpmovmskbl,	pmovmskb_insn,	4,	SUF_L,	0xC0,	0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpmovmskbq,	pmovmskb_insn,	4,	SUF_Q,	0xC0,	0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpmovsxbd,	sse4m32_insn,	2,	SUF_Z,	0x21,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpmovsxbq,	sse4m16_insn,	2,	SUF_Z,	0x22,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpmovsxbw,	sse4m64_insn,	2,	SUF_Z,	0x20,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpmovsxdq,	sse4m64_insn,	2,	SUF_Z,	0x25,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpmovsxwd,	sse4m64_insn,	2,	SUF_Z,	0x23,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpmovsxwq,	sse4m32_insn,	2,	SUF_Z,	0x24,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpmovzxbd,	sse4m32_insn,	2,	SUF_Z,	0x31,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpmovzxbq,	sse4m16_insn,	2,	SUF_Z,	0x32,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpmovzxbw,	sse4m64_insn,	2,	SUF_Z,	0x30,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpmovzxdq,	sse4m64_insn,	2,	SUF_Z,	0x35,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpmovzxwd,	sse4m64_insn,	2,	SUF_Z,	0x33,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpmovzxwq,	sse4m32_insn,	2,	SUF_Z,	0x34,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpmuldq,	ssse3_insn,	3,	SUF_Z,	0x28,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpmulhrsw,	ssse3_insn,	3,	SUF_Z,	0x0B,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpmulhuw,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0xE4,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpmulhw,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0xE5,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpmulld,	ssse3_insn,	3,	SUF_Z,	0x40,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpmullw,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0xD5,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpmuludq,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0xF4,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpor,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0xEB,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpmaddubsw,	ssse3_insn,	5,	SUF_Z,	0x04,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpmaddwd,	xmm_xmm128_256avx2_insn,	4,	SUF_Z,	0x66,	0xF5,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpmaskmovd,	vmaskmov_insn,	4,	SUF_Z,	0x8C,	0,	0,	ONLY_AVX,	CPU_AVX2,	0,	0
+vpmaskmovq,	vmaskmov_vexw1_avx2_insn,	4,	SUF_Z,	0x8C,	0,	0,	ONLY_AVX,	CPU_AVX2,	0,	0
+vpmaxsb,	ssse3_insn,	5,	SUF_Z,	0x3C,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpmaxsd,	ssse3_insn,	5,	SUF_Z,	0x3D,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpmaxsw,	xmm_xmm128_256avx2_insn,	4,	SUF_Z,	0x66,	0xEE,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpmaxub,	xmm_xmm128_256avx2_insn,	4,	SUF_Z,	0x66,	0xDE,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpmaxud,	ssse3_insn,	5,	SUF_Z,	0x3F,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpmaxuw,	ssse3_insn,	5,	SUF_Z,	0x3E,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpminsb,	ssse3_insn,	5,	SUF_Z,	0x38,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpminsd,	ssse3_insn,	5,	SUF_Z,	0x39,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpminsw,	xmm_xmm128_256avx2_insn,	4,	SUF_Z,	0x66,	0xEA,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpminub,	xmm_xmm128_256avx2_insn,	4,	SUF_Z,	0x66,	0xDA,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpminud,	ssse3_insn,	5,	SUF_Z,	0x3B,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpminuw,	ssse3_insn,	5,	SUF_Z,	0x3A,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpmovmskb,	pmovmskb_insn,	6,	SUF_Z,	0xC0,	0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpmovmskbl,	pmovmskb_insn,	6,	SUF_L,	0xC0,	0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpmovmskbq,	pmovmskb_insn,	6,	SUF_Q,	0xC0,	0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpmovsxbd,	sse4m32_insn,	4,	SUF_Z,	0x21,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpmovsxbq,	sse4m16_insn,	4,	SUF_Z,	0x22,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpmovsxbw,	sse4m64_insn,	4,	SUF_Z,	0x20,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpmovsxdq,	sse4m64_insn,	4,	SUF_Z,	0x25,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpmovsxwd,	sse4m64_insn,	4,	SUF_Z,	0x23,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpmovsxwq,	sse4m32_insn,	4,	SUF_Z,	0x24,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpmovzxbd,	sse4m32_insn,	4,	SUF_Z,	0x31,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpmovzxbq,	sse4m16_insn,	4,	SUF_Z,	0x32,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpmovzxbw,	sse4m64_insn,	4,	SUF_Z,	0x30,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpmovzxdq,	sse4m64_insn,	4,	SUF_Z,	0x35,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpmovzxwd,	sse4m64_insn,	4,	SUF_Z,	0x33,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpmovzxwq,	sse4m32_insn,	4,	SUF_Z,	0x34,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpmuldq,	ssse3_insn,	5,	SUF_Z,	0x28,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpmulhrsw,	ssse3_insn,	5,	SUF_Z,	0x0B,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpmulhuw,	xmm_xmm128_256avx2_insn,	4,	SUF_Z,	0x66,	0xE4,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpmulhw,	xmm_xmm128_256avx2_insn,	4,	SUF_Z,	0x66,	0xE5,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpmulld,	ssse3_insn,	5,	SUF_Z,	0x40,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpmullw,	xmm_xmm128_256avx2_insn,	4,	SUF_Z,	0x66,	0xD5,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpmuludq,	xmm_xmm128_256avx2_insn,	4,	SUF_Z,	0x66,	0xF4,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpor,	xmm_xmm128_256avx2_insn,	4,	SUF_Z,	0x66,	0xEB,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
 vpperm,	vpperm_insn,	2,	SUF_Z,	0,	0,	0,	0,	CPU_XOP,	0,	0
 vprotb,	vprot_insn,	3,	SUF_Z,	0x00,	0,	0,	0,	CPU_XOP,	0,	0
 vprotd,	vprot_insn,	3,	SUF_Z,	0x02,	0,	0,	0,	CPU_XOP,	0,	0
 vprotq,	vprot_insn,	3,	SUF_Z,	0x03,	0,	0,	0,	CPU_XOP,	0,	0
 vprotw,	vprot_insn,	3,	SUF_Z,	0x01,	0,	0,	0,	CPU_XOP,	0,	0
-vpsadbw,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0xF6,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpsadbw,	xmm_xmm128_256avx2_insn,	4,	SUF_Z,	0x66,	0xF6,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
 vpshab,	amd_vpshift_insn,	2,	SUF_Z,	0x98,	0,	0,	0,	CPU_XOP,	0,	0
 vpshad,	amd_vpshift_insn,	2,	SUF_Z,	0x9A,	0,	0,	0,	CPU_XOP,	0,	0
 vpshaq,	amd_vpshift_insn,	2,	SUF_Z,	0x9B,	0,	0,	0,	CPU_XOP,	0,	0
@@ -1848,41 +1918,46 @@ vpshlb,	amd_vpshift_insn,	2,	SUF_Z,	0x94,	0,	0,	0,	CPU_XOP,	0,	0
 vpshld,	amd_vpshift_insn,	2,	SUF_Z,	0x96,	0,	0,	0,	CPU_XOP,	0,	0
 vpshlq,	amd_vpshift_insn,	2,	SUF_Z,	0x97,	0,	0,	0,	CPU_XOP,	0,	0
 vpshlw,	amd_vpshift_insn,	2,	SUF_Z,	0x95,	0,	0,	0,	CPU_XOP,	0,	0
-vpshufb,	ssse3_insn,	3,	SUF_Z,	0x00,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpshufd,	xmm_xmm128_imm_insn,	1,	SUF_Z,	0x66,	0x70,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpshufhw,	xmm_xmm128_imm_insn,	1,	SUF_Z,	0xF3,	0x70,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpshuflw,	xmm_xmm128_imm_insn,	1,	SUF_Z,	0xF2,	0x70,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpsignb,	ssse3_insn,	3,	SUF_Z,	0x08,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpsignd,	ssse3_insn,	3,	SUF_Z,	0x0A,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpsignw,	ssse3_insn,	3,	SUF_Z,	0x09,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpslld,	vpshift_insn,	4,	SUF_Z,	0xF2,	0x72,	0x06,	ONLY_AVX,	CPU_AVX,	0,	0
-vpslldq,	pslrldq_insn,	2,	SUF_Z,	0x07,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpsllq,	vpshift_insn,	4,	SUF_Z,	0xF3,	0x73,	0x06,	ONLY_AVX,	CPU_AVX,	0,	0
-vpsllw,	vpshift_insn,	4,	SUF_Z,	0xF1,	0x71,	0x06,	ONLY_AVX,	CPU_AVX,	0,	0
-vpsrad,	vpshift_insn,	4,	SUF_Z,	0xE2,	0x72,	0x04,	ONLY_AVX,	CPU_AVX,	0,	0
-vpsraw,	vpshift_insn,	4,	SUF_Z,	0xE1,	0x71,	0x04,	ONLY_AVX,	CPU_AVX,	0,	0
-vpsrld,	vpshift_insn,	4,	SUF_Z,	0xD2,	0x72,	0x02,	ONLY_AVX,	CPU_AVX,	0,	0
-vpsrldq,	pslrldq_insn,	2,	SUF_Z,	0x03,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpsrlq,	vpshift_insn,	4,	SUF_Z,	0xD3,	0x73,	0x02,	ONLY_AVX,	CPU_AVX,	0,	0
-vpsrlw,	vpshift_insn,	4,	SUF_Z,	0xD1,	0x71,	0x02,	ONLY_AVX,	CPU_AVX,	0,	0
-vpsubb,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0xF8,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpsubd,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0xFA,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpsubq,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0xFB,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpsubsb,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0xE8,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpsubsw,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0xE9,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpsubusb,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0xD8,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpsubusw,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0xD9,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpsubw,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0xF9,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpshufb,	ssse3_insn,	5,	SUF_Z,	0x00,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpshufd,	xmm_xmm128_imm_256avx2_insn,	2,	SUF_Z,	0x66,	0x70,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpshufhw,	xmm_xmm128_imm_256avx2_insn,	2,	SUF_Z,	0xF3,	0x70,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpshuflw,	xmm_xmm128_imm_256avx2_insn,	2,	SUF_Z,	0xF2,	0x70,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpsignb,	ssse3_insn,	5,	SUF_Z,	0x08,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpsignd,	ssse3_insn,	5,	SUF_Z,	0x0A,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpsignw,	ssse3_insn,	5,	SUF_Z,	0x09,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpslld,	vpshift_insn,	8,	SUF_Z,	0xF2,	0x72,	0x06,	ONLY_AVX,	CPU_AVX,	0,	0
+vpslldq,	pslrldq_insn,	4,	SUF_Z,	0x07,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpsllq,	vpshift_insn,	8,	SUF_Z,	0xF3,	0x73,	0x06,	ONLY_AVX,	CPU_AVX,	0,	0
+vpsllvd,	vpshiftv_vexw0_avx2_insn,	2,	SUF_Z,	0x47,	0,	0,	ONLY_AVX,	CPU_AVX2,	0,	0
+vpsllvq,	vpshiftv_vexw1_avx2_insn,	2,	SUF_Z,	0x47,	0,	0,	ONLY_AVX,	CPU_AVX2,	0,	0
+vpsllw,	vpshift_insn,	8,	SUF_Z,	0xF1,	0x71,	0x06,	ONLY_AVX,	CPU_AVX,	0,	0
+vpsrad,	vpshift_insn,	8,	SUF_Z,	0xE2,	0x72,	0x04,	ONLY_AVX,	CPU_AVX,	0,	0
+vpsravd,	vpshiftv_vexw0_avx2_insn,	2,	SUF_Z,	0x46,	0,	0,	ONLY_AVX,	CPU_AVX2,	0,	0
+vpsraw,	vpshift_insn,	8,	SUF_Z,	0xE1,	0x71,	0x04,	ONLY_AVX,	CPU_AVX,	0,	0
+vpsrld,	vpshift_insn,	8,	SUF_Z,	0xD2,	0x72,	0x02,	ONLY_AVX,	CPU_AVX,	0,	0
+vpsrldq,	pslrldq_insn,	4,	SUF_Z,	0x03,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpsrlq,	vpshift_insn,	8,	SUF_Z,	0xD3,	0x73,	0x02,	ONLY_AVX,	CPU_AVX,	0,	0
+vpsrlvd,	vpshiftv_vexw0_avx2_insn,	2,	SUF_Z,	0x45,	0,	0,	ONLY_AVX,	CPU_AVX2,	0,	0
+vpsrlvq,	vpshiftv_vexw1_avx2_insn,	2,	SUF_Z,	0x45,	0,	0,	ONLY_AVX,	CPU_AVX2,	0,	0
+vpsrlw,	vpshift_insn,	8,	SUF_Z,	0xD1,	0x71,	0x02,	ONLY_AVX,	CPU_AVX,	0,	0
+vpsubb,	xmm_xmm128_256avx2_insn,	4,	SUF_Z,	0x66,	0xF8,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpsubd,	xmm_xmm128_256avx2_insn,	4,	SUF_Z,	0x66,	0xFA,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpsubq,	xmm_xmm128_256avx2_insn,	4,	SUF_Z,	0x66,	0xFB,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpsubsb,	xmm_xmm128_256avx2_insn,	4,	SUF_Z,	0x66,	0xE8,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpsubsw,	xmm_xmm128_256avx2_insn,	4,	SUF_Z,	0x66,	0xE9,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpsubusb,	xmm_xmm128_256avx2_insn,	4,	SUF_Z,	0x66,	0xD8,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpsubusw,	xmm_xmm128_256avx2_insn,	4,	SUF_Z,	0x66,	0xD9,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpsubw,	xmm_xmm128_256avx2_insn,	4,	SUF_Z,	0x66,	0xF9,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
 vptest,	sse4_insn,	2,	SUF_Z,	0x17,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpunpckhbw,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0x68,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpunpckhdq,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0x6A,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpunpckhqdq,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0x6D,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpunpckhwd,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0x69,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpunpcklbw,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0x60,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpunpckldq,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0x62,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpunpcklqdq,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0x6C,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpunpcklwd,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0x61,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpxor,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0xEF,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpunpckhbw,	xmm_xmm128_256avx2_insn,	4,	SUF_Z,	0x66,	0x68,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpunpckhdq,	xmm_xmm128_256avx2_insn,	4,	SUF_Z,	0x66,	0x6A,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpunpckhqdq,	xmm_xmm128_256avx2_insn,	4,	SUF_Z,	0x66,	0x6D,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpunpckhwd,	xmm_xmm128_256avx2_insn,	4,	SUF_Z,	0x66,	0x69,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpunpcklbw,	xmm_xmm128_256avx2_insn,	4,	SUF_Z,	0x66,	0x60,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpunpckldq,	xmm_xmm128_256avx2_insn,	4,	SUF_Z,	0x66,	0x62,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpunpcklqdq,	xmm_xmm128_256avx2_insn,	4,	SUF_Z,	0x66,	0x6C,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpunpcklwd,	xmm_xmm128_256avx2_insn,	4,	SUF_Z,	0x66,	0x61,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpxor,	xmm_xmm128_256avx2_insn,	4,	SUF_Z,	0x66,	0xEF,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
 vrcpps,	avx_xmm_xmm128_insn,	2,	SUF_Z,	0x00,	0x53,	0,	ONLY_AVX,	CPU_AVX,	0,	0
 vrcpss,	xmm_xmm32_insn,	4,	SUF_Z,	0xF3,	0x53,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
 vroundpd,	avx_sse4imm_insn,	3,	SUF_Z,	0x09,	0,	0,	ONLY_AVX,	CPU_SSE41,	0,	0
@@ -1898,20 +1973,20 @@ vsqrtps,	avx_xmm_xmm128_insn,	2,	SUF_Z,	0x00,	0x51,	0,	ONLY_AVX,	CPU_AVX,	0,	0
 vsqrtsd,	xmm_xmm64_insn,	4,	SUF_Z,	0xF2,	0x51,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
 vsqrtss,	xmm_xmm32_insn,	4,	SUF_Z,	0xF3,	0x51,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
 vstmxcsr,	ldstmxcsr_insn,	1,	SUF_Z,	0x03,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vsubpd,	xmm_xmm128_256_insn,	3,	SUF_Z,	0x66,	0x5C,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vsubps,	xmm_xmm128_256_insn,	3,	SUF_Z,	0x00,	0x5C,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vsubpd,	xmm_xmm128_256_insn,	4,	SUF_Z,	0x66,	0x5C,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vsubps,	xmm_xmm128_256_insn,	4,	SUF_Z,	0x00,	0x5C,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
 vsubsd,	xmm_xmm64_insn,	4,	SUF_Z,	0xF2,	0x5C,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
 vsubss,	xmm_xmm32_insn,	4,	SUF_Z,	0xF3,	0x5C,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
 vtestpd,	sse4_insn,	2,	SUF_Z,	0x0F,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
 vtestps,	sse4_insn,	2,	SUF_Z,	0x0E,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
 vucomisd,	avx_xmm_xmm64_insn,	2,	SUF_Z,	0x66,	0x2E,	0,	ONLY_AVX,	CPU_AVX,	0,	0
 vucomiss,	avx_xmm_xmm32_insn,	2,	SUF_Z,	0x00,	0x2E,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vunpckhpd,	xmm_xmm128_256_insn,	3,	SUF_Z,	0x66,	0x15,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vunpckhps,	xmm_xmm128_256_insn,	3,	SUF_Z,	0x00,	0x15,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vunpcklpd,	xmm_xmm128_256_insn,	3,	SUF_Z,	0x66,	0x14,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vunpcklps,	xmm_xmm128_256_insn,	3,	SUF_Z,	0x00,	0x14,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vxorpd,	xmm_xmm128_256_insn,	3,	SUF_Z,	0x66,	0x57,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vxorps,	xmm_xmm128_256_insn,	3,	SUF_Z,	0x00,	0x57,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vunpckhpd,	xmm_xmm128_256_insn,	4,	SUF_Z,	0x66,	0x15,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vunpckhps,	xmm_xmm128_256_insn,	4,	SUF_Z,	0x00,	0x15,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vunpcklpd,	xmm_xmm128_256_insn,	4,	SUF_Z,	0x66,	0x14,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vunpcklps,	xmm_xmm128_256_insn,	4,	SUF_Z,	0x00,	0x14,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vxorpd,	xmm_xmm128_256_insn,	4,	SUF_Z,	0x66,	0x57,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vxorps,	xmm_xmm128_256_insn,	4,	SUF_Z,	0x00,	0x57,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
 vzeroall,	vzero_insn,	1,	SUF_Z,	0xC4,	0,	0,	0,	CPU_AVX,	0,	0
 vzeroupper,	vzero_insn,	1,	SUF_Z,	0xC0,	0,	0,	0,	CPU_AVX,	0,	0
 wait,	onebyte_insn,	1,	SUF_Z,	0x9B,	0,	0,	0,	0,	0,	0
@@ -1942,10 +2017,10 @@ xlatb,	onebyte_insn,	1,	SUF_Z,	0xD7,	0x00,	0,	0,	0,	0,	0
 xor,	arith_insn,	22,	SUF_Z,	0x30,	0x06,	0,	0,	0,	0,	0
 xorb,	arith_insn,	22,	SUF_B,	0x30,	0x06,	0,	0,	0,	0,	0
 xorl,	arith_insn,	22,	SUF_L,	0x30,	0x06,	0,	0,	CPU_386,	0,	0
-xorq,	arith_insn,	22,	SUF_Q,	0x30,	0x06,	0,	ONLY_64,	0,	0,	0
-xorw,	arith_insn,	22,	SUF_W,	0x30,	0x06,	0,	0,	0,	0,	0
 xorpd,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0x57,	0,	0,	CPU_SSE2,	0,	0
 xorps,	xmm_xmm128_insn,	2,	SUF_Z,	0x00,	0x57,	0,	0,	CPU_SSE,	0,	0
+xorq,	arith_insn,	22,	SUF_Q,	0x30,	0x06,	0,	ONLY_64,	0,	0,	0
+xorw,	arith_insn,	22,	SUF_W,	0x30,	0x06,	0,	0,	0,	0,	0
 xrstor,	twobytemem_insn,	1,	SUF_Z,	0x05,	0x0F,	0xAE,	0,	CPU_386,	CPU_XSAVE,	0
 xsave,	twobytemem_insn,	1,	SUF_Z,	0x04,	0x0F,	0xAE,	0,	CPU_386,	CPU_XSAVE,	0
 xsaveopt,	twobytemem_insn,	1,	SUF_Z,	0x06,	0x0F,	0xAE,	0,	CPU_XSAVEOPT,	0,	0
diff --git a/x86insn_nasm.gperf b/x86insn_nasm.gperf
index a7f152d..6fbcbf5 100644
--- a/x86insn_nasm.gperf
+++ b/x86insn_nasm.gperf
@@ -1,4 +1,4 @@
-/* Generated by gen_x86_insn.py r2346, do not edit */
+/* Generated by gen_x86_insn.py rHEAD, do not edit */
 %ignore-case
 %language=ANSI-C
 %compare-strncmp
@@ -31,15 +31,20 @@ aesenclast,	aes_insn,	2,	SUF_Z,	0x38,	0xDD,	0,	0,	CPU_AVX,	0,	0
 aesimc,	aesimc_insn,	1,	SUF_Z,	0x38,	0xDB,	0,	0,	CPU_AES,	0,	0
 aeskeygenassist,	aes_imm_insn,	1,	SUF_Z,	0x3A,	0xDF,	0,	0,	CPU_AES,	0,	0
 and,	arith_insn,	22,	SUF_Z,	0x20,	0x04,	0,	0,	0,	0,	0
+andn,	vex_gpr_reg_nds_rm_0F_insn,	2,	SUF_Z,	0x00,	0x38,	0xF2,	ONLY_AVX,	CPU_BMI1,	0,	0
 andnpd,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0x55,	0,	0,	CPU_SSE2,	0,	0
 andnps,	xmm_xmm128_insn,	2,	SUF_Z,	0x00,	0x55,	0,	0,	CPU_SSE,	0,	0
 andpd,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0x54,	0,	0,	CPU_SSE2,	0,	0
 andps,	xmm_xmm128_insn,	2,	SUF_Z,	0x00,	0x54,	0,	0,	CPU_SSE,	0,	0
 arpl,	arpl_insn,	1,	SUF_Z,	0,	0,	0,	NOT_64,	CPU_286,	CPU_Prot,	0
+bextr,	vex_gpr_reg_rm_nds_0F_insn,	2,	SUF_Z,	0x00,	0x38,	0xF7,	ONLY_AVX,	CPU_BMI1,	0,	0
 blendpd,	sse4imm_insn,	2,	SUF_Z,	0x0D,	0,	0,	0,	CPU_SSE41,	0,	0
 blendps,	sse4imm_insn,	2,	SUF_Z,	0x0C,	0,	0,	0,	CPU_SSE41,	0,	0
 blendvpd,	sse4xmm0_insn,	2,	SUF_Z,	0x15,	0,	0,	0,	CPU_SSE41,	0,	0
 blendvps,	sse4xmm0_insn,	2,	SUF_Z,	0x14,	0,	0,	0,	CPU_SSE41,	0,	0
+blsi,	vex_gpr_ndd_rm_0F38_regext_insn,	2,	SUF_Z,	0x00,	0xF3,	0x03,	ONLY_AVX,	CPU_BMI1,	0,	0
+blsmsk,	vex_gpr_ndd_rm_0F38_regext_insn,	2,	SUF_Z,	0x00,	0xF3,	0x02,	ONLY_AVX,	CPU_BMI1,	0,	0
+blsr,	vex_gpr_ndd_rm_0F38_regext_insn,	2,	SUF_Z,	0x00,	0xF3,	0x01,	ONLY_AVX,	CPU_BMI1,	0,	0
 bound,	bound_insn,	2,	SUF_Z,	0,	0,	0,	NOT_64,	CPU_186,	0,	0
 bsf,	bsfr_insn,	3,	SUF_Z,	0xBC,	0,	0,	0,	CPU_386,	0,	0
 bsr,	bsfr_insn,	3,	SUF_Z,	0xBD,	0,	0,	0,	CPU_386,	0,	0
@@ -48,6 +53,7 @@ bt,	bittest_insn,	6,	SUF_Z,	0xA3,	0x04,	0,	0,	CPU_386,	0,	0
 btc,	bittest_insn,	6,	SUF_Z,	0xBB,	0x07,	0,	0,	CPU_386,	0,	0
 btr,	bittest_insn,	6,	SUF_Z,	0xB3,	0x06,	0,	0,	CPU_386,	0,	0
 bts,	bittest_insn,	6,	SUF_Z,	0xAB,	0x05,	0,	0,	CPU_386,	0,	0
+bzhi,	vex_gpr_reg_rm_nds_0F_insn,	2,	SUF_Z,	0x00,	0x38,	0xF5,	ONLY_AVX,	CPU_BMI2,	0,	0
 call,	call_insn,	30,	SUF_Z,	0,	0,	0,	0,	0,	0,	0
 cbw,	onebyte_insn,	1,	SUF_Z,	0x98,	0x10,	0,	0,	0,	0,	0
 cdq,	onebyte_insn,	1,	SUF_Z,	0x99,	0x20,	0,	0,	CPU_386,	0,	0
@@ -300,6 +306,7 @@ invd,	twobyte_insn,	1,	SUF_Z,	0x0F,	0x08,	0,	0,	CPU_486,	CPU_Priv,	0
 invept,	eptvpid_insn,	2,	SUF_Z,	0x00,	0,	0,	0,	CPU_386,	CPU_EPTVPID,	0
 invlpg,	twobytemem_insn,	1,	SUF_Z,	0x07,	0x0F,	0x01,	0,	CPU_486,	CPU_Priv,	0
 invlpga,	invlpga_insn,	2,	SUF_Z,	0,	0,	0,	0,	CPU_SVM,	0,	0
+invpcid,	invpcid_insn,	2,	SUF_Z,	0,	0,	0,	0,	CPU_386,	CPU_INVPCID,	CPU_Priv
 invvpid,	eptvpid_insn,	2,	SUF_Z,	0x01,	0,	0,	0,	CPU_386,	CPU_EPTVPID,	0
 iret,	onebyte_insn,	1,	SUF_Z,	0xCF,	0,	0,	0,	0,	0,	0
 iretd,	onebyte_insn,	1,	SUF_Z,	0xCF,	0x20,	0,	0,	CPU_386,	0,	0
@@ -340,7 +347,7 @@ jrcxz,	jcxz_insn,	2,	SUF_Z,	0x40,	0,	0,	ONLY_64,	0,	0,	0
 js,	jcc_insn,	9,	SUF_Z,	0x08,	0,	0,	0,	0,	0,	0
 jz,	jcc_insn,	9,	SUF_Z,	0x04,	0,	0,	0,	0,	0,	0
 lahf,	onebyte_insn,	1,	SUF_Z,	0x9F,	0,	0,	0,	0,	0,	0
-lar,	bsfr_insn,	3,	SUF_Z,	0x02,	0,	0,	0,	CPU_286,	CPU_Prot,	0
+lar,	larlsl_insn,	6,	SUF_Z,	0x02,	0,	0,	0,	CPU_286,	CPU_Prot,	0
 lddqu,	lddqu_insn,	2,	SUF_Z,	0,	0,	0,	0,	CPU_SSE3,	0,	0
 ldmxcsr,	ldstmxcsr_insn,	1,	SUF_Z,	0x02,	0,	0,	0,	CPU_SSE,	0,	0
 lds,	ldes_insn,	2,	SUF_Z,	0xC5,	0,	0,	NOT_64,	0,	0,	0
@@ -348,9 +355,9 @@ lea,	lea_insn,	3,	SUF_Z,	0,	0,	0,	0,	0,	0,	0
 leave,	onebyte_insn,	1,	SUF_Z,	0xC9,	0x00,	0x40,	0,	CPU_186,	0,	0
 les,	ldes_insn,	2,	SUF_Z,	0xC4,	0,	0,	NOT_64,	0,	0,	0
 lfence,	threebyte_insn,	1,	SUF_Z,	0x0F,	0xAE,	0xE8,	0,	CPU_P3,	0,	0
-lfs,	lfgss_insn,	2,	SUF_Z,	0xB4,	0,	0,	0,	CPU_386,	0,	0
+lfs,	lfgss_insn,	3,	SUF_Z,	0xB4,	0,	0,	0,	CPU_386,	0,	0
 lgdt,	twobytemem_insn,	1,	SUF_Z,	0x02,	0x0F,	0x01,	0,	CPU_286,	CPU_Priv,	0
-lgs,	lfgss_insn,	2,	SUF_Z,	0xB5,	0,	0,	0,	CPU_386,	0,	0
+lgs,	lfgss_insn,	3,	SUF_Z,	0xB5,	0,	0,	0,	CPU_386,	0,	0
 lidt,	twobytemem_insn,	1,	SUF_Z,	0x03,	0x0F,	0x01,	0,	CPU_286,	CPU_Priv,	0
 lldt,	prot286_insn,	1,	SUF_Z,	0x02,	0x00,	0,	0,	CPU_286,	CPU_Priv,	CPU_Prot
 lmsw,	prot286_insn,	1,	SUF_Z,	0x06,	0x01,	0,	0,	CPU_286,	CPU_Priv,	0
@@ -366,10 +373,10 @@ loope,	loop_insn,	8,	SUF_Z,	0x01,	0,	0,	0,	0,	0,	0
 loopne,	loop_insn,	8,	SUF_Z,	0x00,	0,	0,	0,	0,	0,	0
 loopnz,	loop_insn,	8,	SUF_Z,	0x00,	0,	0,	0,	0,	0,	0
 loopz,	loop_insn,	8,	SUF_Z,	0x01,	0,	0,	0,	0,	0,	0
-lsl,	bsfr_insn,	3,	SUF_Z,	0x03,	0,	0,	0,	CPU_286,	CPU_Prot,	0
-lss,	lfgss_insn,	2,	SUF_Z,	0xB2,	0,	0,	0,	CPU_386,	0,	0
+lsl,	larlsl_insn,	6,	SUF_Z,	0x03,	0,	0,	0,	CPU_286,	CPU_Prot,	0
+lss,	lfgss_insn,	3,	SUF_Z,	0xB2,	0,	0,	0,	CPU_386,	0,	0
 ltr,	prot286_insn,	1,	SUF_Z,	0x03,	0x00,	0,	0,	CPU_286,	CPU_Priv,	CPU_Prot
-lzcnt,	cnt_insn,	3,	SUF_Z,	0xBD,	0,	0,	0,	CPU_686,	CPU_AMD,	0
+lzcnt,	cnt_insn,	3,	SUF_Z,	0xBD,	0,	0,	0,	CPU_LZCNT,	0,	0
 maskmovdqu,	maskmovdqu_insn,	1,	SUF_Z,	0,	0,	0,	0,	CPU_SSE2,	0,	0
 maskmovq,	maskmovq_insn,	1,	SUF_Z,	0,	0,	0,	0,	CPU_MMX,	CPU_P3,	0
 maxpd,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0x5F,	0,	0,	CPU_SSE2,	0,	0
@@ -401,7 +408,7 @@ movlps,	movhlp_insn,	3,	SUF_Z,	0x00,	0x12,	0,	0,	CPU_SSE,	0,	0
 movmskpd,	movmsk_insn,	4,	SUF_Z,	0x66,	0,	0,	0,	CPU_SSE2,	0,	0
 movmskps,	movmsk_insn,	4,	SUF_Z,	0,	0,	0,	0,	CPU_386,	CPU_SSE,	0
 movntdq,	movnt_insn,	2,	SUF_Z,	0x66,	0xE7,	0,	0,	CPU_SSE2,	0,	0
-movntdqa,	movntdqa_insn,	1,	SUF_Z,	0,	0,	0,	0,	CPU_SSE41,	0,	0
+movntdqa,	movntdqa_insn,	2,	SUF_Z,	0,	0,	0,	0,	CPU_SSE41,	0,	0
 movnti,	movnti_insn,	2,	SUF_Z,	0,	0,	0,	0,	CPU_P4,	0,	0
 movntpd,	movnt_insn,	2,	SUF_Z,	0x66,	0x2B,	0,	0,	CPU_SSE2,	0,	0
 movntps,	movnt_insn,	2,	SUF_Z,	0x00,	0x2B,	0,	0,	CPU_SSE,	0,	0
@@ -428,6 +435,7 @@ mulpd,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0x59,	0,	0,	CPU_SSE2,	0,	0
 mulps,	xmm_xmm128_insn,	2,	SUF_Z,	0x00,	0x59,	0,	0,	CPU_SSE,	0,	0
 mulsd,	xmm_xmm64_insn,	4,	SUF_Z,	0xF2,	0x59,	0,	0,	CPU_SSE2,	0,	0
 mulss,	xmm_xmm32_insn,	4,	SUF_Z,	0xF3,	0x59,	0,	0,	CPU_SSE,	0,	0
+mulx,	vex_gpr_reg_nds_rm_0F_insn,	2,	SUF_Z,	0xF2,	0x38,	0xF6,	ONLY_AVX,	CPU_BMI2,	0,	0
 mwait,	threebyte_insn,	1,	SUF_Z,	0x0F,	0x01,	0xC9,	0,	CPU_SSE3,	0,	0
 neg,	f6_insn,	4,	SUF_Z,	0x03,	0,	0,	0,	0,	0,	0
 nop,	onebyte_insn,	1,	SUF_Z,	0x90,	0,	0,	0,	0,	0,	0
@@ -442,9 +450,9 @@ out,	out_insn,	12,	SUF_Z,	0,	0,	0,	0,	0,	0,	0
 outsb,	onebyte_insn,	1,	SUF_Z,	0x6E,	0x00,	0,	0,	0,	0,	0
 outsd,	onebyte_insn,	1,	SUF_Z,	0x6F,	0x20,	0,	0,	CPU_386,	0,	0
 outsw,	onebyte_insn,	1,	SUF_Z,	0x6F,	0x10,	0,	0,	0,	0,	0
-pabsb,	ssse3_insn,	3,	SUF_Z,	0x1C,	0,	0,	0,	CPU_SSSE3,	0,	0
-pabsd,	ssse3_insn,	3,	SUF_Z,	0x1E,	0,	0,	0,	CPU_SSSE3,	0,	0
-pabsw,	ssse3_insn,	3,	SUF_Z,	0x1D,	0,	0,	0,	CPU_SSSE3,	0,	0
+pabsb,	ssse3_insn,	5,	SUF_Z,	0x1C,	0,	0,	0,	CPU_SSSE3,	0,	0
+pabsd,	ssse3_insn,	5,	SUF_Z,	0x1E,	0,	0,	0,	CPU_SSSE3,	0,	0
+pabsw,	ssse3_insn,	5,	SUF_Z,	0x1D,	0,	0,	0,	CPU_SSSE3,	0,	0
 packssdw,	mmxsse2_insn,	2,	SUF_Z,	0x6B,	0,	0,	0,	CPU_MMX,	0,	0
 packsswb,	mmxsse2_insn,	2,	SUF_Z,	0x63,	0,	0,	0,	CPU_MMX,	0,	0
 packusdw,	sse4_insn,	2,	SUF_Z,	0x2B,	0,	0,	0,	CPU_SSE41,	0,	0
@@ -485,7 +493,9 @@ pcmpgtq,	sse4_insn,	2,	SUF_Z,	0x37,	0,	0,	0,	CPU_SSE41,	0,	0
 pcmpgtw,	mmxsse2_insn,	2,	SUF_Z,	0x65,	0,	0,	0,	CPU_MMX,	0,	0
 pcmpistri,	sse4pcmpstr_insn,	1,	SUF_Z,	0x63,	0,	0,	0,	CPU_SSE42,	0,	0
 pcmpistrm,	sse4pcmpstr_insn,	1,	SUF_Z,	0x62,	0,	0,	0,	CPU_SSE42,	0,	0
+pdep,	vex_gpr_reg_nds_rm_0F_insn,	2,	SUF_Z,	0xF2,	0x38,	0xF5,	ONLY_AVX,	CPU_BMI2,	0,	0
 pdistib,	cyrixmmx_insn,	1,	SUF_Z,	0x54,	0,	0,	0,	CPU_Cyrix,	CPU_MMX,	0
+pext,	vex_gpr_reg_nds_rm_0F_insn,	2,	SUF_Z,	0xF3,	0x38,	0xF5,	ONLY_AVX,	CPU_BMI2,	0,	0
 pextrb,	pextrb_insn,	3,	SUF_Z,	0,	0,	0,	0,	CPU_SSE41,	0,	0
 pextrd,	pextrd_insn,	1,	SUF_Z,	0,	0,	0,	0,	CPU_386,	CPU_SSE41,	0
 pextrq,	pextrq_insn,	1,	SUF_Z,	0,	0,	0,	ONLY_64,	CPU_SSE41,	0,	0
@@ -509,13 +519,13 @@ pfrsqit1,	now3d_insn,	1,	SUF_Z,	0xA7,	0,	0,	0,	CPU_3DNow,	0,	0
 pfrsqrt,	now3d_insn,	1,	SUF_Z,	0x97,	0,	0,	0,	CPU_3DNow,	0,	0
 pfsub,	now3d_insn,	1,	SUF_Z,	0x9A,	0,	0,	0,	CPU_3DNow,	0,	0
 pfsubr,	now3d_insn,	1,	SUF_Z,	0xAA,	0,	0,	0,	CPU_3DNow,	0,	0
-phaddd,	ssse3_insn,	3,	SUF_Z,	0x02,	0,	0,	0,	CPU_SSSE3,	0,	0
-phaddsw,	ssse3_insn,	3,	SUF_Z,	0x03,	0,	0,	0,	CPU_SSSE3,	0,	0
-phaddw,	ssse3_insn,	3,	SUF_Z,	0x01,	0,	0,	0,	CPU_SSSE3,	0,	0
+phaddd,	ssse3_insn,	5,	SUF_Z,	0x02,	0,	0,	0,	CPU_SSSE3,	0,	0
+phaddsw,	ssse3_insn,	5,	SUF_Z,	0x03,	0,	0,	0,	CPU_SSSE3,	0,	0
+phaddw,	ssse3_insn,	5,	SUF_Z,	0x01,	0,	0,	0,	CPU_SSSE3,	0,	0
 phminposuw,	sse4_insn,	2,	SUF_Z,	0x41,	0,	0,	0,	CPU_SSE41,	0,	0
-phsubd,	ssse3_insn,	3,	SUF_Z,	0x06,	0,	0,	0,	CPU_SSSE3,	0,	0
-phsubsw,	ssse3_insn,	3,	SUF_Z,	0x07,	0,	0,	0,	CPU_SSSE3,	0,	0
-phsubw,	ssse3_insn,	3,	SUF_Z,	0x05,	0,	0,	0,	CPU_SSSE3,	0,	0
+phsubd,	ssse3_insn,	5,	SUF_Z,	0x06,	0,	0,	0,	CPU_SSSE3,	0,	0
+phsubsw,	ssse3_insn,	5,	SUF_Z,	0x07,	0,	0,	0,	CPU_SSSE3,	0,	0
+phsubw,	ssse3_insn,	5,	SUF_Z,	0x05,	0,	0,	0,	CPU_SSSE3,	0,	0
 pi2fd,	now3d_insn,	1,	SUF_Z,	0x0D,	0,	0,	0,	CPU_3DNow,	0,	0
 pi2fw,	now3d_insn,	1,	SUF_Z,	0x0C,	0,	0,	0,	CPU_3DNow,	CPU_Athlon,	0
 pinsrb,	pinsrb_insn,	4,	SUF_Z,	0,	0,	0,	0,	CPU_SSE41,	0,	0
@@ -523,7 +533,7 @@ pinsrd,	pinsrd_insn,	2,	SUF_Z,	0,	0,	0,	0,	CPU_386,	CPU_SSE41,	0
 pinsrq,	pinsrq_insn,	2,	SUF_Z,	0,	0,	0,	ONLY_64,	CPU_SSE41,	0,	0
 pinsrw,	pinsrw_insn,	9,	SUF_Z,	0,	0,	0,	0,	CPU_MMX,	CPU_P3,	0
 pmachriw,	pmachriw_insn,	1,	SUF_Z,	0,	0,	0,	0,	CPU_Cyrix,	CPU_MMX,	0
-pmaddubsw,	ssse3_insn,	3,	SUF_Z,	0x04,	0,	0,	0,	CPU_SSSE3,	0,	0
+pmaddubsw,	ssse3_insn,	5,	SUF_Z,	0x04,	0,	0,	0,	CPU_SSSE3,	0,	0
 pmaddwd,	mmxsse2_insn,	2,	SUF_Z,	0xF5,	0,	0,	0,	CPU_MMX,	0,	0
 pmagw,	cyrixmmx_insn,	1,	SUF_Z,	0x52,	0,	0,	0,	CPU_Cyrix,	CPU_MMX,	0
 pmaxsb,	sse4_insn,	2,	SUF_Z,	0x3C,	0,	0,	0,	CPU_SSE41,	0,	0
@@ -538,22 +548,22 @@ pminsw,	mmxsse2_insn,	2,	SUF_Z,	0xEA,	0,	0,	0,	CPU_MMX,	CPU_P3,	0
 pminub,	mmxsse2_insn,	2,	SUF_Z,	0xDA,	0,	0,	0,	CPU_MMX,	CPU_P3,	0
 pminud,	sse4_insn,	2,	SUF_Z,	0x3B,	0,	0,	0,	CPU_SSE41,	0,	0
 pminuw,	sse4_insn,	2,	SUF_Z,	0x3A,	0,	0,	0,	CPU_SSE41,	0,	0
-pmovmskb,	pmovmskb_insn,	4,	SUF_Z,	0,	0,	0,	0,	CPU_MMX,	CPU_P3,	0
-pmovsxbd,	sse4m32_insn,	2,	SUF_Z,	0x21,	0,	0,	0,	CPU_SSE41,	0,	0
-pmovsxbq,	sse4m16_insn,	2,	SUF_Z,	0x22,	0,	0,	0,	CPU_SSE41,	0,	0
-pmovsxbw,	sse4m64_insn,	2,	SUF_Z,	0x20,	0,	0,	0,	CPU_SSE41,	0,	0
-pmovsxdq,	sse4m64_insn,	2,	SUF_Z,	0x25,	0,	0,	0,	CPU_SSE41,	0,	0
-pmovsxwd,	sse4m64_insn,	2,	SUF_Z,	0x23,	0,	0,	0,	CPU_SSE41,	0,	0
-pmovsxwq,	sse4m32_insn,	2,	SUF_Z,	0x24,	0,	0,	0,	CPU_SSE41,	0,	0
-pmovzxbd,	sse4m32_insn,	2,	SUF_Z,	0x31,	0,	0,	0,	CPU_SSE41,	0,	0
-pmovzxbq,	sse4m16_insn,	2,	SUF_Z,	0x32,	0,	0,	0,	CPU_SSE41,	0,	0
-pmovzxbw,	sse4m64_insn,	2,	SUF_Z,	0x30,	0,	0,	0,	CPU_SSE41,	0,	0
-pmovzxdq,	sse4m64_insn,	2,	SUF_Z,	0x35,	0,	0,	0,	CPU_SSE41,	0,	0
-pmovzxwd,	sse4m64_insn,	2,	SUF_Z,	0x33,	0,	0,	0,	CPU_SSE41,	0,	0
-pmovzxwq,	sse4m32_insn,	2,	SUF_Z,	0x34,	0,	0,	0,	CPU_SSE41,	0,	0
+pmovmskb,	pmovmskb_insn,	6,	SUF_Z,	0,	0,	0,	0,	CPU_MMX,	CPU_P3,	0
+pmovsxbd,	sse4m32_insn,	4,	SUF_Z,	0x21,	0,	0,	0,	CPU_SSE41,	0,	0
+pmovsxbq,	sse4m16_insn,	4,	SUF_Z,	0x22,	0,	0,	0,	CPU_SSE41,	0,	0
+pmovsxbw,	sse4m64_insn,	4,	SUF_Z,	0x20,	0,	0,	0,	CPU_SSE41,	0,	0
+pmovsxdq,	sse4m64_insn,	4,	SUF_Z,	0x25,	0,	0,	0,	CPU_SSE41,	0,	0
+pmovsxwd,	sse4m64_insn,	4,	SUF_Z,	0x23,	0,	0,	0,	CPU_SSE41,	0,	0
+pmovsxwq,	sse4m32_insn,	4,	SUF_Z,	0x24,	0,	0,	0,	CPU_SSE41,	0,	0
+pmovzxbd,	sse4m32_insn,	4,	SUF_Z,	0x31,	0,	0,	0,	CPU_SSE41,	0,	0
+pmovzxbq,	sse4m16_insn,	4,	SUF_Z,	0x32,	0,	0,	0,	CPU_SSE41,	0,	0
+pmovzxbw,	sse4m64_insn,	4,	SUF_Z,	0x30,	0,	0,	0,	CPU_SSE41,	0,	0
+pmovzxdq,	sse4m64_insn,	4,	SUF_Z,	0x35,	0,	0,	0,	CPU_SSE41,	0,	0
+pmovzxwd,	sse4m64_insn,	4,	SUF_Z,	0x33,	0,	0,	0,	CPU_SSE41,	0,	0
+pmovzxwq,	sse4m32_insn,	4,	SUF_Z,	0x34,	0,	0,	0,	CPU_SSE41,	0,	0
 pmuldq,	sse4_insn,	2,	SUF_Z,	0x28,	0,	0,	0,	CPU_SSE41,	0,	0
 pmulhriw,	cyrixmmx_insn,	1,	SUF_Z,	0x5D,	0,	0,	0,	CPU_Cyrix,	CPU_MMX,	0
-pmulhrsw,	ssse3_insn,	3,	SUF_Z,	0x0B,	0,	0,	0,	CPU_SSSE3,	0,	0
+pmulhrsw,	ssse3_insn,	5,	SUF_Z,	0x0B,	0,	0,	0,	CPU_SSSE3,	0,	0
 pmulhrwa,	now3d_insn,	1,	SUF_Z,	0xB7,	0,	0,	0,	CPU_3DNow,	0,	0
 pmulhrwc,	cyrixmmx_insn,	1,	SUF_Z,	0x59,	0,	0,	0,	CPU_Cyrix,	CPU_MMX,	0
 pmulhuw,	mmxsse2_insn,	2,	SUF_Z,	0xE4,	0,	0,	0,	CPU_MMX,	CPU_P3,	0
@@ -565,7 +575,7 @@ pmvgezb,	cyrixmmx_insn,	1,	SUF_Z,	0x5C,	0,	0,	0,	CPU_Cyrix,	CPU_MMX,	0
 pmvlzb,	cyrixmmx_insn,	1,	SUF_Z,	0x5B,	0,	0,	0,	CPU_Cyrix,	CPU_MMX,	0
 pmvnzb,	cyrixmmx_insn,	1,	SUF_Z,	0x5A,	0,	0,	0,	CPU_Cyrix,	CPU_MMX,	0
 pmvzb,	cyrixmmx_insn,	1,	SUF_Z,	0x58,	0,	0,	0,	CPU_Cyrix,	CPU_MMX,	0
-pop,	pop_insn,	21,	SUF_Z,	0,	0,	0,	0,	0,	0,	0
+pop,	pop_insn,	23,	SUF_Z,	0,	0,	0,	0,	0,	0,	0
 popa,	onebyte_insn,	1,	SUF_Z,	0x61,	0x00,	0,	NOT_64,	CPU_186,	0,	0
 popad,	onebyte_insn,	1,	SUF_Z,	0x61,	0x20,	0,	NOT_64,	CPU_386,	0,	0
 popaw,	onebyte_insn,	1,	SUF_Z,	0x61,	0x10,	0,	NOT_64,	CPU_186,	0,	0
@@ -582,22 +592,22 @@ prefetcht1,	twobytemem_insn,	1,	SUF_Z,	0x02,	0x0F,	0x18,	0,	CPU_P3,	0,	0
 prefetcht2,	twobytemem_insn,	1,	SUF_Z,	0x03,	0x0F,	0x18,	0,	CPU_P3,	0,	0
 prefetchw,	twobytemem_insn,	1,	SUF_Z,	0x01,	0x0F,	0x0D,	0,	CPU_3DNow,	0,	0
 psadbw,	mmxsse2_insn,	2,	SUF_Z,	0xF6,	0,	0,	0,	CPU_MMX,	CPU_P3,	0
-pshufb,	ssse3_insn,	3,	SUF_Z,	0x00,	0,	0,	0,	CPU_SSSE3,	0,	0
+pshufb,	ssse3_insn,	5,	SUF_Z,	0x00,	0,	0,	0,	CPU_SSSE3,	0,	0
 pshufd,	xmm_xmm128_imm_insn,	1,	SUF_Z,	0x66,	0x70,	0,	0,	CPU_SSE2,	0,	0
 pshufhw,	xmm_xmm128_imm_insn,	1,	SUF_Z,	0xF3,	0x70,	0,	0,	CPU_SSE2,	0,	0
 pshuflw,	xmm_xmm128_imm_insn,	1,	SUF_Z,	0xF2,	0x70,	0,	0,	CPU_SSE2,	0,	0
 pshufw,	pshufw_insn,	1,	SUF_Z,	0,	0,	0,	0,	CPU_MMX,	CPU_P3,	0
-psignb,	ssse3_insn,	3,	SUF_Z,	0x08,	0,	0,	0,	CPU_SSSE3,	0,	0
-psignd,	ssse3_insn,	3,	SUF_Z,	0x0A,	0,	0,	0,	CPU_SSSE3,	0,	0
-psignw,	ssse3_insn,	3,	SUF_Z,	0x09,	0,	0,	0,	CPU_SSSE3,	0,	0
+psignb,	ssse3_insn,	5,	SUF_Z,	0x08,	0,	0,	0,	CPU_SSSE3,	0,	0
+psignd,	ssse3_insn,	5,	SUF_Z,	0x0A,	0,	0,	0,	CPU_SSSE3,	0,	0
+psignw,	ssse3_insn,	5,	SUF_Z,	0x09,	0,	0,	0,	CPU_SSSE3,	0,	0
 pslld,	pshift_insn,	4,	SUF_Z,	0xF2,	0x72,	0x06,	0,	CPU_MMX,	0,	0
-pslldq,	pslrldq_insn,	2,	SUF_Z,	0x07,	0,	0,	0,	CPU_SSE2,	0,	0
+pslldq,	pslrldq_insn,	4,	SUF_Z,	0x07,	0,	0,	0,	CPU_SSE2,	0,	0
 psllq,	pshift_insn,	4,	SUF_Z,	0xF3,	0x73,	0x06,	0,	CPU_MMX,	0,	0
 psllw,	pshift_insn,	4,	SUF_Z,	0xF1,	0x71,	0x06,	0,	CPU_MMX,	0,	0
 psrad,	pshift_insn,	4,	SUF_Z,	0xE2,	0x72,	0x04,	0,	CPU_MMX,	0,	0
 psraw,	pshift_insn,	4,	SUF_Z,	0xE1,	0x71,	0x04,	0,	CPU_MMX,	0,	0
 psrld,	pshift_insn,	4,	SUF_Z,	0xD2,	0x72,	0x02,	0,	CPU_MMX,	0,	0
-psrldq,	pslrldq_insn,	2,	SUF_Z,	0x03,	0,	0,	0,	CPU_SSE2,	0,	0
+psrldq,	pslrldq_insn,	4,	SUF_Z,	0x03,	0,	0,	0,	CPU_SSE2,	0,	0
 psrlq,	pshift_insn,	4,	SUF_Z,	0xD3,	0x73,	0x02,	0,	CPU_MMX,	0,	0
 psrlw,	pshift_insn,	4,	SUF_Z,	0xD1,	0x71,	0x02,	0,	CPU_MMX,	0,	0
 psubb,	mmxsse2_insn,	2,	SUF_Z,	0xF8,	0,	0,	0,	CPU_MMX,	0,	0
@@ -619,7 +629,7 @@ punpcklbw,	mmxsse2_insn,	2,	SUF_Z,	0x60,	0,	0,	0,	CPU_MMX,	0,	0
 punpckldq,	mmxsse2_insn,	2,	SUF_Z,	0x62,	0,	0,	0,	CPU_MMX,	0,	0
 punpcklqdq,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0x6C,	0,	0,	CPU_SSE2,	0,	0
 punpcklwd,	mmxsse2_insn,	2,	SUF_Z,	0x61,	0,	0,	0,	CPU_MMX,	0,	0
-push,	push_insn,	33,	SUF_Z,	0,	0,	0,	0,	0,	0,	0
+push,	push_insn,	35,	SUF_Z,	0,	0,	0,	0,	0,	0,	0
 pusha,	onebyte_insn,	1,	SUF_Z,	0x60,	0x00,	0,	NOT_64,	CPU_186,	0,	0
 pushad,	onebyte_insn,	1,	SUF_Z,	0x60,	0x20,	0,	NOT_64,	CPU_386,	0,	0
 pushaw,	onebyte_insn,	1,	SUF_Z,	0x60,	0x10,	0,	NOT_64,	CPU_186,	0,	0
@@ -650,6 +660,7 @@ retf,	retnf_insn,	6,	SUF_Z,	0xCA,	0x40,	0,	0,	0,	0,	0
 retn,	retnf_insn,	6,	SUF_Z,	0xC2,	0,	0,	0,	0,	0,	0
 rol,	shift_insn,	16,	SUF_Z,	0x00,	0,	0,	0,	0,	0,	0
 ror,	shift_insn,	16,	SUF_Z,	0x01,	0,	0,	0,	0,	0,	0
+rorx,	vex_gpr_reg_rm_0F_imm8_insn,	2,	SUF_Z,	0xF2,	0x3A,	0xF0,	ONLY_AVX,	CPU_BMI2,	0,	0
 roundpd,	sse4imm_insn,	2,	SUF_Z,	0x09,	0,	0,	0,	CPU_SSE41,	0,	0
 roundps,	sse4imm_insn,	2,	SUF_Z,	0x08,	0,	0,	0,	CPU_SSE41,	0,	0
 roundsd,	sse4m64imm_insn,	4,	SUF_Z,	0x0B,	0,	0,	0,	CPU_SSE41,	0,	0
@@ -664,6 +675,7 @@ sahf,	onebyte_insn,	1,	SUF_Z,	0x9E,	0,	0,	0,	0,	0,	0
 sal,	shift_insn,	16,	SUF_Z,	0x04,	0,	0,	0,	0,	0,	0
 salc,	onebyte_insn,	1,	SUF_Z,	0xD6,	0,	0,	NOT_64,	CPU_Undoc,	0,	0
 sar,	shift_insn,	16,	SUF_Z,	0x07,	0,	0,	0,	0,	0,	0
+sarx,	vex_gpr_reg_rm_nds_0F_insn,	2,	SUF_Z,	0xF3,	0x38,	0xF7,	ONLY_AVX,	CPU_BMI2,	0,	0
 sbb,	arith_insn,	22,	SUF_Z,	0x18,	0x03,	0,	0,	0,	0,	0
 scasb,	onebyte_insn,	1,	SUF_Z,	0xAE,	0x00,	0,	0,	0,	0,	0
 scasd,	onebyte_insn,	1,	SUF_Z,	0xAF,	0x20,	0,	0,	CPU_386,	0,	0
@@ -703,8 +715,10 @@ sfence,	threebyte_insn,	1,	SUF_Z,	0x0F,	0xAE,	0xF8,	0,	CPU_P3,	0,	0
 sgdt,	twobytemem_insn,	1,	SUF_Z,	0x00,	0x0F,	0x01,	0,	CPU_286,	CPU_Priv,	0
 shl,	shift_insn,	16,	SUF_Z,	0x04,	0,	0,	0,	0,	0,	0
 shld,	shlrd_insn,	9,	SUF_Z,	0xA4,	0,	0,	0,	CPU_386,	0,	0
+shlx,	vex_gpr_reg_rm_nds_0F_insn,	2,	SUF_Z,	0x66,	0x38,	0xF7,	ONLY_AVX,	CPU_BMI2,	0,	0
 shr,	shift_insn,	16,	SUF_Z,	0x05,	0,	0,	0,	0,	0,	0
 shrd,	shlrd_insn,	9,	SUF_Z,	0xAC,	0,	0,	0,	CPU_386,	0,	0
+shrx,	vex_gpr_reg_rm_nds_0F_insn,	2,	SUF_Z,	0xF2,	0x38,	0xF7,	ONLY_AVX,	CPU_BMI2,	0,	0
 shufpd,	xmm_xmm128_imm_insn,	1,	SUF_Z,	0x66,	0xC6,	0,	0,	CPU_SSE2,	0,	0
 shufps,	xmm_xmm128_imm_insn,	1,	SUF_Z,	0x00,	0xC6,	0,	0,	CPU_SSE,	0,	0
 sidt,	twobytemem_insn,	1,	SUF_Z,	0x01,	0x0F,	0x01,	0,	CPU_286,	CPU_Priv,	0
@@ -742,6 +756,7 @@ sysenter,	twobyte_insn,	1,	SUF_Z,	0x0F,	0x34,	0,	NOT_64,	CPU_686,	0,	0
 sysexit,	twobyte_insn,	1,	SUF_Z,	0x0F,	0x35,	0,	NOT_64,	CPU_686,	CPU_Priv,	0
 sysret,	twobyte_insn,	1,	SUF_Z,	0x0F,	0x07,	0,	0,	CPU_686,	CPU_AMD,	CPU_Priv
 test,	test_insn,	20,	SUF_Z,	0,	0,	0,	0,	0,	0,	0
+tzcnt,	cnt_insn,	3,	SUF_Z,	0xBC,	0,	0,	0,	CPU_BMI1,	0,	0
 ucomisd,	xmm_xmm64_insn,	4,	SUF_Z,	0x66,	0x2E,	0,	0,	CPU_SSE2,	0,	0
 ucomiss,	xmm_xmm32_insn,	4,	SUF_Z,	0x00,	0x2E,	0,	0,	CPU_SSE,	0,	0
 ud1,	twobyte_insn,	1,	SUF_Z,	0x0F,	0xB9,	0,	0,	CPU_286,	CPU_Undoc,	0
@@ -751,29 +766,30 @@ unpckhpd,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0x15,	0,	0,	CPU_SSE2,	0,	0
 unpckhps,	xmm_xmm128_insn,	2,	SUF_Z,	0x00,	0x15,	0,	0,	CPU_SSE,	0,	0
 unpcklpd,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0x14,	0,	0,	CPU_SSE2,	0,	0
 unpcklps,	xmm_xmm128_insn,	2,	SUF_Z,	0x00,	0x14,	0,	0,	CPU_SSE,	0,	0
-vaddpd,	xmm_xmm128_256_insn,	3,	SUF_Z,	0x66,	0x58,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vaddps,	xmm_xmm128_256_insn,	3,	SUF_Z,	0x00,	0x58,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vaddpd,	xmm_xmm128_256_insn,	4,	SUF_Z,	0x66,	0x58,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vaddps,	xmm_xmm128_256_insn,	4,	SUF_Z,	0x00,	0x58,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
 vaddsd,	xmm_xmm64_insn,	4,	SUF_Z,	0xF2,	0x58,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
 vaddss,	xmm_xmm32_insn,	4,	SUF_Z,	0xF3,	0x58,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vaddsubpd,	xmm_xmm128_256_insn,	3,	SUF_Z,	0x66,	0xD0,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vaddsubps,	xmm_xmm128_256_insn,	3,	SUF_Z,	0xF2,	0xD0,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vaddsubpd,	xmm_xmm128_256_insn,	4,	SUF_Z,	0x66,	0xD0,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vaddsubps,	xmm_xmm128_256_insn,	4,	SUF_Z,	0xF2,	0xD0,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
 vaesdec,	aes_insn,	2,	SUF_Z,	0x38,	0xDE,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
 vaesdeclast,	aes_insn,	2,	SUF_Z,	0x38,	0xDF,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
 vaesenc,	aes_insn,	2,	SUF_Z,	0x38,	0xDC,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
 vaesenclast,	aes_insn,	2,	SUF_Z,	0x38,	0xDD,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
 vaesimc,	aesimc_insn,	1,	SUF_Z,	0x38,	0xDB,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
 vaeskeygenassist,	aes_imm_insn,	1,	SUF_Z,	0x3A,	0xDF,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vandnpd,	xmm_xmm128_256_insn,	3,	SUF_Z,	0x66,	0x55,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vandnps,	xmm_xmm128_256_insn,	3,	SUF_Z,	0x00,	0x55,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vandpd,	xmm_xmm128_256_insn,	3,	SUF_Z,	0x66,	0x54,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vandps,	xmm_xmm128_256_insn,	3,	SUF_Z,	0x00,	0x54,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vblendpd,	sse4imm_256_insn,	3,	SUF_Z,	0x0D,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vblendps,	sse4imm_256_insn,	3,	SUF_Z,	0x0C,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vandnpd,	xmm_xmm128_256_insn,	4,	SUF_Z,	0x66,	0x55,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vandnps,	xmm_xmm128_256_insn,	4,	SUF_Z,	0x00,	0x55,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vandpd,	xmm_xmm128_256_insn,	4,	SUF_Z,	0x66,	0x54,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vandps,	xmm_xmm128_256_insn,	4,	SUF_Z,	0x00,	0x54,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vblendpd,	sse4imm_256_insn,	4,	SUF_Z,	0x0D,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vblendps,	sse4imm_256_insn,	4,	SUF_Z,	0x0C,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
 vblendvpd,	avx_sse4xmm0_insn,	2,	SUF_Z,	0x4B,	0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
 vblendvps,	avx_sse4xmm0_insn,	2,	SUF_Z,	0x4A,	0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vbroadcastf128,	vbroadcastf128_insn,	1,	SUF_Z,	0,	0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vbroadcastsd,	vbroadcastsd_insn,	1,	SUF_Z,	0,	0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vbroadcastss,	vbroadcastss_insn,	2,	SUF_Z,	0,	0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vbroadcastf128,	vbroadcastif128_insn,	1,	SUF_Z,	0x1A,	0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vbroadcasti128,	vbroadcastif128_insn,	1,	SUF_Z,	0x5A,	0,	0,	ONLY_AVX,	CPU_AVX2,	0,	0
+vbroadcastsd,	vbroadcastsd_insn,	2,	SUF_Z,	0,	0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vbroadcastss,	vbroadcastss_insn,	4,	SUF_Z,	0,	0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
 vcmpeq_ospd,	ssecmp_128_insn,	3,	SUF_Z,	0x10,	0x66,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
 vcmpeq_osps,	ssecmp_128_insn,	3,	SUF_Z,	0x10,	0x00,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
 vcmpeq_ossd,	ssecmp_64_insn,	4,	SUF_Z,	0x10,	0xF2,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
@@ -926,15 +942,16 @@ vcvttpd2dq,	avx_cvt_xmm128_insn,	2,	SUF_Z,	0x66,	0xE6,	0,	ONLY_AVX,	CPU_AVX,	0,
 vcvttps2dq,	avx_xmm_xmm128_insn,	2,	SUF_Z,	0xF3,	0x5B,	0,	ONLY_AVX,	CPU_AVX,	0,	0
 vcvttsd2si,	cvt_rx_xmm64_insn,	4,	SUF_Z,	0xF2,	0x2C,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
 vcvttss2si,	cvt_rx_xmm32_insn,	4,	SUF_Z,	0xF3,	0x2C,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vdivpd,	xmm_xmm128_256_insn,	3,	SUF_Z,	0x66,	0x5E,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vdivps,	xmm_xmm128_256_insn,	3,	SUF_Z,	0x00,	0x5E,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vdivpd,	xmm_xmm128_256_insn,	4,	SUF_Z,	0x66,	0x5E,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vdivps,	xmm_xmm128_256_insn,	4,	SUF_Z,	0x00,	0x5E,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
 vdivsd,	xmm_xmm64_insn,	4,	SUF_Z,	0xF2,	0x5E,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
 vdivss,	xmm_xmm32_insn,	4,	SUF_Z,	0xF3,	0x5E,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
 vdppd,	sse4imm_insn,	2,	SUF_Z,	0x41,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vdpps,	sse4imm_256_insn,	3,	SUF_Z,	0x40,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vdpps,	sse4imm_256_insn,	4,	SUF_Z,	0x40,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
 verr,	prot286_insn,	1,	SUF_Z,	0x04,	0x00,	0,	0,	CPU_286,	CPU_Prot,	0
 verw,	prot286_insn,	1,	SUF_Z,	0x05,	0x00,	0,	0,	CPU_286,	CPU_Prot,	0
-vextractf128,	vextractf128_insn,	1,	SUF_Z,	0,	0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vextractf128,	vextractif128_insn,	1,	SUF_Z,	0x19,	0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vextracti128,	vextractif128_insn,	1,	SUF_Z,	0x39,	0,	0,	ONLY_AVX,	CPU_AVX2,	0,	0
 vextractps,	extractps_insn,	2,	SUF_Z,	0xC0,	0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
 vfmadd132pd,	vfma_pd_insn,	2,	SUF_Z,	0x98,	0,	0,	ONLY_AVX,	CPU_FMA,	0,	0
 vfmadd132ps,	vfma_ps_insn,	2,	SUF_Z,	0x98,	0,	0,	ONLY_AVX,	CPU_FMA,	0,	0
@@ -1020,25 +1037,30 @@ vfrczpd,	vfrc_pdps_insn,	2,	SUF_Z,	0x01,	0,	0,	0,	CPU_XOP,	0,	0
 vfrczps,	vfrc_pdps_insn,	2,	SUF_Z,	0x00,	0,	0,	0,	CPU_XOP,	0,	0
 vfrczsd,	vfrczsd_insn,	2,	SUF_Z,	0,	0,	0,	0,	CPU_XOP,	0,	0
 vfrczss,	vfrczss_insn,	2,	SUF_Z,	0,	0,	0,	0,	CPU_XOP,	0,	0
-vhaddpd,	xmm_xmm128_256_insn,	3,	SUF_Z,	0x66,	0x7C,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vhaddps,	xmm_xmm128_256_insn,	3,	SUF_Z,	0xF2,	0x7C,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vhsubpd,	xmm_xmm128_256_insn,	3,	SUF_Z,	0x66,	0x7D,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vhsubps,	xmm_xmm128_256_insn,	3,	SUF_Z,	0xF2,	0x7D,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vinsertf128,	vinsertf128_insn,	1,	SUF_Z,	0,	0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vgatherdpd,	gather_64x_64x_insn,	2,	SUF_Z,	0x92,	0,	0,	ONLY_AVX,	CPU_AVX2,	0,	0
+vgatherdps,	gather_32x_32y_insn,	2,	SUF_Z,	0x92,	0,	0,	ONLY_AVX,	CPU_AVX2,	0,	0
+vgatherqpd,	gather_64x_64y_insn,	2,	SUF_Z,	0x93,	0,	0,	ONLY_AVX,	CPU_AVX2,	0,	0
+vgatherqps,	gather_32x_32y_128_insn,	2,	SUF_Z,	0x93,	0,	0,	ONLY_AVX,	CPU_AVX2,	0,	0
+vhaddpd,	xmm_xmm128_256_insn,	4,	SUF_Z,	0x66,	0x7C,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vhaddps,	xmm_xmm128_256_insn,	4,	SUF_Z,	0xF2,	0x7C,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vhsubpd,	xmm_xmm128_256_insn,	4,	SUF_Z,	0x66,	0x7D,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vhsubps,	xmm_xmm128_256_insn,	4,	SUF_Z,	0xF2,	0x7D,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vinsertf128,	vinsertif128_insn,	1,	SUF_Z,	0x18,	0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vinserti128,	vinsertif128_insn,	1,	SUF_Z,	0x38,	0,	0,	ONLY_AVX,	CPU_AVX2,	0,	0
 vinsertps,	insertps_insn,	4,	SUF_Z,	0xC0,	0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
 vlddqu,	lddqu_insn,	2,	SUF_Z,	0xC0,	0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
 vldmxcsr,	ldstmxcsr_insn,	1,	SUF_Z,	0x02,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
 vmaskmovdqu,	maskmovdqu_insn,	1,	SUF_Z,	0xC0,	0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
 vmaskmovpd,	vmaskmov_insn,	4,	SUF_Z,	0x2D,	0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
 vmaskmovps,	vmaskmov_insn,	4,	SUF_Z,	0x2C,	0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vmaxpd,	xmm_xmm128_256_insn,	3,	SUF_Z,	0x66,	0x5F,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vmaxps,	xmm_xmm128_256_insn,	3,	SUF_Z,	0x00,	0x5F,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vmaxpd,	xmm_xmm128_256_insn,	4,	SUF_Z,	0x66,	0x5F,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vmaxps,	xmm_xmm128_256_insn,	4,	SUF_Z,	0x00,	0x5F,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
 vmaxsd,	xmm_xmm64_insn,	4,	SUF_Z,	0xF2,	0x5F,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
 vmaxss,	xmm_xmm32_insn,	4,	SUF_Z,	0xF3,	0x5F,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
 vmcall,	threebyte_insn,	1,	SUF_Z,	0x0F,	0x01,	0xC1,	0,	CPU_P4,	0,	0
 vmclear,	vmxthreebytemem_insn,	1,	SUF_Z,	0x66,	0,	0,	0,	CPU_P4,	0,	0
-vminpd,	xmm_xmm128_256_insn,	3,	SUF_Z,	0x66,	0x5D,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vminps,	xmm_xmm128_256_insn,	3,	SUF_Z,	0x00,	0x5D,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vminpd,	xmm_xmm128_256_insn,	4,	SUF_Z,	0x66,	0x5D,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vminps,	xmm_xmm128_256_insn,	4,	SUF_Z,	0x00,	0x5D,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
 vminsd,	xmm_xmm64_insn,	4,	SUF_Z,	0xF2,	0x5D,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
 vminss,	xmm_xmm32_insn,	4,	SUF_Z,	0xF3,	0x5D,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
 vmlaunch,	threebyte_insn,	1,	SUF_Z,	0x0F,	0x01,	0xC2,	0,	CPU_P4,	0,	0
@@ -1059,7 +1081,7 @@ vmovlps,	movhlp_insn,	3,	SUF_Z,	0x00,	0x12,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
 vmovmskpd,	movmsk_insn,	4,	SUF_Z,	0x66,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
 vmovmskps,	movmsk_insn,	4,	SUF_Z,	0x00,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
 vmovntdq,	movnt_insn,	2,	SUF_Z,	0x66,	0xE7,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vmovntdqa,	movntdqa_insn,	1,	SUF_Z,	0xC0,	0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vmovntdqa,	movntdqa_insn,	2,	SUF_Z,	0xC0,	0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
 vmovntpd,	movnt_insn,	2,	SUF_Z,	0x66,	0x2B,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
 vmovntps,	movnt_insn,	2,	SUF_Z,	0x00,	0x2B,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
 vmovq,	vmovq_insn,	5,	SUF_Z,	0,	0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
@@ -1069,60 +1091,65 @@ vmovsldup,	avx_xmm_xmm128_insn,	2,	SUF_Z,	0xF3,	0x12,	0,	ONLY_AVX,	CPU_AVX,	0,	0
 vmovss,	movss_insn,	4,	SUF_Z,	0xC0,	0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
 vmovupd,	movau_insn,	6,	SUF_Z,	0x66,	0x10,	0x01,	ONLY_AVX,	CPU_AVX,	0,	0
 vmovups,	movau_insn,	6,	SUF_Z,	0x00,	0x10,	0x01,	ONLY_AVX,	CPU_AVX,	0,	0
-vmpsadbw,	sse4imm_insn,	2,	SUF_Z,	0x42,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vmpsadbw,	sse4imm_256avx2_insn,	4,	SUF_Z,	0x42,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
 vmptrld,	vmxtwobytemem_insn,	1,	SUF_Z,	0x06,	0,	0,	0,	CPU_P4,	0,	0
 vmptrst,	vmxtwobytemem_insn,	1,	SUF_Z,	0x07,	0,	0,	0,	CPU_P4,	0,	0
 vmread,	vmxmemrd_insn,	2,	SUF_Z,	0,	0,	0,	0,	CPU_P4,	0,	0
 vmresume,	threebyte_insn,	1,	SUF_Z,	0x0F,	0x01,	0xC3,	0,	CPU_P4,	0,	0
 vmrun,	svm_rax_insn,	2,	SUF_Z,	0xD8,	0,	0,	0,	CPU_SVM,	0,	0
 vmsave,	svm_rax_insn,	2,	SUF_Z,	0xDB,	0,	0,	0,	CPU_SVM,	0,	0
-vmulpd,	xmm_xmm128_256_insn,	3,	SUF_Z,	0x66,	0x59,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vmulps,	xmm_xmm128_256_insn,	3,	SUF_Z,	0x00,	0x59,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vmulpd,	xmm_xmm128_256_insn,	4,	SUF_Z,	0x66,	0x59,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vmulps,	xmm_xmm128_256_insn,	4,	SUF_Z,	0x00,	0x59,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
 vmulsd,	xmm_xmm64_insn,	4,	SUF_Z,	0xF2,	0x59,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
 vmulss,	xmm_xmm32_insn,	4,	SUF_Z,	0xF3,	0x59,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
 vmwrite,	vmxmemwr_insn,	2,	SUF_Z,	0,	0,	0,	0,	CPU_P4,	0,	0
 vmxoff,	threebyte_insn,	1,	SUF_Z,	0x0F,	0x01,	0xC4,	0,	CPU_P4,	0,	0
 vmxon,	vmxthreebytemem_insn,	1,	SUF_Z,	0xF3,	0,	0,	0,	CPU_P4,	0,	0
-vorpd,	xmm_xmm128_256_insn,	3,	SUF_Z,	0x66,	0x56,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vorps,	xmm_xmm128_256_insn,	3,	SUF_Z,	0x00,	0x56,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpabsb,	avx_ssse3_2op_insn,	1,	SUF_Z,	0x1C,	0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpabsd,	avx_ssse3_2op_insn,	1,	SUF_Z,	0x1E,	0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpabsw,	avx_ssse3_2op_insn,	1,	SUF_Z,	0x1D,	0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpackssdw,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0x6B,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpacksswb,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0x63,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpackusdw,	ssse3_insn,	3,	SUF_Z,	0x2B,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpackuswb,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0x67,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpaddb,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0xFC,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpaddd,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0xFE,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpaddq,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0xD4,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpaddsb,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0xEC,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpaddsw,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0xED,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpaddusb,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0xDC,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpaddusw,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0xDD,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpaddw,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0xFD,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpalignr,	sse4imm_insn,	2,	SUF_Z,	0x0F,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpand,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0xDB,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpandn,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0xDF,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpavgb,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0xE0,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpavgw,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0xE3,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpblendvb,	avx_sse4xmm0_128_insn,	1,	SUF_Z,	0x4C,	0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpblendw,	sse4imm_insn,	2,	SUF_Z,	0x0E,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vorpd,	xmm_xmm128_256_insn,	4,	SUF_Z,	0x66,	0x56,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vorps,	xmm_xmm128_256_insn,	4,	SUF_Z,	0x00,	0x56,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpabsb,	avx2_ssse3_2op_insn,	2,	SUF_Z,	0x1C,	0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpabsd,	avx2_ssse3_2op_insn,	2,	SUF_Z,	0x1E,	0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpabsw,	avx2_ssse3_2op_insn,	2,	SUF_Z,	0x1D,	0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpackssdw,	xmm_xmm128_256avx2_insn,	4,	SUF_Z,	0x66,	0x6B,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpacksswb,	xmm_xmm128_256avx2_insn,	4,	SUF_Z,	0x66,	0x63,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpackusdw,	ssse3_insn,	5,	SUF_Z,	0x2B,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpackuswb,	xmm_xmm128_256avx2_insn,	4,	SUF_Z,	0x66,	0x67,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpaddb,	xmm_xmm128_256avx2_insn,	4,	SUF_Z,	0x66,	0xFC,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpaddd,	xmm_xmm128_256avx2_insn,	4,	SUF_Z,	0x66,	0xFE,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpaddq,	xmm_xmm128_256avx2_insn,	4,	SUF_Z,	0x66,	0xD4,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpaddsb,	xmm_xmm128_256avx2_insn,	4,	SUF_Z,	0x66,	0xEC,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpaddsw,	xmm_xmm128_256avx2_insn,	4,	SUF_Z,	0x66,	0xED,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpaddusb,	xmm_xmm128_256avx2_insn,	4,	SUF_Z,	0x66,	0xDC,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpaddusw,	xmm_xmm128_256avx2_insn,	4,	SUF_Z,	0x66,	0xDD,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpaddw,	xmm_xmm128_256avx2_insn,	4,	SUF_Z,	0x66,	0xFD,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpalignr,	sse4imm_256avx2_insn,	4,	SUF_Z,	0x0F,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpand,	xmm_xmm128_256avx2_insn,	4,	SUF_Z,	0x66,	0xDB,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpandn,	xmm_xmm128_256avx2_insn,	4,	SUF_Z,	0x66,	0xDF,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpavgb,	xmm_xmm128_256avx2_insn,	4,	SUF_Z,	0x66,	0xE0,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpavgw,	xmm_xmm128_256avx2_insn,	4,	SUF_Z,	0x66,	0xE3,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpblendd,	vex_66_0F3A_imm8_avx2_insn,	2,	SUF_Z,	0x02,	0,	0,	ONLY_AVX,	CPU_AVX2,	0,	0
+vpblendvb,	avx2_sse4xmm0_insn,	2,	SUF_Z,	0x4C,	0,	0,	ONLY_AVX,	CPU_AVX2,	0,	0
+vpblendw,	sse4imm_256avx2_insn,	4,	SUF_Z,	0x0E,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpbroadcastb,	vpbroadcastb_avx2_insn,	4,	SUF_Z,	0,	0,	0,	ONLY_AVX,	CPU_AVX2,	0,	0
+vpbroadcastd,	vpbroadcastd_avx2_insn,	4,	SUF_Z,	0,	0,	0,	ONLY_AVX,	CPU_AVX2,	0,	0
+vpbroadcastq,	vpbroadcastq_avx2_insn,	4,	SUF_Z,	0,	0,	0,	ONLY_AVX,	CPU_AVX2,	0,	0
+vpbroadcastw,	vpbroadcastw_avx2_insn,	4,	SUF_Z,	0,	0,	0,	ONLY_AVX,	CPU_AVX2,	0,	0
 vpclmulhqhqdq,	pclmulqdq_fixed_insn,	2,	SUF_Z,	0x11,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
 vpclmulhqlqdq,	pclmulqdq_fixed_insn,	2,	SUF_Z,	0x01,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
 vpclmullqhqdq,	pclmulqdq_fixed_insn,	2,	SUF_Z,	0x10,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
 vpclmullqlqdq,	pclmulqdq_fixed_insn,	2,	SUF_Z,	0x00,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
 vpclmulqdq,	pclmulqdq_insn,	2,	SUF_Z,	0x3A,	0x44,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
 vpcmov,	vpcmov_insn,	4,	SUF_Z,	0,	0,	0,	0,	CPU_XOP,	0,	0
-vpcmpeqb,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0x74,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpcmpeqd,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0x76,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpcmpeqq,	ssse3_insn,	3,	SUF_Z,	0x29,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpcmpeqw,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0x75,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpcmpeqb,	xmm_xmm128_256avx2_insn,	4,	SUF_Z,	0x66,	0x74,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpcmpeqd,	xmm_xmm128_256avx2_insn,	4,	SUF_Z,	0x66,	0x76,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpcmpeqq,	ssse3_insn,	5,	SUF_Z,	0x29,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpcmpeqw,	xmm_xmm128_256avx2_insn,	4,	SUF_Z,	0x66,	0x75,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
 vpcmpestri,	sse4pcmpstr_insn,	1,	SUF_Z,	0x61,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
 vpcmpestrm,	sse4pcmpstr_insn,	1,	SUF_Z,	0x60,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpcmpgtb,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0x64,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpcmpgtd,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0x66,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpcmpgtq,	ssse3_insn,	3,	SUF_Z,	0x37,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpcmpgtw,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0x65,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpcmpgtb,	xmm_xmm128_256avx2_insn,	4,	SUF_Z,	0x66,	0x64,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpcmpgtd,	xmm_xmm128_256avx2_insn,	4,	SUF_Z,	0x66,	0x66,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpcmpgtq,	ssse3_insn,	5,	SUF_Z,	0x37,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpcmpgtw,	xmm_xmm128_256avx2_insn,	4,	SUF_Z,	0x66,	0x65,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
 vpcmpistri,	sse4pcmpstr_insn,	1,	SUF_Z,	0x63,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
 vpcmpistrm,	sse4pcmpstr_insn,	1,	SUF_Z,	0x62,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
 vpcomb,	vpcom_imm_insn,	1,	SUF_Z,	0xCC,	0,	0,	0,	CPU_XOP,	0,	0
@@ -1206,33 +1233,42 @@ vpcomuq,	vpcom_imm_insn,	1,	SUF_Z,	0xEF,	0,	0,	0,	CPU_XOP,	0,	0
 vpcomuw,	vpcom_imm_insn,	1,	SUF_Z,	0xED,	0,	0,	0,	CPU_XOP,	0,	0
 vpcomw,	vpcom_imm_insn,	1,	SUF_Z,	0xCD,	0,	0,	0,	CPU_XOP,	0,	0
 vperm2f128,	vperm2f128_insn,	1,	SUF_Z,	0,	0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vperm2i128,	vperm2i128_avx2_insn,	1,	SUF_Z,	0,	0,	0,	ONLY_AVX,	CPU_AVX2,	0,	0
+vpermd,	vperm_var_avx2_insn,	1,	SUF_Z,	0x36,	0,	0,	ONLY_AVX,	CPU_AVX2,	0,	0
 vpermilpd,	vpermil_insn,	4,	SUF_Z,	0x05,	0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
 vpermilps,	vpermil_insn,	4,	SUF_Z,	0x04,	0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpermpd,	vperm_imm_avx2_insn,	1,	SUF_Z,	0x01,	0,	0,	ONLY_AVX,	CPU_AVX2,	0,	0
+vpermps,	vperm_var_avx2_insn,	1,	SUF_Z,	0x16,	0,	0,	ONLY_AVX,	CPU_AVX2,	0,	0
+vpermq,	vperm_imm_avx2_insn,	1,	SUF_Z,	0x00,	0,	0,	ONLY_AVX,	CPU_AVX2,	0,	0
 vpextrb,	pextrb_insn,	3,	SUF_Z,	0xC0,	0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
 vpextrd,	pextrd_insn,	1,	SUF_Z,	0xC0,	0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
 vpextrq,	pextrq_insn,	1,	SUF_Z,	0xC0,	0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
 vpextrw,	pextrw_insn,	7,	SUF_Z,	0xC0,	0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpgatherdd,	gather_32x_32y_insn,	2,	SUF_Z,	0x90,	0,	0,	ONLY_AVX,	CPU_AVX2,	0,	0
+vpgatherdq,	gather_64x_64x_insn,	2,	SUF_Z,	0x90,	0,	0,	ONLY_AVX,	CPU_AVX2,	0,	0
+vpgatherqd,	gather_32x_32y_128_insn,	2,	SUF_Z,	0x91,	0,	0,	ONLY_AVX,	CPU_AVX2,	0,	0
+vpgatherqq,	gather_64x_64y_insn,	2,	SUF_Z,	0x91,	0,	0,	ONLY_AVX,	CPU_AVX2,	0,	0
 vphaddbd,	vphaddsub_insn,	1,	SUF_Z,	0xC2,	0,	0,	0,	CPU_XOP,	0,	0
 vphaddbq,	vphaddsub_insn,	1,	SUF_Z,	0xC3,	0,	0,	0,	CPU_XOP,	0,	0
 vphaddbw,	vphaddsub_insn,	1,	SUF_Z,	0xC1,	0,	0,	0,	CPU_XOP,	0,	0
-vphaddd,	ssse3_insn,	3,	SUF_Z,	0x02,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vphaddd,	ssse3_insn,	5,	SUF_Z,	0x02,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
 vphadddq,	vphaddsub_insn,	1,	SUF_Z,	0xCB,	0,	0,	0,	CPU_XOP,	0,	0
-vphaddsw,	ssse3_insn,	3,	SUF_Z,	0x03,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vphaddsw,	ssse3_insn,	5,	SUF_Z,	0x03,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
 vphaddubd,	vphaddsub_insn,	1,	SUF_Z,	0xD2,	0,	0,	0,	CPU_XOP,	0,	0
 vphaddubq,	vphaddsub_insn,	1,	SUF_Z,	0xD3,	0,	0,	0,	CPU_XOP,	0,	0
 vphaddubw,	vphaddsub_insn,	1,	SUF_Z,	0xD1,	0,	0,	0,	CPU_XOP,	0,	0
 vphaddudq,	vphaddsub_insn,	1,	SUF_Z,	0xD8,	0,	0,	0,	CPU_XOP,	0,	0
 vphadduwd,	vphaddsub_insn,	1,	SUF_Z,	0xD6,	0,	0,	0,	CPU_XOP,	0,	0
 vphadduwq,	vphaddsub_insn,	1,	SUF_Z,	0xD7,	0,	0,	0,	CPU_XOP,	0,	0
-vphaddw,	ssse3_insn,	3,	SUF_Z,	0x01,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vphaddw,	ssse3_insn,	5,	SUF_Z,	0x01,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
 vphaddwd,	vphaddsub_insn,	1,	SUF_Z,	0xC6,	0,	0,	0,	CPU_XOP,	0,	0
 vphaddwq,	vphaddsub_insn,	1,	SUF_Z,	0xC7,	0,	0,	0,	CPU_XOP,	0,	0
 vphminposuw,	avx_ssse3_2op_insn,	1,	SUF_Z,	0x41,	0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
 vphsubbw,	vphaddsub_insn,	1,	SUF_Z,	0xE1,	0,	0,	0,	CPU_XOP,	0,	0
-vphsubd,	ssse3_insn,	3,	SUF_Z,	0x06,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vphsubd,	ssse3_insn,	5,	SUF_Z,	0x06,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
 vphsubdq,	vphaddsub_insn,	1,	SUF_Z,	0xE3,	0,	0,	0,	CPU_XOP,	0,	0
-vphsubsw,	ssse3_insn,	3,	SUF_Z,	0x07,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vphsubw,	ssse3_insn,	3,	SUF_Z,	0x05,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vphsubsw,	ssse3_insn,	5,	SUF_Z,	0x07,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vphsubw,	ssse3_insn,	5,	SUF_Z,	0x05,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
 vphsubwd,	vphaddsub_insn,	1,	SUF_Z,	0xE2,	0,	0,	0,	CPU_XOP,	0,	0
 vpinsrb,	pinsrb_insn,	4,	SUF_Z,	0xC0,	0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
 vpinsrd,	pinsrd_insn,	2,	SUF_Z,	0xC0,	0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
@@ -1250,47 +1286,49 @@ vpmacswd,	vpma_insn,	1,	SUF_Z,	0x96,	0,	0,	0,	CPU_XOP,	0,	0
 vpmacsww,	vpma_insn,	1,	SUF_Z,	0x95,	0,	0,	0,	CPU_XOP,	0,	0
 vpmadcsswd,	vpma_insn,	1,	SUF_Z,	0xA6,	0,	0,	0,	CPU_XOP,	0,	0
 vpmadcswd,	vpma_insn,	1,	SUF_Z,	0xB6,	0,	0,	0,	CPU_XOP,	0,	0
-vpmaddubsw,	ssse3_insn,	3,	SUF_Z,	0x04,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpmaddwd,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0xF5,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpmaxsb,	ssse3_insn,	3,	SUF_Z,	0x3C,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpmaxsd,	ssse3_insn,	3,	SUF_Z,	0x3D,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpmaxsw,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0xEE,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpmaxub,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0xDE,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpmaxud,	ssse3_insn,	3,	SUF_Z,	0x3F,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpmaxuw,	ssse3_insn,	3,	SUF_Z,	0x3E,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpminsb,	ssse3_insn,	3,	SUF_Z,	0x38,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpminsd,	ssse3_insn,	3,	SUF_Z,	0x39,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpminsw,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0xEA,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpminub,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0xDA,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpminud,	ssse3_insn,	3,	SUF_Z,	0x3B,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpminuw,	ssse3_insn,	3,	SUF_Z,	0x3A,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpmovmskb,	pmovmskb_insn,	4,	SUF_Z,	0xC0,	0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpmovsxbd,	sse4m32_insn,	2,	SUF_Z,	0x21,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpmovsxbq,	sse4m16_insn,	2,	SUF_Z,	0x22,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpmovsxbw,	sse4m64_insn,	2,	SUF_Z,	0x20,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpmovsxdq,	sse4m64_insn,	2,	SUF_Z,	0x25,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpmovsxwd,	sse4m64_insn,	2,	SUF_Z,	0x23,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpmovsxwq,	sse4m32_insn,	2,	SUF_Z,	0x24,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpmovzxbd,	sse4m32_insn,	2,	SUF_Z,	0x31,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpmovzxbq,	sse4m16_insn,	2,	SUF_Z,	0x32,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpmovzxbw,	sse4m64_insn,	2,	SUF_Z,	0x30,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpmovzxdq,	sse4m64_insn,	2,	SUF_Z,	0x35,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpmovzxwd,	sse4m64_insn,	2,	SUF_Z,	0x33,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpmovzxwq,	sse4m32_insn,	2,	SUF_Z,	0x34,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpmuldq,	ssse3_insn,	3,	SUF_Z,	0x28,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpmulhrsw,	ssse3_insn,	3,	SUF_Z,	0x0B,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpmulhuw,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0xE4,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpmulhw,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0xE5,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpmulld,	ssse3_insn,	3,	SUF_Z,	0x40,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpmullw,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0xD5,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpmuludq,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0xF4,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpor,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0xEB,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpmaddubsw,	ssse3_insn,	5,	SUF_Z,	0x04,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpmaddwd,	xmm_xmm128_256avx2_insn,	4,	SUF_Z,	0x66,	0xF5,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpmaskmovd,	vmaskmov_insn,	4,	SUF_Z,	0x8C,	0,	0,	ONLY_AVX,	CPU_AVX2,	0,	0
+vpmaskmovq,	vmaskmov_vexw1_avx2_insn,	4,	SUF_Z,	0x8C,	0,	0,	ONLY_AVX,	CPU_AVX2,	0,	0
+vpmaxsb,	ssse3_insn,	5,	SUF_Z,	0x3C,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpmaxsd,	ssse3_insn,	5,	SUF_Z,	0x3D,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpmaxsw,	xmm_xmm128_256avx2_insn,	4,	SUF_Z,	0x66,	0xEE,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpmaxub,	xmm_xmm128_256avx2_insn,	4,	SUF_Z,	0x66,	0xDE,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpmaxud,	ssse3_insn,	5,	SUF_Z,	0x3F,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpmaxuw,	ssse3_insn,	5,	SUF_Z,	0x3E,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpminsb,	ssse3_insn,	5,	SUF_Z,	0x38,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpminsd,	ssse3_insn,	5,	SUF_Z,	0x39,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpminsw,	xmm_xmm128_256avx2_insn,	4,	SUF_Z,	0x66,	0xEA,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpminub,	xmm_xmm128_256avx2_insn,	4,	SUF_Z,	0x66,	0xDA,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpminud,	ssse3_insn,	5,	SUF_Z,	0x3B,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpminuw,	ssse3_insn,	5,	SUF_Z,	0x3A,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpmovmskb,	pmovmskb_insn,	6,	SUF_Z,	0xC0,	0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpmovsxbd,	sse4m32_insn,	4,	SUF_Z,	0x21,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpmovsxbq,	sse4m16_insn,	4,	SUF_Z,	0x22,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpmovsxbw,	sse4m64_insn,	4,	SUF_Z,	0x20,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpmovsxdq,	sse4m64_insn,	4,	SUF_Z,	0x25,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpmovsxwd,	sse4m64_insn,	4,	SUF_Z,	0x23,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpmovsxwq,	sse4m32_insn,	4,	SUF_Z,	0x24,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpmovzxbd,	sse4m32_insn,	4,	SUF_Z,	0x31,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpmovzxbq,	sse4m16_insn,	4,	SUF_Z,	0x32,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpmovzxbw,	sse4m64_insn,	4,	SUF_Z,	0x30,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpmovzxdq,	sse4m64_insn,	4,	SUF_Z,	0x35,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpmovzxwd,	sse4m64_insn,	4,	SUF_Z,	0x33,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpmovzxwq,	sse4m32_insn,	4,	SUF_Z,	0x34,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpmuldq,	ssse3_insn,	5,	SUF_Z,	0x28,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpmulhrsw,	ssse3_insn,	5,	SUF_Z,	0x0B,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpmulhuw,	xmm_xmm128_256avx2_insn,	4,	SUF_Z,	0x66,	0xE4,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpmulhw,	xmm_xmm128_256avx2_insn,	4,	SUF_Z,	0x66,	0xE5,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpmulld,	ssse3_insn,	5,	SUF_Z,	0x40,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpmullw,	xmm_xmm128_256avx2_insn,	4,	SUF_Z,	0x66,	0xD5,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpmuludq,	xmm_xmm128_256avx2_insn,	4,	SUF_Z,	0x66,	0xF4,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpor,	xmm_xmm128_256avx2_insn,	4,	SUF_Z,	0x66,	0xEB,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
 vpperm,	vpperm_insn,	2,	SUF_Z,	0,	0,	0,	0,	CPU_XOP,	0,	0
 vprotb,	vprot_insn,	3,	SUF_Z,	0x00,	0,	0,	0,	CPU_XOP,	0,	0
 vprotd,	vprot_insn,	3,	SUF_Z,	0x02,	0,	0,	0,	CPU_XOP,	0,	0
 vprotq,	vprot_insn,	3,	SUF_Z,	0x03,	0,	0,	0,	CPU_XOP,	0,	0
 vprotw,	vprot_insn,	3,	SUF_Z,	0x01,	0,	0,	0,	CPU_XOP,	0,	0
-vpsadbw,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0xF6,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpsadbw,	xmm_xmm128_256avx2_insn,	4,	SUF_Z,	0x66,	0xF6,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
 vpshab,	amd_vpshift_insn,	2,	SUF_Z,	0x98,	0,	0,	0,	CPU_XOP,	0,	0
 vpshad,	amd_vpshift_insn,	2,	SUF_Z,	0x9A,	0,	0,	0,	CPU_XOP,	0,	0
 vpshaq,	amd_vpshift_insn,	2,	SUF_Z,	0x9B,	0,	0,	0,	CPU_XOP,	0,	0
@@ -1299,41 +1337,46 @@ vpshlb,	amd_vpshift_insn,	2,	SUF_Z,	0x94,	0,	0,	0,	CPU_XOP,	0,	0
 vpshld,	amd_vpshift_insn,	2,	SUF_Z,	0x96,	0,	0,	0,	CPU_XOP,	0,	0
 vpshlq,	amd_vpshift_insn,	2,	SUF_Z,	0x97,	0,	0,	0,	CPU_XOP,	0,	0
 vpshlw,	amd_vpshift_insn,	2,	SUF_Z,	0x95,	0,	0,	0,	CPU_XOP,	0,	0
-vpshufb,	ssse3_insn,	3,	SUF_Z,	0x00,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpshufd,	xmm_xmm128_imm_insn,	1,	SUF_Z,	0x66,	0x70,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpshufhw,	xmm_xmm128_imm_insn,	1,	SUF_Z,	0xF3,	0x70,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpshuflw,	xmm_xmm128_imm_insn,	1,	SUF_Z,	0xF2,	0x70,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpsignb,	ssse3_insn,	3,	SUF_Z,	0x08,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpsignd,	ssse3_insn,	3,	SUF_Z,	0x0A,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpsignw,	ssse3_insn,	3,	SUF_Z,	0x09,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpslld,	vpshift_insn,	4,	SUF_Z,	0xF2,	0x72,	0x06,	ONLY_AVX,	CPU_AVX,	0,	0
-vpslldq,	pslrldq_insn,	2,	SUF_Z,	0x07,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpsllq,	vpshift_insn,	4,	SUF_Z,	0xF3,	0x73,	0x06,	ONLY_AVX,	CPU_AVX,	0,	0
-vpsllw,	vpshift_insn,	4,	SUF_Z,	0xF1,	0x71,	0x06,	ONLY_AVX,	CPU_AVX,	0,	0
-vpsrad,	vpshift_insn,	4,	SUF_Z,	0xE2,	0x72,	0x04,	ONLY_AVX,	CPU_AVX,	0,	0
-vpsraw,	vpshift_insn,	4,	SUF_Z,	0xE1,	0x71,	0x04,	ONLY_AVX,	CPU_AVX,	0,	0
-vpsrld,	vpshift_insn,	4,	SUF_Z,	0xD2,	0x72,	0x02,	ONLY_AVX,	CPU_AVX,	0,	0
-vpsrldq,	pslrldq_insn,	2,	SUF_Z,	0x03,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpsrlq,	vpshift_insn,	4,	SUF_Z,	0xD3,	0x73,	0x02,	ONLY_AVX,	CPU_AVX,	0,	0
-vpsrlw,	vpshift_insn,	4,	SUF_Z,	0xD1,	0x71,	0x02,	ONLY_AVX,	CPU_AVX,	0,	0
-vpsubb,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0xF8,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpsubd,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0xFA,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpsubq,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0xFB,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpsubsb,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0xE8,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpsubsw,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0xE9,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpsubusb,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0xD8,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpsubusw,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0xD9,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpsubw,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0xF9,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpshufb,	ssse3_insn,	5,	SUF_Z,	0x00,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpshufd,	xmm_xmm128_imm_256avx2_insn,	2,	SUF_Z,	0x66,	0x70,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpshufhw,	xmm_xmm128_imm_256avx2_insn,	2,	SUF_Z,	0xF3,	0x70,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpshuflw,	xmm_xmm128_imm_256avx2_insn,	2,	SUF_Z,	0xF2,	0x70,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpsignb,	ssse3_insn,	5,	SUF_Z,	0x08,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpsignd,	ssse3_insn,	5,	SUF_Z,	0x0A,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpsignw,	ssse3_insn,	5,	SUF_Z,	0x09,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpslld,	vpshift_insn,	8,	SUF_Z,	0xF2,	0x72,	0x06,	ONLY_AVX,	CPU_AVX,	0,	0
+vpslldq,	pslrldq_insn,	4,	SUF_Z,	0x07,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpsllq,	vpshift_insn,	8,	SUF_Z,	0xF3,	0x73,	0x06,	ONLY_AVX,	CPU_AVX,	0,	0
+vpsllvd,	vpshiftv_vexw0_avx2_insn,	2,	SUF_Z,	0x47,	0,	0,	ONLY_AVX,	CPU_AVX2,	0,	0
+vpsllvq,	vpshiftv_vexw1_avx2_insn,	2,	SUF_Z,	0x47,	0,	0,	ONLY_AVX,	CPU_AVX2,	0,	0
+vpsllw,	vpshift_insn,	8,	SUF_Z,	0xF1,	0x71,	0x06,	ONLY_AVX,	CPU_AVX,	0,	0
+vpsrad,	vpshift_insn,	8,	SUF_Z,	0xE2,	0x72,	0x04,	ONLY_AVX,	CPU_AVX,	0,	0
+vpsravd,	vpshiftv_vexw0_avx2_insn,	2,	SUF_Z,	0x46,	0,	0,	ONLY_AVX,	CPU_AVX2,	0,	0
+vpsraw,	vpshift_insn,	8,	SUF_Z,	0xE1,	0x71,	0x04,	ONLY_AVX,	CPU_AVX,	0,	0
+vpsrld,	vpshift_insn,	8,	SUF_Z,	0xD2,	0x72,	0x02,	ONLY_AVX,	CPU_AVX,	0,	0
+vpsrldq,	pslrldq_insn,	4,	SUF_Z,	0x03,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpsrlq,	vpshift_insn,	8,	SUF_Z,	0xD3,	0x73,	0x02,	ONLY_AVX,	CPU_AVX,	0,	0
+vpsrlvd,	vpshiftv_vexw0_avx2_insn,	2,	SUF_Z,	0x45,	0,	0,	ONLY_AVX,	CPU_AVX2,	0,	0
+vpsrlvq,	vpshiftv_vexw1_avx2_insn,	2,	SUF_Z,	0x45,	0,	0,	ONLY_AVX,	CPU_AVX2,	0,	0
+vpsrlw,	vpshift_insn,	8,	SUF_Z,	0xD1,	0x71,	0x02,	ONLY_AVX,	CPU_AVX,	0,	0
+vpsubb,	xmm_xmm128_256avx2_insn,	4,	SUF_Z,	0x66,	0xF8,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpsubd,	xmm_xmm128_256avx2_insn,	4,	SUF_Z,	0x66,	0xFA,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpsubq,	xmm_xmm128_256avx2_insn,	4,	SUF_Z,	0x66,	0xFB,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpsubsb,	xmm_xmm128_256avx2_insn,	4,	SUF_Z,	0x66,	0xE8,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpsubsw,	xmm_xmm128_256avx2_insn,	4,	SUF_Z,	0x66,	0xE9,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpsubusb,	xmm_xmm128_256avx2_insn,	4,	SUF_Z,	0x66,	0xD8,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpsubusw,	xmm_xmm128_256avx2_insn,	4,	SUF_Z,	0x66,	0xD9,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpsubw,	xmm_xmm128_256avx2_insn,	4,	SUF_Z,	0x66,	0xF9,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
 vptest,	sse4_insn,	2,	SUF_Z,	0x17,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpunpckhbw,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0x68,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpunpckhdq,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0x6A,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpunpckhqdq,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0x6D,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpunpckhwd,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0x69,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpunpcklbw,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0x60,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpunpckldq,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0x62,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpunpcklqdq,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0x6C,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpunpcklwd,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0x61,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vpxor,	xmm_xmm128_insn,	2,	SUF_Z,	0x66,	0xEF,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpunpckhbw,	xmm_xmm128_256avx2_insn,	4,	SUF_Z,	0x66,	0x68,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpunpckhdq,	xmm_xmm128_256avx2_insn,	4,	SUF_Z,	0x66,	0x6A,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpunpckhqdq,	xmm_xmm128_256avx2_insn,	4,	SUF_Z,	0x66,	0x6D,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpunpckhwd,	xmm_xmm128_256avx2_insn,	4,	SUF_Z,	0x66,	0x69,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpunpcklbw,	xmm_xmm128_256avx2_insn,	4,	SUF_Z,	0x66,	0x60,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpunpckldq,	xmm_xmm128_256avx2_insn,	4,	SUF_Z,	0x66,	0x62,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpunpcklqdq,	xmm_xmm128_256avx2_insn,	4,	SUF_Z,	0x66,	0x6C,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpunpcklwd,	xmm_xmm128_256avx2_insn,	4,	SUF_Z,	0x66,	0x61,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vpxor,	xmm_xmm128_256avx2_insn,	4,	SUF_Z,	0x66,	0xEF,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
 vrcpps,	avx_xmm_xmm128_insn,	2,	SUF_Z,	0x00,	0x53,	0,	ONLY_AVX,	CPU_AVX,	0,	0
 vrcpss,	xmm_xmm32_insn,	4,	SUF_Z,	0xF3,	0x53,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
 vroundpd,	avx_sse4imm_insn,	3,	SUF_Z,	0x09,	0,	0,	ONLY_AVX,	CPU_SSE41,	0,	0
@@ -1349,20 +1392,20 @@ vsqrtps,	avx_xmm_xmm128_insn,	2,	SUF_Z,	0x00,	0x51,	0,	ONLY_AVX,	CPU_AVX,	0,	0
 vsqrtsd,	xmm_xmm64_insn,	4,	SUF_Z,	0xF2,	0x51,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
 vsqrtss,	xmm_xmm32_insn,	4,	SUF_Z,	0xF3,	0x51,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
 vstmxcsr,	ldstmxcsr_insn,	1,	SUF_Z,	0x03,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vsubpd,	xmm_xmm128_256_insn,	3,	SUF_Z,	0x66,	0x5C,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vsubps,	xmm_xmm128_256_insn,	3,	SUF_Z,	0x00,	0x5C,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vsubpd,	xmm_xmm128_256_insn,	4,	SUF_Z,	0x66,	0x5C,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vsubps,	xmm_xmm128_256_insn,	4,	SUF_Z,	0x00,	0x5C,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
 vsubsd,	xmm_xmm64_insn,	4,	SUF_Z,	0xF2,	0x5C,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
 vsubss,	xmm_xmm32_insn,	4,	SUF_Z,	0xF3,	0x5C,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
 vtestpd,	sse4_insn,	2,	SUF_Z,	0x0F,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
 vtestps,	sse4_insn,	2,	SUF_Z,	0x0E,	0xC0,	0,	ONLY_AVX,	CPU_AVX,	0,	0
 vucomisd,	avx_xmm_xmm64_insn,	2,	SUF_Z,	0x66,	0x2E,	0,	ONLY_AVX,	CPU_AVX,	0,	0
 vucomiss,	avx_xmm_xmm32_insn,	2,	SUF_Z,	0x00,	0x2E,	0,	ONLY_AVX,	CPU_AVX,	0,	0
-vunpckhpd,	xmm_xmm128_256_insn,	3,	SUF_Z,	0x66,	0x15,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vunpckhps,	xmm_xmm128_256_insn,	3,	SUF_Z,	0x00,	0x15,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vunpcklpd,	xmm_xmm128_256_insn,	3,	SUF_Z,	0x66,	0x14,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vunpcklps,	xmm_xmm128_256_insn,	3,	SUF_Z,	0x00,	0x14,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vxorpd,	xmm_xmm128_256_insn,	3,	SUF_Z,	0x66,	0x57,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
-vxorps,	xmm_xmm128_256_insn,	3,	SUF_Z,	0x00,	0x57,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vunpckhpd,	xmm_xmm128_256_insn,	4,	SUF_Z,	0x66,	0x15,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vunpckhps,	xmm_xmm128_256_insn,	4,	SUF_Z,	0x00,	0x15,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vunpcklpd,	xmm_xmm128_256_insn,	4,	SUF_Z,	0x66,	0x14,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vunpcklps,	xmm_xmm128_256_insn,	4,	SUF_Z,	0x00,	0x14,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vxorpd,	xmm_xmm128_256_insn,	4,	SUF_Z,	0x66,	0x57,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
+vxorps,	xmm_xmm128_256_insn,	4,	SUF_Z,	0x00,	0x57,	0xC0,	ONLY_AVX,	CPU_AVX,	0,	0
 vzeroall,	vzero_insn,	1,	SUF_Z,	0xC4,	0,	0,	0,	CPU_AVX,	0,	0
 vzeroupper,	vzero_insn,	1,	SUF_Z,	0xC0,	0,	0,	0,	CPU_AVX,	0,	0
 wait,	onebyte_insn,	1,	SUF_Z,	0x9B,	0,	0,	0,	0,	0,	0
diff --git a/x86insns.c b/x86insns.c
index 8c8eb7f..5ae0a9f 100644
--- a/x86insns.c
+++ b/x86insns.c
@@ -1,4 +1,4 @@
-/* Generated by gen_x86_insn.py r2346, do not edit */
+/* Generated by gen_x86_insn.py rHEAD, do not edit */
 static const x86_info_operand insn_operands[] = {
    {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
     {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
@@ -10,6 +10,18 @@ static const x86_info_operand insn_operands[] = {
     {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
     {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
     {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
+    {OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
+    {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
+    {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
+    {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
+    {OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
+    {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEXImmSrc, OPAP_None},
+    {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
+    {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
+    {OPT_SIMDRM, OPS_256, 1, 0, OPTM_None, OPA_EA, OPAP_None},
+    {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_VEXImmSrc, OPAP_None},
+    {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
+    {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
     {OPT_SIMDRM, OPS_256, 1, 0, OPTM_None, OPA_EA, OPAP_None},
     {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
     {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
@@ -26,10 +38,6 @@ static const x86_info_operand insn_operands[] = {
     {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
     {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
     {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
-    {OPT_RM, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
-    {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
-    {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
-    {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
     {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_EA, OPAP_None},
     {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEXImmSrc, OPAP_None},
     {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
@@ -56,18 +64,18 @@ static const x86_info_operand insn_operands[] = {
     {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
     {OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
     {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
-    {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
-    {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
-    {OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
+    {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
+    {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_EA, OPAP_None},
+    {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_EA, OPAP_None},
     {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
     {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
     {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
-    {OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
     {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEXImmSrc, OPAP_None},
+    {OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
     {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
     {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
-    {OPT_SIMDRM, OPS_256, 1, 0, OPTM_None, OPA_EA, OPAP_None},
     {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_VEXImmSrc, OPAP_None},
+    {OPT_SIMDRM, OPS_256, 1, 0, OPTM_None, OPA_EA, OPAP_None},
     {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
     {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
     {OPT_Mem, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
@@ -82,15 +90,7 @@ static const x86_info_operand insn_operands[] = {
     {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
     {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
     {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
-    {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEXImmSrc, OPAP_None},
-    {OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
-    {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
-    {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
-    {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_VEXImmSrc, OPAP_None},
-    {OPT_SIMDRM, OPS_256, 1, 0, OPTM_None, OPA_EA, OPAP_None},
-    {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
-    {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_EA, OPAP_None},
-    {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_EA, OPAP_None},
+    {OPT_RM, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
     {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
     {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_SpareVEX, OPAP_None},
     {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_EA, OPAP_None},
@@ -134,15 +134,30 @@ static const x86_info_operand insn_operands[] = {
     {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_SpareVEX, OPAP_None},
     {OPT_Mem, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_None},
     {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
-    {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_SpareVEX, OPAP_None},
+    {OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
     {OPT_RM, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
     {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
+    {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
+    {OPT_RM, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
+    {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
+    {OPT_SIMDReg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
+    {OPT_SIMDRM, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
+    {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
     {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_SpareVEX, OPAP_None},
     {OPT_Mem, OPS_8, 1, 0, OPTM_None, OPA_EA, OPAP_None},
     {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
     {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_SpareVEX, OPAP_None},
     {OPT_Mem, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
     {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
+    {OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
+    {OPT_RM, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
+    {OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
+    {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
+    {OPT_RM, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
+    {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
+    {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
+    {OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
+    {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
     {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_SpareVEX, OPAP_None},
     {OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
     {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
@@ -182,11 +197,11 @@ static const x86_info_operand insn_operands[] = {
     {OPT_Mem, OPS_8, 1, 0, OPTM_None, OPA_EA, OPAP_None},
     {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
     {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
-    {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
-    {OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
-    {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
-    {OPT_SIMDReg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
-    {OPT_SIMDRM, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
+    {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_SpareVEX, OPAP_None},
+    {OPT_SIMDRM, OPS_256, 1, 0, OPTM_None, OPA_EA, OPAP_None},
+    {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
+    {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
+    {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_EA, OPAP_None},
     {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
     {OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
     {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
@@ -206,12 +221,39 @@ static const x86_info_operand insn_operands[] = {
     {OPT_Mem, OPS_128, 0, 0, OPTM_None, OPA_EA, OPAP_None},
     {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
     {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
+    {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
+    {OPT_MemXMMIndex, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
+    {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
+    {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
+    {OPT_MemXMMIndex, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
+    {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
     {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_SpareVEX, OPAP_None},
     {OPT_RM, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
     {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
+    {OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
+    {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
+    {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
+    {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_SpareVEX, OPAP_None},
+    {OPT_RM, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
+    {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
     {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
     {OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
     {OPT_XMM0, OPS_128, 0, 0, OPTM_None, OPA_None, OPAP_None},
+    {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
+    {OPT_MemXMMIndex, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
+    {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
+    {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
+    {OPT_MemYMMIndex, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
+    {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
+    {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
+    {OPT_MemYMMIndex, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
+    {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
+    {OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
+    {OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
+    {OPT_RM, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
+    {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
+    {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
+    {OPT_RM, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
     {OPT_RM, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_None},
     {OPT_Reg, OPS_16, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
     {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
@@ -230,9 +272,9 @@ static const x86_info_operand insn_operands[] = {
     {OPT_RM, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
     {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
     {OPT_Creg, OPS_8, 0, 0, OPTM_None, OPA_None, OPAP_None},
-    {OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
     {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
-    {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
+    {OPT_MemYMMIndex, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
+    {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
     {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
     {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
     {OPT_RM, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None},
@@ -401,11 +443,23 @@ static const x86_info_operand insn_operands[] = {
     {OPT_SIMDReg, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None},
     {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
     {OPT_Mem, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_None},
+    {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
+    {OPT_Mem, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
     {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
     {OPT_Mem, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
     {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
     {OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
     {OPT_Reg, OPS_16, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
+    {OPT_Reg, OPS_16, 0, 0, OPTM_None, OPA_EA, OPAP_None},
+    {OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
+    {OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None},
+    {OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
+    {OPT_RM, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_None},
+    {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
+    {OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None},
+    {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
+    {OPT_RM, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_None},
+    {OPT_Reg, OPS_16, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
     {OPT_Mem, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_None},
     {OPT_Mem, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_None},
     {OPT_Reg, OPS_16, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
@@ -419,12 +473,12 @@ static const x86_info_operand insn_operands[] = {
     {OPT_RM, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None},
     {OPT_Areg, OPS_64, 0, 0, OPTM_None, OPA_None, OPAP_None},
     {OPT_RM, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None},
+    {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
+    {OPT_Mem, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
     {OPT_Imm, OPS_Any, 0, 0, OPTM_None, OPA_JmpRel, OPAP_None},
     {OPT_Creg, OPS_32, 0, 0, OPTM_None, OPA_AdSizeR, OPAP_None},
     {OPT_Imm, OPS_Any, 0, 0, OPTM_Short, OPA_JmpRel, OPAP_None},
     {OPT_Creg, OPS_32, 0, 0, OPTM_None, OPA_AdSizeR, OPAP_None},
-    {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
-    {OPT_Mem, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
     {OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
     {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
     {OPT_SIMDRM, OPS_256, 1, 0, OPTM_None, OPA_EA, OPAP_None},
@@ -437,8 +491,6 @@ static const x86_info_operand insn_operands[] = {
     {OPT_Creg, OPS_16, 0, 0, OPTM_None, OPA_AdSizeR, OPAP_None},
     {OPT_Imm, OPS_Any, 0, 0, OPTM_Short, OPA_JmpRel, OPAP_None},
     {OPT_Creg, OPS_16, 0, 0, OPTM_None, OPA_AdSizeR, OPAP_None},
-    {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
-    {OPT_Mem, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
     {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
     {OPT_Areg, OPS_8, 0, 0, OPTM_None, OPA_None, OPAP_None},
     {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
@@ -451,8 +503,12 @@ static const x86_info_operand insn_operands[] = {
     {OPT_Areg, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None},
     {OPT_Dreg, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None},
     {OPT_Areg, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None},
+    {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
+    {OPT_Mem, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
     {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_EAVEX, OPAP_None},
     {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
+    {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_EAVEX, OPAP_None},
+    {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
     {OPT_MemrAX, OPS_Any, 0, 0, OPTM_None, OPA_AdSizeEA, OPAP_None},
     {OPT_Creg, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None},
     {OPT_Areg, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None},
@@ -481,6 +537,14 @@ static const x86_info_operand insn_operands[] = {
     {OPT_RM, OPS_16, 0, 0, OPTM_None, OPA_EA, OPAP_None},
     {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
     {OPT_RM, OPS_8, 0, 0, OPTM_None, OPA_EA, OPAP_None},
+    {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
+    {OPT_SIMDReg, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
+    {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
+    {OPT_SIMDReg, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
+    {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
+    {OPT_RM, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_None},
+    {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
+    {OPT_RM, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_None},
     {OPT_RM, OPS_8, 0, 0, OPTM_None, OPA_EA, OPAP_None},
     {OPT_Creg, OPS_8, 0, 0, OPTM_None, OPA_None, OPAP_None},
     {OPT_RM, OPS_8, 0, 0, OPTM_None, OPA_EA, OPAP_None},
@@ -529,8 +593,8 @@ static const x86_info_operand insn_operands[] = {
     {OPT_Imm, OPS_32, 1, 0, OPTM_None, OPA_Imm, OPAP_SImm8},
     {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
     {OPT_Mem, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
-    {OPT_Mem, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
-    {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
+    {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
+    {OPT_Mem, OPS_256, 1, 0, OPTM_None, OPA_EA, OPAP_None},
     {OPT_Mem, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
     {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
     {OPT_Mem, OPS_256, 1, 0, OPTM_None, OPA_EA, OPAP_None},
@@ -543,18 +607,18 @@ static const x86_info_operand insn_operands[] = {
     {OPT_SIMDRM, OPS_128, 0, 0, OPTM_None, OPA_EA, OPAP_None},
     {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
     {OPT_SIMDRM, OPS_256, 0, 0, OPTM_None, OPA_EA, OPAP_None},
+    {OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
+    {OPT_Mem, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
+    {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
+    {OPT_Mem, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
     {OPT_SIMDReg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
     {OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
     {OPT_Areg, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None},
     {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
-    {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
-    {OPT_Mem, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
     {OPT_Mem, OPS_80, 1, 0, OPTM_None, OPA_EA, OPAP_None},
     {OPT_SegReg, OPS_16, 1, 0, OPTM_None, OPA_Spare, OPAP_None},
-    {OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
-    {OPT_Mem, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
-    {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
-    {OPT_Mem, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
+    {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
+    {OPT_RM, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
     {OPT_Areg, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None},
     {OPT_Imm, OPS_16, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
     {OPT_Areg, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None},
@@ -565,10 +629,16 @@ static const x86_info_operand insn_operands[] = {
     {OPT_Mem, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None},
     {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
     {OPT_Mem, OPS_128, 0, 0, OPTM_None, OPA_EA, OPAP_None},
+    {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
+    {OPT_RM, OPS_8, 1, 0, OPTM_None, OPA_EA, OPAP_None},
     {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
-    {OPT_Mem, OPS_256, 1, 0, OPTM_None, OPA_EA, OPAP_None},
+    {OPT_RM, OPS_8, 1, 0, OPTM_None, OPA_EA, OPAP_None},
+    {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_SpareVEX, OPAP_None},
+    {OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
     {OPT_SIMDReg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
     {OPT_SIMDReg, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None},
+    {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
+    {OPT_RM, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
     {OPT_Imm, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_A16},
     {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
     {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
@@ -581,6 +651,8 @@ static const x86_info_operand insn_operands[] = {
     {OPT_Mem, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None},
     {OPT_MemEAX, OPS_Any, 0, 0, OPTM_None, OPA_None, OPAP_None},
     {OPT_Mem, OPS_80, 0, 0, OPTM_None, OPA_EA, OPAP_None},
+    {OPT_Reg, OPS_BITS, 0, 0, OPTM_None, OPA_Op0Add, OPAP_None},
+    {OPT_RM, OPS_BITS, 0, 0, OPTM_None, OPA_EA, OPAP_None},
     {OPT_SS, OPS_Any, 0, 0, OPTM_None, OPA_None, OPAP_None},
     {OPT_SS, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None},
     {OPT_SS, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None},
@@ -657,304 +729,309 @@ static const x86_insn_info threebyte_insn[] = {
 };
 
 static const x86_insn_info onebytemem_insn[] = {
-   { SUF_L|SUF_Q|SUF_S|SUF_Z, 0, 0, 0, 0, {MOD_SpAdd, MOD_Op0Add, 0}, 0, 0, 0, 1, {0x00, 0, 0}, 0, 1, 596 }
+   { SUF_L|SUF_Q|SUF_S|SUF_Z, 0, 0, 0, 0, {MOD_SpAdd, MOD_Op0Add, 0}, 0, 0, 0, 1, {0x00, 0, 0}, 0, 1, 668 }
 };
 
 static const x86_insn_info twobytemem_insn[] = {
-   { SUF_L|SUF_Q|SUF_S|SUF_W|SUF_Z, 0, 0, 0, 0, {MOD_SpAdd, MOD_Op0Add, MOD_Op1Add}, 0, 0, 0, 2, {0x00, 0x00, 0}, 0, 1, 470 }
+   { SUF_L|SUF_Q|SUF_S|SUF_W|SUF_Z, 0, 0, 0, 0, {MOD_SpAdd, MOD_Op0Add, MOD_Op1Add}, 0, 0, 0, 2, {0x00, 0x00, 0}, 0, 1, 526 }
 };
 
 static const x86_insn_info mov_insn[] = {
-   { SUF_B|SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xA0, 0, 0}, 0, 2, 317 },
-    { SUF_W|SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xA1, 0, 0}, 0, 2, 319 },
-    { SUF_L|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xA1, 0, 0}, 0, 2, 321 },
-    { SUF_B|SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xA2, 0, 0}, 0, 2, 323 },
-    { SUF_W|SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xA3, 0, 0}, 0, 2, 325 },
-    { SUF_L|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xA3, 0, 0}, 0, 2, 327 },
-    { SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xA0, 0, 0}, 0, 2, 293 },
-    { SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xA1, 0, 0}, 0, 2, 295 },
-    { SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xA1, 0, 0}, 0, 2, 297 },
-    { SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xA1, 0, 0}, 0, 2, 299 },
-    { SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xA2, 0, 0}, 0, 2, 301 },
-    { SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xA3, 0, 0}, 0, 2, 303 },
-    { SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xA3, 0, 0}, 0, 2, 305 },
-    { SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xA3, 0, 0}, 0, 2, 307 },
-    { SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x88, 0xA2, 0}, 0, 2, 329 },
-    { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x89, 0xA3, 0}, 0, 2, 331 },
-    { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x89, 0xA3, 0}, 0, 2, 333 },
-    { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x89, 0xA3, 0}, 0, 2, 335 },
-    { SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x88, 0, 0}, 0, 2, 275 },
-    { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x89, 0, 0}, 0, 2, 212 },
-    { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x89, 0, 0}, 0, 2, 218 },
-    { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x89, 0, 0}, 0, 2, 224 },
-    { SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x8A, 0xA0, 0}, 0, 2, 337 },
-    { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x8B, 0xA1, 0}, 0, 2, 339 },
-    { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x8B, 0xA1, 0}, 0, 2, 341 },
-    { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x8B, 0xA1, 0}, 0, 2, 343 },
-    { SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x8A, 0, 0}, 0, 2, 277 },
+   { SUF_B|SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xA0, 0, 0}, 0, 2, 359 },
+    { SUF_W|SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xA1, 0, 0}, 0, 2, 361 },
+    { SUF_L|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xA1, 0, 0}, 0, 2, 363 },
+    { SUF_B|SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xA2, 0, 0}, 0, 2, 365 },
+    { SUF_W|SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xA3, 0, 0}, 0, 2, 367 },
+    { SUF_L|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xA3, 0, 0}, 0, 2, 369 },
+    { SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xA0, 0, 0}, 0, 2, 335 },
+    { SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xA1, 0, 0}, 0, 2, 337 },
+    { SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xA1, 0, 0}, 0, 2, 339 },
+    { SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xA1, 0, 0}, 0, 2, 341 },
+    { SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xA2, 0, 0}, 0, 2, 343 },
+    { SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xA3, 0, 0}, 0, 2, 345 },
+    { SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xA3, 0, 0}, 0, 2, 347 },
+    { SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xA3, 0, 0}, 0, 2, 349 },
+    { SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x88, 0xA2, 0}, 0, 2, 371 },
+    { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x89, 0xA3, 0}, 0, 2, 373 },
+    { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x89, 0xA3, 0}, 0, 2, 375 },
+    { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x89, 0xA3, 0}, 0, 2, 377 },
+    { SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x88, 0, 0}, 0, 2, 317 },
+    { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x89, 0, 0}, 0, 2, 254 },
+    { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x89, 0, 0}, 0, 2, 260 },
+    { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x89, 0, 0}, 0, 2, 266 },
+    { SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x8A, 0xA0, 0}, 0, 2, 379 },
+    { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x8B, 0xA1, 0}, 0, 2, 381 },
+    { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x8B, 0xA1, 0}, 0, 2, 383 },
+    { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x8B, 0xA1, 0}, 0, 2, 385 },
+    { SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x8A, 0, 0}, 0, 2, 319 },
     { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x8B, 0, 0}, 0, 2, 98 },
     { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x8B, 0, 0}, 0, 2, 101 },
     { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x8B, 0, 0}, 0, 2, 104 },
-    { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x8C, 0, 0}, 0, 2, 345 },
-    { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x8C, 0, 0}, 0, 2, 347 },
-    { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x8C, 0, 0}, 0, 2, 349 },
-    { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x8C, 0, 0}, 0, 2, 351 },
-    { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x8E, 0, 0}, 0, 2, 353 },
-    { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x8E, 0, 0}, 0, 2, 348 },
-    { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x8E, 0, 0}, 0, 2, 350 },
-    { SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xB0, 0, 0}, 0, 2, 355 },
-    { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xB8, 0, 0}, 0, 2, 357 },
-    { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xB8, 0, 0}, 0, 2, 359 },
-    { GAS_ILLEGAL|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xB8, 0, 0}, 0, 2, 361 },
-    { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xB8, 0xC7, 0}, 0, 2, 363 },
-    { SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xC6, 0, 0}, 0, 2, 365 },
-    { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xC7, 0, 0}, 0, 2, 367 },
-    { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xC7, 0, 0}, 0, 2, 369 },
-    { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xC7, 0, 0}, 0, 2, 371 },
-    { SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xC6, 0, 0}, 0, 2, 373 },
-    { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xC7, 0, 0}, 0, 2, 375 },
-    { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xC7, 0, 0}, 0, 2, 377 },
-    { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xC7, 0, 0}, 0, 2, 379 },
-    { SUF_L|SUF_Z, NOT_64, CPU_586, CPU_Priv, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x22, 0}, 0, 2, 381 },
-    { SUF_L|SUF_Z, NOT_64, CPU_386, CPU_Priv, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x22, 0}, 0, 2, 383 },
-    { SUF_Q|SUF_Z, ONLY_64, CPU_Priv, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x22, 0}, 0, 2, 385 },
-    { SUF_L|SUF_Z, NOT_64, CPU_586, CPU_Priv, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x20, 0}, 0, 2, 387 },
-    { SUF_L|SUF_Z, NOT_64, CPU_386, CPU_Priv, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x20, 0}, 0, 2, 382 },
-    { SUF_Q|SUF_Z, ONLY_64, CPU_Priv, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x20, 0}, 0, 2, 389 },
-    { SUF_L|SUF_Z, NOT_64, CPU_386, CPU_Priv, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x23, 0}, 0, 2, 391 },
-    { SUF_Q|SUF_Z, ONLY_64, CPU_Priv, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x23, 0}, 0, 2, 393 },
-    { SUF_L|SUF_Z, NOT_64, CPU_386, CPU_Priv, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x21, 0}, 0, 2, 392 },
-    { SUF_Q|SUF_Z, ONLY_64, CPU_Priv, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x21, 0}, 0, 2, 395 },
-    { GAS_ONLY|SUF_Q|SUF_Z, 0, CPU_MMX, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x6F, 0}, 0, 2, 185 },
-    { GAS_ONLY|SUF_Q|SUF_Z, ONLY_64, CPU_MMX, 0, 0, {0, 0, 0}, 64, 0, 0, 2, {0x0F, 0x6E, 0}, 0, 2, 247 },
-    { GAS_ONLY|SUF_Q|SUF_Z, 0, CPU_MMX, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x7F, 0}, 0, 2, 283 },
-    { GAS_ONLY|SUF_Q|SUF_Z, ONLY_64, CPU_MMX, 0, 0, {0, 0, 0}, 64, 0, 0, 2, {0x0F, 0x7E, 0}, 0, 2, 249 },
-    { GAS_ONLY|SUF_Q|SUF_Z, 0, CPU_SSE2, 0, 0, {0, 0, 0}, 0, 0, 0xF3, 2, {0x0F, 0x7E, 0}, 0, 2, 88 },
-    { GAS_ONLY|SUF_Q|SUF_Z, 0, CPU_SSE2, 0, 0, {0, 0, 0}, 0, 0, 0xF3, 2, {0x0F, 0x7E, 0}, 0, 2, 285 },
-    { GAS_ONLY|SUF_Q|SUF_Z, ONLY_64, CPU_SSE2, 0, 0, {0, 0, 0}, 64, 0, 0x66, 2, {0x0F, 0x6E, 0}, 0, 2, 253 },
-    { GAS_ONLY|SUF_Q|SUF_Z, 0, CPU_SSE2, 0, 0, {0, 0, 0}, 0, 0, 0x66, 2, {0x0F, 0xD6, 0}, 0, 2, 287 },
-    { GAS_ONLY|SUF_Q|SUF_Z, ONLY_64, CPU_SSE2, 0, 0, {0, 0, 0}, 64, 0, 0x66, 2, {0x0F, 0x7E, 0}, 0, 2, 167 }
+    { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x8C, 0, 0}, 0, 2, 387 },
+    { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x8C, 0, 0}, 0, 2, 389 },
+    { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x8C, 0, 0}, 0, 2, 391 },
+    { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x8C, 0, 0}, 0, 2, 393 },
+    { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x8E, 0, 0}, 0, 2, 395 },
+    { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x8E, 0, 0}, 0, 2, 390 },
+    { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x8E, 0, 0}, 0, 2, 392 },
+    { SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xB0, 0, 0}, 0, 2, 397 },
+    { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xB8, 0, 0}, 0, 2, 399 },
+    { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xB8, 0, 0}, 0, 2, 401 },
+    { GAS_ILLEGAL|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xB8, 0, 0}, 0, 2, 403 },
+    { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xB8, 0xC7, 0}, 0, 2, 405 },
+    { SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xC6, 0, 0}, 0, 2, 407 },
+    { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xC7, 0, 0}, 0, 2, 409 },
+    { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xC7, 0, 0}, 0, 2, 411 },
+    { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xC7, 0, 0}, 0, 2, 413 },
+    { SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xC6, 0, 0}, 0, 2, 415 },
+    { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xC7, 0, 0}, 0, 2, 417 },
+    { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xC7, 0, 0}, 0, 2, 419 },
+    { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xC7, 0, 0}, 0, 2, 421 },
+    { SUF_L|SUF_Z, NOT_64, CPU_586, CPU_Priv, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x22, 0}, 0, 2, 423 },
+    { SUF_L|SUF_Z, NOT_64, CPU_386, CPU_Priv, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x22, 0}, 0, 2, 425 },
+    { SUF_Q|SUF_Z, ONLY_64, CPU_Priv, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x22, 0}, 0, 2, 427 },
+    { SUF_L|SUF_Z, NOT_64, CPU_586, CPU_Priv, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x20, 0}, 0, 2, 429 },
+    { SUF_L|SUF_Z, NOT_64, CPU_386, CPU_Priv, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x20, 0}, 0, 2, 424 },
+    { SUF_Q|SUF_Z, ONLY_64, CPU_Priv, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x20, 0}, 0, 2, 431 },
+    { SUF_L|SUF_Z, NOT_64, CPU_386, CPU_Priv, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x23, 0}, 0, 2, 433 },
+    { SUF_Q|SUF_Z, ONLY_64, CPU_Priv, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x23, 0}, 0, 2, 435 },
+    { SUF_L|SUF_Z, NOT_64, CPU_386, CPU_Priv, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x21, 0}, 0, 2, 434 },
+    { SUF_Q|SUF_Z, ONLY_64, CPU_Priv, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x21, 0}, 0, 2, 437 },
+    { GAS_ONLY|SUF_Q|SUF_Z, 0, CPU_MMX, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x6F, 0}, 0, 2, 140 },
+    { GAS_ONLY|SUF_Q|SUF_Z, ONLY_64, CPU_MMX, 0, 0, {0, 0, 0}, 64, 0, 0, 2, {0x0F, 0x6E, 0}, 0, 2, 289 },
+    { GAS_ONLY|SUF_Q|SUF_Z, 0, CPU_MMX, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x7F, 0}, 0, 2, 325 },
+    { GAS_ONLY|SUF_Q|SUF_Z, ONLY_64, CPU_MMX, 0, 0, {0, 0, 0}, 64, 0, 0, 2, {0x0F, 0x7E, 0}, 0, 2, 291 },
+    { GAS_ONLY|SUF_Q|SUF_Z, 0, CPU_SSE2, 0, 0, {0, 0, 0}, 0, 0, 0xF3, 2, {0x0F, 0x7E, 0}, 0, 2, 64 },
+    { GAS_ONLY|SUF_Q|SUF_Z, 0, CPU_SSE2, 0, 0, {0, 0, 0}, 0, 0, 0xF3, 2, {0x0F, 0x7E, 0}, 0, 2, 327 },
+    { GAS_ONLY|SUF_Q|SUF_Z, ONLY_64, CPU_SSE2, 0, 0, {0, 0, 0}, 64, 0, 0x66, 2, {0x0F, 0x6E, 0}, 0, 2, 295 },
+    { GAS_ONLY|SUF_Q|SUF_Z, 0, CPU_SSE2, 0, 0, {0, 0, 0}, 0, 0, 0x66, 2, {0x0F, 0xD6, 0}, 0, 2, 329 },
+    { GAS_ONLY|SUF_Q|SUF_Z, ONLY_64, CPU_SSE2, 0, 0, {0, 0, 0}, 64, 0, 0x66, 2, {0x0F, 0x7E, 0}, 0, 2, 182 }
 };
 
 static const x86_insn_info movabs_insn[] = {
-   { SUF_B|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xA0, 0, 0}, 0, 2, 293 },
-    { SUF_W|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xA1, 0, 0}, 0, 2, 295 },
-    { SUF_L|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xA1, 0, 0}, 0, 2, 297 },
-    { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xA1, 0, 0}, 0, 2, 299 },
-    { SUF_B|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xA2, 0, 0}, 0, 2, 301 },
-    { SUF_W|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xA3, 0, 0}, 0, 2, 303 },
-    { SUF_L|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xA3, 0, 0}, 0, 2, 305 },
-    { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xA3, 0, 0}, 0, 2, 307 },
-    { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xB8, 0, 0}, 0, 2, 309 }
+   { SUF_B|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xA0, 0, 0}, 0, 2, 335 },
+    { SUF_W|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xA1, 0, 0}, 0, 2, 337 },
+    { SUF_L|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xA1, 0, 0}, 0, 2, 339 },
+    { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xA1, 0, 0}, 0, 2, 341 },
+    { SUF_B|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xA2, 0, 0}, 0, 2, 343 },
+    { SUF_W|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xA3, 0, 0}, 0, 2, 345 },
+    { SUF_L|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xA3, 0, 0}, 0, 2, 347 },
+    { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xA3, 0, 0}, 0, 2, 349 },
+    { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xB8, 0, 0}, 0, 2, 351 }
 };
 
 static const x86_insn_info movszx_insn[] = {
-   { SUF_B|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 16, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 535 },
-    { SUF_B|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 475 },
-    { SUF_B|SUF_Z, ONLY_64, 0, 0, 0, {MOD_Op1Add, 0, 0}, 64, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 479 },
-    { SUF_W|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 2, {0x0F, 0x01, 0}, 0, 2, 477 },
-    { SUF_W|SUF_Z, ONLY_64, 0, 0, 0, {MOD_Op1Add, 0, 0}, 64, 0, 0, 2, {0x0F, 0x01, 0}, 0, 2, 537 }
+   { SUF_B|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 16, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 599 },
+    { SUF_B|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 531 },
+    { SUF_B|SUF_Z, ONLY_64, 0, 0, 0, {MOD_Op1Add, 0, 0}, 64, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 535 },
+    { SUF_W|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 2, {0x0F, 0x01, 0}, 0, 2, 533 },
+    { SUF_W|SUF_Z, ONLY_64, 0, 0, 0, {MOD_Op1Add, 0, 0}, 64, 0, 0, 2, {0x0F, 0x01, 0}, 0, 2, 601 }
 };
 
 static const x86_insn_info movsxd_insn[] = {
-   { SUF_L|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x63, 0, 0}, 0, 2, 571 }
+   { SUF_L|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x63, 0, 0}, 0, 2, 641 }
 };
 
 static const x86_insn_info push_insn[] = {
-   { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 64, 0, 1, {0x50, 0, 0}, 0, 1, 357 },
-    { SUF_L|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x50, 0, 0}, 0, 1, 359 },
-    { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0x50, 0, 0}, 0, 1, 309 },
-    { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 64, 0, 1, {0xFF, 0, 0}, 6, 1, 239 },
-    { SUF_L|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xFF, 0, 0}, 6, 1, 235 },
-    { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0xFF, 0, 0}, 6, 1, 238 },
+   { SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0x50, 0, 0}, 0, 1, 651 },
+    { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 64, 0, 1, {0x50, 0, 0}, 0, 1, 399 },
+    { SUF_L|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x50, 0, 0}, 0, 1, 401 },
+    { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0x50, 0, 0}, 0, 1, 351 },
+    { SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0xFF, 0, 0}, 6, 1, 652 },
+    { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 64, 0, 1, {0xFF, 0, 0}, 6, 1, 281 },
+    { SUF_L|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xFF, 0, 0}, 6, 1, 277 },
+    { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0xFF, 0, 0}, 6, 1, 280 },
     { GAS_ILLEGAL|SUF_Z, 0, CPU_186, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0x6A, 0, 0}, 0, 1, 100 },
-    { GAS_ONLY|SUF_Z, 0, CPU_186, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0x6A, 0, 0}, 0, 1, 624 },
+    { GAS_ONLY|SUF_Z, 0, CPU_186, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0x6A, 0, 0}, 0, 1, 696 },
     { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 64, 0, 1, {0x6A, 0x68, 0}, 0, 1, 112 },
-    { GAS_ILLEGAL|SUF_Z, NOT_64, CPU_186, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x6A, 0x68, 0}, 0, 1, 625 },
-    { SUF_W|SUF_Z, 0, CPU_186, 0, 0, {0, 0, 0}, 16, 64, 0, 1, {0x6A, 0x68, 0}, 0, 1, 506 },
-    { SUF_L|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x6A, 0x68, 0}, 0, 1, 508 },
-    { GAS_ILLEGAL|SUF_Z, 0, CPU_186, 0, 0, {0, 0, 0}, 16, 64, 0, 1, {0x68, 0, 0}, 0, 1, 368 },
-    { GAS_ILLEGAL|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x68, 0, 0}, 0, 1, 370 },
-    { GAS_ILLEGAL|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 64, 0, 1, {0x68, 0, 0}, 0, 1, 626 },
-    { SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x0E, 0, 0}, 0, 1, 627 },
-    { SUF_W|SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x0E, 0, 0}, 0, 1, 628 },
-    { SUF_L|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x0E, 0, 0}, 0, 1, 629 },
-    { SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x16, 0, 0}, 0, 1, 581 },
-    { SUF_W|SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x16, 0, 0}, 0, 1, 582 },
-    { SUF_L|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x16, 0, 0}, 0, 1, 583 },
-    { SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x1E, 0, 0}, 0, 1, 584 },
-    { SUF_W|SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x1E, 0, 0}, 0, 1, 585 },
-    { SUF_L|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x1E, 0, 0}, 0, 1, 586 },
-    { SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x06, 0, 0}, 0, 1, 587 },
-    { SUF_W|SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x06, 0, 0}, 0, 1, 588 },
-    { SUF_L|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x06, 0, 0}, 0, 1, 589 },
-    { SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0xA0, 0}, 0, 1, 590 },
-    { SUF_W|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 16, 0, 0, 2, {0x0F, 0xA0, 0}, 0, 1, 591 },
-    { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 2, {0x0F, 0xA0, 0}, 0, 1, 592 },
-    { SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0xA8, 0}, 0, 1, 593 },
-    { SUF_W|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 16, 0, 0, 2, {0x0F, 0xA8, 0}, 0, 1, 594 },
-    { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 2, {0x0F, 0xA8, 0}, 0, 1, 595 }
+    { GAS_ILLEGAL|SUF_Z, NOT_64, CPU_186, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x6A, 0x68, 0}, 0, 1, 697 },
+    { SUF_W|SUF_Z, 0, CPU_186, 0, 0, {0, 0, 0}, 16, 64, 0, 1, {0x6A, 0x68, 0}, 0, 1, 570 },
+    { SUF_L|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x6A, 0x68, 0}, 0, 1, 572 },
+    { GAS_ILLEGAL|SUF_Z, 0, CPU_186, 0, 0, {0, 0, 0}, 16, 64, 0, 1, {0x68, 0, 0}, 0, 1, 410 },
+    { GAS_ILLEGAL|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x68, 0, 0}, 0, 1, 412 },
+    { GAS_ILLEGAL|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 64, 0, 1, {0x68, 0, 0}, 0, 1, 698 },
+    { SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x0E, 0, 0}, 0, 1, 699 },
+    { SUF_W|SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x0E, 0, 0}, 0, 1, 700 },
+    { SUF_L|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x0E, 0, 0}, 0, 1, 701 },
+    { SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x16, 0, 0}, 0, 1, 653 },
+    { SUF_W|SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x16, 0, 0}, 0, 1, 654 },
+    { SUF_L|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x16, 0, 0}, 0, 1, 655 },
+    { SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x1E, 0, 0}, 0, 1, 656 },
+    { SUF_W|SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x1E, 0, 0}, 0, 1, 657 },
+    { SUF_L|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x1E, 0, 0}, 0, 1, 658 },
+    { SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x06, 0, 0}, 0, 1, 659 },
+    { SUF_W|SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x06, 0, 0}, 0, 1, 660 },
+    { SUF_L|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x06, 0, 0}, 0, 1, 661 },
+    { SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0xA0, 0}, 0, 1, 662 },
+    { SUF_W|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 16, 0, 0, 2, {0x0F, 0xA0, 0}, 0, 1, 663 },
+    { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 2, {0x0F, 0xA0, 0}, 0, 1, 664 },
+    { SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0xA8, 0}, 0, 1, 665 },
+    { SUF_W|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 16, 0, 0, 2, {0x0F, 0xA8, 0}, 0, 1, 666 },
+    { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 2, {0x0F, 0xA8, 0}, 0, 1, 667 }
 };
 
 static const x86_insn_info pop_insn[] = {
-   { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 64, 0, 1, {0x58, 0, 0}, 0, 1, 357 },
-    { SUF_L|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x58, 0, 0}, 0, 1, 359 },
-    { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0x58, 0, 0}, 0, 1, 309 },
-    { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 64, 0, 1, {0x8F, 0, 0}, 0, 1, 239 },
-    { SUF_L|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x8F, 0, 0}, 0, 1, 235 },
-    { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0x8F, 0, 0}, 0, 1, 238 },
-    { SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x17, 0, 0}, 0, 1, 581 },
-    { SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x17, 0, 0}, 0, 1, 582 },
-    { SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x17, 0, 0}, 0, 1, 583 },
-    { SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x1F, 0, 0}, 0, 1, 584 },
-    { SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x1F, 0, 0}, 0, 1, 585 },
-    { SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x1F, 0, 0}, 0, 1, 586 },
-    { SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x07, 0, 0}, 0, 1, 587 },
-    { SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x07, 0, 0}, 0, 1, 588 },
-    { SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x07, 0, 0}, 0, 1, 589 },
-    { SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0xA1, 0}, 0, 1, 590 },
-    { SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 16, 0, 0, 2, {0x0F, 0xA1, 0}, 0, 1, 591 },
-    { SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 2, {0x0F, 0xA1, 0}, 0, 1, 592 },
-    { SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0xA9, 0}, 0, 1, 593 },
-    { SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 16, 0, 0, 2, {0x0F, 0xA9, 0}, 0, 1, 594 },
-    { SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 2, {0x0F, 0xA9, 0}, 0, 1, 595 }
+   { SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0x58, 0, 0}, 0, 1, 651 },
+    { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 64, 0, 1, {0x58, 0, 0}, 0, 1, 399 },
+    { SUF_L|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x58, 0, 0}, 0, 1, 401 },
+    { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0x58, 0, 0}, 0, 1, 351 },
+    { SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0x8F, 0, 0}, 0, 1, 652 },
+    { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 64, 0, 1, {0x8F, 0, 0}, 0, 1, 281 },
+    { SUF_L|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x8F, 0, 0}, 0, 1, 277 },
+    { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0x8F, 0, 0}, 0, 1, 280 },
+    { SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x17, 0, 0}, 0, 1, 653 },
+    { SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x17, 0, 0}, 0, 1, 654 },
+    { SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x17, 0, 0}, 0, 1, 655 },
+    { SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x1F, 0, 0}, 0, 1, 656 },
+    { SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x1F, 0, 0}, 0, 1, 657 },
+    { SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x1F, 0, 0}, 0, 1, 658 },
+    { SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x07, 0, 0}, 0, 1, 659 },
+    { SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x07, 0, 0}, 0, 1, 660 },
+    { SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x07, 0, 0}, 0, 1, 661 },
+    { SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0xA1, 0}, 0, 1, 662 },
+    { SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 16, 0, 0, 2, {0x0F, 0xA1, 0}, 0, 1, 663 },
+    { SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 2, {0x0F, 0xA1, 0}, 0, 1, 664 },
+    { SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0xA9, 0}, 0, 1, 665 },
+    { SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 16, 0, 0, 2, {0x0F, 0xA9, 0}, 0, 1, 666 },
+    { SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 2, {0x0F, 0xA9, 0}, 0, 1, 667 }
 };
 
 static const x86_insn_info xchg_insn[] = {
-   { SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x86, 0, 0}, 0, 2, 275 },
-    { SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x86, 0, 0}, 0, 2, 277 },
-    { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x90, 0, 0}, 0, 2, 455 },
-    { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x90, 0, 0}, 0, 2, 457 },
-    { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x87, 0, 0}, 0, 2, 212 },
+   { SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x86, 0, 0}, 0, 2, 317 },
+    { SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x86, 0, 0}, 0, 2, 319 },
+    { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x90, 0, 0}, 0, 2, 511 },
+    { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x90, 0, 0}, 0, 2, 513 },
+    { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x87, 0, 0}, 0, 2, 254 },
     { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x87, 0, 0}, 0, 2, 98 },
-    { SUF_L|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x87, 0, 0}, 0, 2, 459 },
-    { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x90, 0, 0}, 0, 2, 461 },
-    { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x90, 0, 0}, 0, 2, 463 },
-    { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x87, 0, 0}, 0, 2, 218 },
+    { SUF_L|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x87, 0, 0}, 0, 2, 515 },
+    { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x90, 0, 0}, 0, 2, 517 },
+    { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x90, 0, 0}, 0, 2, 519 },
+    { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x87, 0, 0}, 0, 2, 260 },
     { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x87, 0, 0}, 0, 2, 101 },
-    { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x90, 0, 0}, 0, 2, 465 },
-    { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x90, 0, 0}, 0, 2, 308 },
-    { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x90, 0, 0}, 0, 2, 467 },
-    { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x87, 0, 0}, 0, 2, 224 },
+    { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x90, 0, 0}, 0, 2, 521 },
+    { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x90, 0, 0}, 0, 2, 350 },
+    { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x90, 0, 0}, 0, 2, 523 },
+    { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x87, 0, 0}, 0, 2, 266 },
     { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x87, 0, 0}, 0, 2, 104 }
 };
 
 static const x86_insn_info in_insn[] = {
-   { SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xE4, 0, 0}, 0, 2, 440 },
-    { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xE5, 0, 0}, 0, 2, 442 },
-    { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xE5, 0, 0}, 0, 2, 545 },
-    { SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xEC, 0, 0}, 0, 2, 446 },
-    { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xED, 0, 0}, 0, 2, 448 },
-    { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xED, 0, 0}, 0, 2, 444 },
+   { SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xE4, 0, 0}, 0, 2, 492 },
+    { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xE5, 0, 0}, 0, 2, 494 },
+    { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xE5, 0, 0}, 0, 2, 613 },
+    { SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xEC, 0, 0}, 0, 2, 498 },
+    { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xED, 0, 0}, 0, 2, 500 },
+    { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xED, 0, 0}, 0, 2, 496 },
     { GAS_ONLY|SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xE4, 0, 0}, 0, 1, 3 },
     { GAS_ONLY|SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xE5, 0, 0}, 0, 1, 3 },
     { GAS_ONLY|SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xE5, 0, 0}, 0, 1, 3 },
-    { GAS_ONLY|SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xEC, 0, 0}, 0, 1, 445 },
-    { GAS_ONLY|SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xED, 0, 0}, 0, 1, 445 },
-    { GAS_ONLY|SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xED, 0, 0}, 0, 1, 445 }
+    { GAS_ONLY|SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xEC, 0, 0}, 0, 1, 497 },
+    { GAS_ONLY|SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xED, 0, 0}, 0, 1, 497 },
+    { GAS_ONLY|SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xED, 0, 0}, 0, 1, 497 }
 };
 
 static const x86_insn_info out_insn[] = {
-   { SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xE6, 0, 0}, 0, 2, 439 },
-    { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xE7, 0, 0}, 0, 2, 441 },
-    { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xE7, 0, 0}, 0, 2, 443 },
-    { SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xEE, 0, 0}, 0, 2, 445 },
-    { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xEF, 0, 0}, 0, 2, 447 },
-    { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xEF, 0, 0}, 0, 2, 449 },
+   { SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xE6, 0, 0}, 0, 2, 491 },
+    { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xE7, 0, 0}, 0, 2, 493 },
+    { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xE7, 0, 0}, 0, 2, 495 },
+    { SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xEE, 0, 0}, 0, 2, 497 },
+    { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xEF, 0, 0}, 0, 2, 499 },
+    { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xEF, 0, 0}, 0, 2, 501 },
     { GAS_ONLY|SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xE6, 0, 0}, 0, 1, 3 },
     { GAS_ONLY|SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xE7, 0, 0}, 0, 1, 3 },
     { GAS_ONLY|SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xE7, 0, 0}, 0, 1, 3 },
-    { GAS_ONLY|SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xEE, 0, 0}, 0, 1, 445 },
-    { GAS_ONLY|SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xEF, 0, 0}, 0, 1, 445 },
-    { GAS_ONLY|SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xEF, 0, 0}, 0, 1, 445 }
+    { GAS_ONLY|SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xEE, 0, 0}, 0, 1, 497 },
+    { GAS_ONLY|SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xEF, 0, 0}, 0, 1, 497 },
+    { GAS_ONLY|SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xEF, 0, 0}, 0, 1, 497 }
 };
 
 static const x86_insn_info lea_insn[] = {
-   { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x8D, 0, 0}, 0, 2, 469 },
-    { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x8D, 0, 0}, 0, 2, 471 },
-    { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x8D, 0, 0}, 0, 2, 473 }
+   { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x8D, 0, 0}, 0, 2, 525 },
+    { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x8D, 0, 0}, 0, 2, 527 },
+    { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x8D, 0, 0}, 0, 2, 529 }
 };
 
 static const x86_insn_info ldes_insn[] = {
-   { SUF_W|SUF_Z, NOT_64, 0, 0, 0, {MOD_Op0Add, 0, 0}, 16, 0, 0, 1, {0x00, 0, 0}, 0, 2, 469 },
-    { SUF_L|SUF_Z, NOT_64, CPU_386, 0, 0, {MOD_Op0Add, 0, 0}, 32, 0, 0, 1, {0x00, 0, 0}, 0, 2, 471 }
+   { SUF_W|SUF_Z, NOT_64, 0, 0, 0, {MOD_Op0Add, 0, 0}, 16, 0, 0, 1, {0x00, 0, 0}, 0, 2, 525 },
+    { SUF_L|SUF_Z, NOT_64, CPU_386, 0, 0, {MOD_Op0Add, 0, 0}, 32, 0, 0, 1, {0x00, 0, 0}, 0, 2, 527 }
 };
 
 static const x86_insn_info lfgss_insn[] = {
-   { SUF_W|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 16, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 469 },
-    { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 471 }
+   { SUF_W|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 16, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 525 },
+    { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 527 },
+    { SUF_Q|SUF_Z, ONLY_64, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 64, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 529 }
 };
 
 static const x86_insn_info arith_insn[] = {
-   { SUF_B|SUF_Z, 0, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 0, 0, 1, {0x04, 0, 0}, 0, 2, 440 },
-    { SUF_W|SUF_Z, 0, 0, 0, 0, {MOD_Op2Add, MOD_Op1AddSp, 0}, 16, 0, 0, 2, {0x83, 0xC0, 0x05}, 0, 2, 505 },
-    { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op2Add, MOD_Op1AddSp, 0}, 32, 0, 0, 2, {0x83, 0xC0, 0x05}, 0, 2, 507 },
-    { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {MOD_Op2Add, MOD_Op1AddSp, 0}, 64, 0, 0, 2, {0x83, 0xC0, 0x05}, 0, 2, 509 },
-    { SUF_B|SUF_Z, 0, 0, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 0, 0, 0, 1, {0x80, 0, 0}, 0, 2, 373 },
-    { SUF_B|SUF_Z, 0, 0, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 0, 0, 0, 1, {0x80, 0, 0}, 0, 2, 365 },
-    { SUF_W|SUF_Z, 0, 0, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 16, 0, 0, 1, {0x83, 0, 0}, 0, 2, 511 },
-    { GAS_ILLEGAL|SUF_Z, 0, 0, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 16, 0, 0, 1, {0x83, 0x81, 0}, 0, 2, 513 },
-    { SUF_W|SUF_Z, 0, 0, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 16, 0, 0, 1, {0x83, 0x81, 0}, 0, 2, 515 },
-    { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 32, 0, 0, 1, {0x83, 0, 0}, 0, 2, 517 },
-    { GAS_ILLEGAL|SUF_Z, NOT_64, CPU_386, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 32, 0, 0, 1, {0x83, 0x81, 0}, 0, 2, 519 },
-    { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 32, 0, 0, 1, {0x83, 0x81, 0}, 0, 2, 521 },
-    { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 64, 0, 0, 1, {0x83, 0, 0}, 0, 2, 523 },
-    { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 64, 0, 0, 1, {0x83, 0x81, 0}, 0, 2, 525 },
-    { SUF_B|SUF_Z, 0, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 0, 0, 1, {0x00, 0, 0}, 0, 2, 275 },
-    { SUF_W|SUF_Z, 0, 0, 0, 0, {MOD_Op0Add, 0, 0}, 16, 0, 0, 1, {0x01, 0, 0}, 0, 2, 212 },
-    { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op0Add, 0, 0}, 32, 0, 0, 1, {0x01, 0, 0}, 0, 2, 218 },
-    { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {MOD_Op0Add, 0, 0}, 64, 0, 0, 1, {0x01, 0, 0}, 0, 2, 224 },
-    { SUF_B|SUF_Z, 0, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 0, 0, 1, {0x02, 0, 0}, 0, 2, 277 },
+   { SUF_B|SUF_Z, 0, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 0, 0, 1, {0x04, 0, 0}, 0, 2, 492 },
+    { SUF_W|SUF_Z, 0, 0, 0, 0, {MOD_Op2Add, MOD_Op1AddSp, 0}, 16, 0, 0, 2, {0x83, 0xC0, 0x05}, 0, 2, 569 },
+    { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op2Add, MOD_Op1AddSp, 0}, 32, 0, 0, 2, {0x83, 0xC0, 0x05}, 0, 2, 571 },
+    { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {MOD_Op2Add, MOD_Op1AddSp, 0}, 64, 0, 0, 2, {0x83, 0xC0, 0x05}, 0, 2, 573 },
+    { SUF_B|SUF_Z, 0, 0, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 0, 0, 0, 1, {0x80, 0, 0}, 0, 2, 415 },
+    { SUF_B|SUF_Z, 0, 0, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 0, 0, 0, 1, {0x80, 0, 0}, 0, 2, 407 },
+    { SUF_W|SUF_Z, 0, 0, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 16, 0, 0, 1, {0x83, 0, 0}, 0, 2, 575 },
+    { GAS_ILLEGAL|SUF_Z, 0, 0, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 16, 0, 0, 1, {0x83, 0x81, 0}, 0, 2, 577 },
+    { SUF_W|SUF_Z, 0, 0, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 16, 0, 0, 1, {0x83, 0x81, 0}, 0, 2, 579 },
+    { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 32, 0, 0, 1, {0x83, 0, 0}, 0, 2, 581 },
+    { GAS_ILLEGAL|SUF_Z, NOT_64, CPU_386, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 32, 0, 0, 1, {0x83, 0x81, 0}, 0, 2, 583 },
+    { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 32, 0, 0, 1, {0x83, 0x81, 0}, 0, 2, 585 },
+    { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 64, 0, 0, 1, {0x83, 0, 0}, 0, 2, 587 },
+    { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 64, 0, 0, 1, {0x83, 0x81, 0}, 0, 2, 589 },
+    { SUF_B|SUF_Z, 0, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 0, 0, 1, {0x00, 0, 0}, 0, 2, 317 },
+    { SUF_W|SUF_Z, 0, 0, 0, 0, {MOD_Op0Add, 0, 0}, 16, 0, 0, 1, {0x01, 0, 0}, 0, 2, 254 },
+    { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op0Add, 0, 0}, 32, 0, 0, 1, {0x01, 0, 0}, 0, 2, 260 },
+    { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {MOD_Op0Add, 0, 0}, 64, 0, 0, 1, {0x01, 0, 0}, 0, 2, 266 },
+    { SUF_B|SUF_Z, 0, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 0, 0, 1, {0x02, 0, 0}, 0, 2, 319 },
     { SUF_W|SUF_Z, 0, 0, 0, 0, {MOD_Op0Add, 0, 0}, 16, 0, 0, 1, {0x03, 0, 0}, 0, 2, 98 },
     { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op0Add, 0, 0}, 32, 0, 0, 1, {0x03, 0, 0}, 0, 2, 101 },
     { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {MOD_Op0Add, 0, 0}, 64, 0, 0, 1, {0x03, 0, 0}, 0, 2, 104 }
 };
 
 static const x86_insn_info incdec_insn[] = {
-   { SUF_B|SUF_Z, 0, 0, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 0, 0, 0, 1, {0xFE, 0, 0}, 0, 1, 373 },
-    { SUF_W|SUF_Z, NOT_64, 0, 0, 0, {MOD_Op0Add, 0, 0}, 16, 0, 0, 1, {0x00, 0, 0}, 0, 1, 357 },
-    { SUF_W|SUF_Z, 0, 0, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 16, 0, 0, 1, {0xFF, 0, 0}, 0, 1, 239 },
-    { SUF_L|SUF_Z, NOT_64, CPU_386, 0, 0, {MOD_Op0Add, 0, 0}, 32, 0, 0, 1, {0x00, 0, 0}, 0, 1, 359 },
-    { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 32, 0, 0, 1, {0xFF, 0, 0}, 0, 1, 235 },
-    { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 64, 0, 0, 1, {0xFF, 0, 0}, 0, 1, 238 }
+   { SUF_B|SUF_Z, 0, 0, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 0, 0, 0, 1, {0xFE, 0, 0}, 0, 1, 415 },
+    { SUF_W|SUF_Z, NOT_64, 0, 0, 0, {MOD_Op0Add, 0, 0}, 16, 0, 0, 1, {0x00, 0, 0}, 0, 1, 399 },
+    { SUF_W|SUF_Z, 0, 0, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 16, 0, 0, 1, {0xFF, 0, 0}, 0, 1, 281 },
+    { SUF_L|SUF_Z, NOT_64, CPU_386, 0, 0, {MOD_Op0Add, 0, 0}, 32, 0, 0, 1, {0x00, 0, 0}, 0, 1, 401 },
+    { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 32, 0, 0, 1, {0xFF, 0, 0}, 0, 1, 277 },
+    { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 64, 0, 0, 1, {0xFF, 0, 0}, 0, 1, 280 }
 };
 
 static const x86_insn_info f6_insn[] = {
-   { SUF_B|SUF_Z, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 1, {0xF6, 0, 0}, 0, 1, 373 },
-    { SUF_W|SUF_Z, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 16, 0, 0, 1, {0xF7, 0, 0}, 0, 1, 239 },
-    { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_SpAdd, 0, 0}, 32, 0, 0, 1, {0xF7, 0, 0}, 0, 1, 235 },
-    { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {MOD_SpAdd, 0, 0}, 64, 0, 0, 1, {0xF7, 0, 0}, 0, 1, 238 }
+   { SUF_B|SUF_Z, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 1, {0xF6, 0, 0}, 0, 1, 415 },
+    { SUF_W|SUF_Z, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 16, 0, 0, 1, {0xF7, 0, 0}, 0, 1, 281 },
+    { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_SpAdd, 0, 0}, 32, 0, 0, 1, {0xF7, 0, 0}, 0, 1, 277 },
+    { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {MOD_SpAdd, 0, 0}, 64, 0, 0, 1, {0xF7, 0, 0}, 0, 1, 280 }
 };
 
 static const x86_insn_info div_insn[] = {
-   { SUF_B|SUF_Z, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 1, {0xF6, 0, 0}, 0, 1, 373 },
-    { SUF_W|SUF_Z, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 16, 0, 0, 1, {0xF7, 0, 0}, 0, 1, 239 },
-    { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_SpAdd, 0, 0}, 32, 0, 0, 1, {0xF7, 0, 0}, 0, 1, 235 },
-    { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {MOD_SpAdd, 0, 0}, 64, 0, 0, 1, {0xF7, 0, 0}, 0, 1, 238 },
-    { SUF_B|SUF_Z, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 1, {0xF6, 0, 0}, 0, 2, 411 },
-    { SUF_W|SUF_Z, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 16, 0, 0, 1, {0xF7, 0, 0}, 0, 2, 413 },
-    { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_SpAdd, 0, 0}, 32, 0, 0, 1, {0xF7, 0, 0}, 0, 2, 415 },
-    { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {MOD_SpAdd, 0, 0}, 64, 0, 0, 1, {0xF7, 0, 0}, 0, 2, 417 }
+   { SUF_B|SUF_Z, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 1, {0xF6, 0, 0}, 0, 1, 415 },
+    { SUF_W|SUF_Z, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 16, 0, 0, 1, {0xF7, 0, 0}, 0, 1, 281 },
+    { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_SpAdd, 0, 0}, 32, 0, 0, 1, {0xF7, 0, 0}, 0, 1, 277 },
+    { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {MOD_SpAdd, 0, 0}, 64, 0, 0, 1, {0xF7, 0, 0}, 0, 1, 280 },
+    { SUF_B|SUF_Z, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 1, {0xF6, 0, 0}, 0, 2, 465 },
+    { SUF_W|SUF_Z, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 16, 0, 0, 1, {0xF7, 0, 0}, 0, 2, 467 },
+    { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_SpAdd, 0, 0}, 32, 0, 0, 1, {0xF7, 0, 0}, 0, 2, 469 },
+    { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {MOD_SpAdd, 0, 0}, 64, 0, 0, 1, {0xF7, 0, 0}, 0, 2, 471 }
 };
 
 static const x86_insn_info test_insn[] = {
-   { SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xA8, 0, 0}, 0, 2, 440 },
-    { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xA9, 0, 0}, 0, 2, 555 },
-    { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xA9, 0, 0}, 0, 2, 557 },
-    { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xA9, 0, 0}, 0, 2, 559 },
-    { SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xF6, 0, 0}, 0, 2, 373 },
-    { SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xF6, 0, 0}, 0, 2, 365 },
-    { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xF7, 0, 0}, 0, 2, 375 },
-    { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xF7, 0, 0}, 0, 2, 367 },
-    { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xF7, 0, 0}, 0, 2, 377 },
-    { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xF7, 0, 0}, 0, 2, 369 },
-    { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xF7, 0, 0}, 0, 2, 379 },
-    { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xF7, 0, 0}, 0, 2, 371 },
-    { SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x84, 0, 0}, 0, 2, 275 },
-    { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x85, 0, 0}, 0, 2, 212 },
-    { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x85, 0, 0}, 0, 2, 218 },
-    { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x85, 0, 0}, 0, 2, 224 },
-    { SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x84, 0, 0}, 0, 2, 277 },
+   { SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xA8, 0, 0}, 0, 2, 492 },
+    { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xA9, 0, 0}, 0, 2, 619 },
+    { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xA9, 0, 0}, 0, 2, 621 },
+    { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xA9, 0, 0}, 0, 2, 623 },
+    { SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xF6, 0, 0}, 0, 2, 415 },
+    { SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xF6, 0, 0}, 0, 2, 407 },
+    { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xF7, 0, 0}, 0, 2, 417 },
+    { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xF7, 0, 0}, 0, 2, 409 },
+    { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xF7, 0, 0}, 0, 2, 419 },
+    { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xF7, 0, 0}, 0, 2, 411 },
+    { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xF7, 0, 0}, 0, 2, 421 },
+    { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xF7, 0, 0}, 0, 2, 413 },
+    { SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x84, 0, 0}, 0, 2, 317 },
+    { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x85, 0, 0}, 0, 2, 254 },
+    { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x85, 0, 0}, 0, 2, 260 },
+    { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x85, 0, 0}, 0, 2, 266 },
+    { SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x84, 0, 0}, 0, 2, 319 },
     { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x85, 0, 0}, 0, 2, 98 },
     { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x85, 0, 0}, 0, 2, 101 },
     { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x85, 0, 0}, 0, 2, 104 }
@@ -966,201 +1043,201 @@ static const x86_insn_info aadm_insn[] = {
 };
 
 static const x86_insn_info imul_insn[] = {
-   { SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xF6, 0, 0}, 5, 1, 373 },
-    { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xF7, 0, 0}, 5, 1, 239 },
-    { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xF7, 0, 0}, 5, 1, 235 },
-    { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xF7, 0, 0}, 5, 1, 238 },
+   { SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xF6, 0, 0}, 5, 1, 415 },
+    { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xF7, 0, 0}, 5, 1, 281 },
+    { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xF7, 0, 0}, 5, 1, 277 },
+    { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xF7, 0, 0}, 5, 1, 280 },
     { SUF_W|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 16, 0, 0, 2, {0x0F, 0xAF, 0}, 0, 2, 98 },
     { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 2, {0x0F, 0xAF, 0}, 0, 2, 101 },
     { SUF_Q|SUF_Z, ONLY_64, CPU_386, 0, 0, {0, 0, 0}, 64, 0, 0, 2, {0x0F, 0xAF, 0}, 0, 2, 104 },
     { SUF_W|SUF_Z, 0, CPU_186, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x6B, 0, 0}, 0, 3, 98 },
     { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x6B, 0, 0}, 0, 3, 101 },
     { SUF_Q|SUF_Z, ONLY_64, CPU_186, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x6B, 0, 0}, 0, 3, 104 },
-    { SUF_W|SUF_Z, 0, CPU_186, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x6B, 0, 0}, 0, 2, 255 },
-    { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x6B, 0, 0}, 0, 2, 257 },
-    { SUF_Q|SUF_Z, ONLY_64, CPU_186, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x6B, 0, 0}, 0, 2, 259 },
+    { SUF_W|SUF_Z, 0, CPU_186, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x6B, 0, 0}, 0, 2, 297 },
+    { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x6B, 0, 0}, 0, 2, 299 },
+    { SUF_Q|SUF_Z, ONLY_64, CPU_186, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x6B, 0, 0}, 0, 2, 301 },
     { SUF_W|SUF_Z, 0, CPU_186, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x6B, 0x69, 0}, 0, 3, 107 },
     { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x6B, 0x69, 0}, 0, 3, 110 },
     { SUF_Q|SUF_Z, ONLY_64, CPU_186, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x6B, 0x69, 0}, 0, 3, 113 },
-    { SUF_W|SUF_Z, 0, CPU_186, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x6B, 0x69, 0}, 0, 2, 261 },
-    { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x6B, 0x69, 0}, 0, 2, 263 },
-    { SUF_Q|SUF_Z, ONLY_64, CPU_186, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x6B, 0x69, 0}, 0, 2, 265 }
+    { SUF_W|SUF_Z, 0, CPU_186, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x6B, 0x69, 0}, 0, 2, 303 },
+    { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x6B, 0x69, 0}, 0, 2, 305 },
+    { SUF_Q|SUF_Z, ONLY_64, CPU_186, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x6B, 0x69, 0}, 0, 2, 307 }
 };
 
 static const x86_insn_info shift_insn[] = {
-   { SUF_B|SUF_Z, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 1, {0xD2, 0, 0}, 0, 2, 481 },
-    { SUF_B|SUF_Z, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 1, {0xD0, 0, 0}, 0, 2, 483 },
-    { SUF_B|SUF_Z, 0, CPU_186, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 1, {0xC0, 0, 0}, 0, 2, 373 },
-    { SUF_W|SUF_Z, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 16, 0, 0, 1, {0xD3, 0, 0}, 0, 2, 485 },
-    { SUF_W|SUF_Z, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 16, 0, 0, 1, {0xD1, 0, 0}, 0, 2, 487 },
-    { SUF_W|SUF_Z, 0, CPU_186, 0, 0, {MOD_SpAdd, 0, 0}, 16, 0, 0, 1, {0xC1, 0, 0}, 0, 2, 239 },
-    { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_SpAdd, 0, 0}, 32, 0, 0, 1, {0xD3, 0, 0}, 0, 2, 489 },
-    { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_SpAdd, 0, 0}, 32, 0, 0, 1, {0xD1, 0, 0}, 0, 2, 491 },
-    { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_SpAdd, 0, 0}, 32, 0, 0, 1, {0xC1, 0, 0}, 0, 2, 241 },
-    { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {MOD_SpAdd, 0, 0}, 64, 0, 0, 1, {0xD3, 0, 0}, 0, 2, 493 },
-    { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {MOD_SpAdd, 0, 0}, 64, 0, 0, 1, {0xD1, 0, 0}, 0, 2, 495 },
-    { SUF_Q|SUF_Z, ONLY_64, CPU_186, 0, 0, {MOD_SpAdd, 0, 0}, 64, 0, 0, 1, {0xC1, 0, 0}, 0, 2, 243 },
-    { GAS_ONLY|SUF_B|SUF_Z, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 1, {0xD0, 0, 0}, 0, 1, 373 },
-    { GAS_ONLY|SUF_W|SUF_Z, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 16, 0, 0, 1, {0xD1, 0, 0}, 0, 1, 239 },
-    { GAS_ONLY|SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_SpAdd, 0, 0}, 32, 0, 0, 1, {0xD1, 0, 0}, 0, 1, 235 },
-    { GAS_ONLY|SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {MOD_SpAdd, 0, 0}, 64, 0, 0, 1, {0xD1, 0, 0}, 0, 1, 238 }
+   { SUF_B|SUF_Z, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 1, {0xD2, 0, 0}, 0, 2, 545 },
+    { SUF_B|SUF_Z, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 1, {0xD0, 0, 0}, 0, 2, 547 },
+    { SUF_B|SUF_Z, 0, CPU_186, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 1, {0xC0, 0, 0}, 0, 2, 415 },
+    { SUF_W|SUF_Z, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 16, 0, 0, 1, {0xD3, 0, 0}, 0, 2, 549 },
+    { SUF_W|SUF_Z, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 16, 0, 0, 1, {0xD1, 0, 0}, 0, 2, 551 },
+    { SUF_W|SUF_Z, 0, CPU_186, 0, 0, {MOD_SpAdd, 0, 0}, 16, 0, 0, 1, {0xC1, 0, 0}, 0, 2, 281 },
+    { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_SpAdd, 0, 0}, 32, 0, 0, 1, {0xD3, 0, 0}, 0, 2, 553 },
+    { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_SpAdd, 0, 0}, 32, 0, 0, 1, {0xD1, 0, 0}, 0, 2, 555 },
+    { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_SpAdd, 0, 0}, 32, 0, 0, 1, {0xC1, 0, 0}, 0, 2, 283 },
+    { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {MOD_SpAdd, 0, 0}, 64, 0, 0, 1, {0xD3, 0, 0}, 0, 2, 557 },
+    { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {MOD_SpAdd, 0, 0}, 64, 0, 0, 1, {0xD1, 0, 0}, 0, 2, 559 },
+    { SUF_Q|SUF_Z, ONLY_64, CPU_186, 0, 0, {MOD_SpAdd, 0, 0}, 64, 0, 0, 1, {0xC1, 0, 0}, 0, 2, 285 },
+    { GAS_ONLY|SUF_B|SUF_Z, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 1, {0xD0, 0, 0}, 0, 1, 415 },
+    { GAS_ONLY|SUF_W|SUF_Z, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 16, 0, 0, 1, {0xD1, 0, 0}, 0, 1, 281 },
+    { GAS_ONLY|SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_SpAdd, 0, 0}, 32, 0, 0, 1, {0xD1, 0, 0}, 0, 1, 277 },
+    { GAS_ONLY|SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {MOD_SpAdd, 0, 0}, 64, 0, 0, 1, {0xD1, 0, 0}, 0, 1, 280 }
 };
 
 static const x86_insn_info shlrd_insn[] = {
-   { SUF_W|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 16, 0, 0, 2, {0x0F, 0x00, 0}, 0, 3, 212 },
-    { SUF_W|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 16, 0, 0, 2, {0x0F, 0x01, 0}, 0, 3, 215 },
-    { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 2, {0x0F, 0x00, 0}, 0, 3, 218 },
-    { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 2, {0x0F, 0x01, 0}, 0, 3, 221 },
-    { SUF_Q|SUF_Z, ONLY_64, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 64, 0, 0, 2, {0x0F, 0x00, 0}, 0, 3, 224 },
-    { SUF_Q|SUF_Z, ONLY_64, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 64, 0, 0, 2, {0x0F, 0x01, 0}, 0, 3, 227 },
-    { GAS_ONLY|SUF_W|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 16, 0, 0, 2, {0x0F, 0x01, 0}, 0, 2, 212 },
-    { GAS_ONLY|SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 2, {0x0F, 0x01, 0}, 0, 2, 218 },
-    { GAS_ONLY|SUF_Q|SUF_Z, ONLY_64, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 64, 0, 0, 2, {0x0F, 0x01, 0}, 0, 2, 224 }
+   { SUF_W|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 16, 0, 0, 2, {0x0F, 0x00, 0}, 0, 3, 254 },
+    { SUF_W|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 16, 0, 0, 2, {0x0F, 0x01, 0}, 0, 3, 257 },
+    { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 2, {0x0F, 0x00, 0}, 0, 3, 260 },
+    { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 2, {0x0F, 0x01, 0}, 0, 3, 263 },
+    { SUF_Q|SUF_Z, ONLY_64, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 64, 0, 0, 2, {0x0F, 0x00, 0}, 0, 3, 266 },
+    { SUF_Q|SUF_Z, ONLY_64, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 64, 0, 0, 2, {0x0F, 0x01, 0}, 0, 3, 269 },
+    { GAS_ONLY|SUF_W|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 16, 0, 0, 2, {0x0F, 0x01, 0}, 0, 2, 254 },
+    { GAS_ONLY|SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 2, {0x0F, 0x01, 0}, 0, 2, 260 },
+    { GAS_ONLY|SUF_Q|SUF_Z, ONLY_64, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 64, 0, 0, 2, {0x0F, 0x01, 0}, 0, 2, 266 }
 };
 
 static const x86_insn_info call_insn[] = {
-   { SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, {0, 0, 0}, 0, 1, 597 },
-    { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, {0, 0, 0}, 0, 1, 598 },
-    { SUF_L|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, {0, 0, 0}, 0, 1, 599 },
-    { SUF_L|SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 0, {0, 0, 0}, 0, 1, 599 },
-    { SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 64, 0, 1, {0xE8, 0, 0}, 0, 1, 600 },
-    { SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xE8, 0, 0}, 0, 1, 601 },
-    { SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 64, 0, 1, {0xE8, 0, 0}, 0, 1, 601 },
-    { SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0xE8, 0, 0}, 0, 1, 602 },
-    { SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xFF, 0, 0}, 2, 1, 239 },
-    { SUF_L, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xFF, 0, 0}, 2, 1, 235 },
-    { SUF_Q, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 64, 0, 1, {0xFF, 0, 0}, 2, 1, 238 },
-    { GAS_ONLY|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0xFF, 0, 0}, 2, 1, 603 },
-    { SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0xFF, 0, 0}, 2, 1, 596 },
-    { GAS_ILLEGAL|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 64, 0, 1, {0xFF, 0, 0}, 2, 1, 604 },
-    { GAS_ILLEGAL|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xFF, 0, 0}, 2, 1, 605 },
-    { GAS_ILLEGAL|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 64, 0, 1, {0xFF, 0, 0}, 2, 1, 606 },
-    { GAS_ILLEGAL|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0xFF, 0, 0}, 2, 1, 607 },
-    { GAS_ILLEGAL|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xFF, 0, 0}, 3, 1, 608 },
-    { GAS_ILLEGAL|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xFF, 0, 0}, 3, 1, 609 },
-    { GAS_ILLEGAL|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xFF, 0, 0}, 3, 1, 610 },
-    { GAS_ILLEGAL|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xFF, 0, 0}, 3, 1, 611 },
-    { GAS_ILLEGAL|SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x9A, 0, 0}, 0, 1, 612 },
-    { GAS_ILLEGAL|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x9A, 0, 0}, 0, 1, 613 },
-    { GAS_ILLEGAL|SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x9A, 0, 0}, 0, 1, 614 },
-    { GAS_ILLEGAL|SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x9A, 0, 0}, 0, 1, 615 },
-    { GAS_ILLEGAL|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x9A, 0, 0}, 0, 1, 616 },
-    { GAS_ILLEGAL|SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x9A, 0, 0}, 0, 1, 617 },
-    { GAS_ONLY|GAS_NO_REV|SUF_W, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x9A, 0, 0}, 0, 2, 499 },
-    { GAS_ONLY|GAS_NO_REV|SUF_L, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x9A, 0, 0}, 0, 2, 501 },
-    { GAS_ONLY|GAS_NO_REV|SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x9A, 0, 0}, 0, 2, 503 }
+   { SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, {0, 0, 0}, 0, 1, 669 },
+    { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, {0, 0, 0}, 0, 1, 670 },
+    { SUF_L|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, {0, 0, 0}, 0, 1, 671 },
+    { SUF_L|SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 0, {0, 0, 0}, 0, 1, 671 },
+    { SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 64, 0, 1, {0xE8, 0, 0}, 0, 1, 672 },
+    { SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xE8, 0, 0}, 0, 1, 673 },
+    { SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 64, 0, 1, {0xE8, 0, 0}, 0, 1, 673 },
+    { SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0xE8, 0, 0}, 0, 1, 674 },
+    { SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xFF, 0, 0}, 2, 1, 281 },
+    { SUF_L, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xFF, 0, 0}, 2, 1, 277 },
+    { SUF_Q, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 64, 0, 1, {0xFF, 0, 0}, 2, 1, 280 },
+    { GAS_ONLY|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0xFF, 0, 0}, 2, 1, 675 },
+    { SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0xFF, 0, 0}, 2, 1, 668 },
+    { GAS_ILLEGAL|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 64, 0, 1, {0xFF, 0, 0}, 2, 1, 676 },
+    { GAS_ILLEGAL|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xFF, 0, 0}, 2, 1, 677 },
+    { GAS_ILLEGAL|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 64, 0, 1, {0xFF, 0, 0}, 2, 1, 678 },
+    { GAS_ILLEGAL|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0xFF, 0, 0}, 2, 1, 679 },
+    { GAS_ILLEGAL|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xFF, 0, 0}, 3, 1, 680 },
+    { GAS_ILLEGAL|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xFF, 0, 0}, 3, 1, 681 },
+    { GAS_ILLEGAL|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xFF, 0, 0}, 3, 1, 682 },
+    { GAS_ILLEGAL|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xFF, 0, 0}, 3, 1, 683 },
+    { GAS_ILLEGAL|SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x9A, 0, 0}, 0, 1, 684 },
+    { GAS_ILLEGAL|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x9A, 0, 0}, 0, 1, 685 },
+    { GAS_ILLEGAL|SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x9A, 0, 0}, 0, 1, 686 },
+    { GAS_ILLEGAL|SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x9A, 0, 0}, 0, 1, 687 },
+    { GAS_ILLEGAL|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x9A, 0, 0}, 0, 1, 688 },
+    { GAS_ILLEGAL|SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x9A, 0, 0}, 0, 1, 689 },
+    { GAS_ONLY|GAS_NO_REV|SUF_W, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x9A, 0, 0}, 0, 2, 563 },
+    { GAS_ONLY|GAS_NO_REV|SUF_L, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x9A, 0, 0}, 0, 2, 565 },
+    { GAS_ONLY|GAS_NO_REV|SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x9A, 0, 0}, 0, 2, 567 }
 };
 
 static const x86_insn_info jmp_insn[] = {
-   { SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, {0, 0, 0}, 0, 1, 597 },
-    { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, {0, 0, 0}, 0, 1, 598 },
-    { SUF_L|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x00, 0, 0}, 0, 1, 599 },
-    { SUF_L|SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x00, 0, 0}, 0, 1, 599 },
-    { SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0xEB, 0, 0}, 0, 1, 421 },
-    { SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 64, 0, 1, {0xE9, 0, 0}, 0, 1, 600 },
-    { SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xE9, 0, 0}, 0, 1, 601 },
-    { SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 64, 0, 1, {0xE9, 0, 0}, 0, 1, 601 },
-    { SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0xE9, 0, 0}, 0, 1, 602 },
-    { SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 64, 0, 1, {0xFF, 0, 0}, 4, 1, 239 },
-    { SUF_L, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xFF, 0, 0}, 4, 1, 235 },
-    { SUF_Q, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 64, 0, 1, {0xFF, 0, 0}, 4, 1, 238 },
-    { GAS_ONLY|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0xFF, 0, 0}, 4, 1, 603 },
-    { SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0xFF, 0, 0}, 4, 1, 596 },
-    { GAS_ILLEGAL|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 64, 0, 1, {0xFF, 0, 0}, 4, 1, 604 },
-    { GAS_ILLEGAL|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xFF, 0, 0}, 4, 1, 605 },
-    { GAS_ILLEGAL|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 64, 0, 1, {0xFF, 0, 0}, 4, 1, 606 },
-    { GAS_ILLEGAL|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0xFF, 0, 0}, 4, 1, 607 },
-    { SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xFF, 0, 0}, 5, 1, 608 },
-    { SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xFF, 0, 0}, 5, 1, 609 },
-    { SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xFF, 0, 0}, 5, 1, 610 },
-    { SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xFF, 0, 0}, 5, 1, 611 },
-    { SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xEA, 0, 0}, 0, 1, 612 },
-    { SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xEA, 0, 0}, 0, 1, 613 },
-    { SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xEA, 0, 0}, 0, 1, 614 },
-    { GAS_ILLEGAL|SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xEA, 0, 0}, 0, 1, 615 },
-    { GAS_ILLEGAL|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xEA, 0, 0}, 0, 1, 616 },
-    { GAS_ILLEGAL|SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xEA, 0, 0}, 0, 1, 617 },
-    { GAS_ONLY|GAS_NO_REV|SUF_W, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xEA, 0, 0}, 0, 2, 499 },
-    { GAS_ONLY|GAS_NO_REV|SUF_L, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xEA, 0, 0}, 0, 2, 501 },
-    { GAS_ONLY|GAS_NO_REV|SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xEA, 0, 0}, 0, 2, 503 }
+   { SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, {0, 0, 0}, 0, 1, 669 },
+    { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, {0, 0, 0}, 0, 1, 670 },
+    { SUF_L|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x00, 0, 0}, 0, 1, 671 },
+    { SUF_L|SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x00, 0, 0}, 0, 1, 671 },
+    { SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0xEB, 0, 0}, 0, 1, 477 },
+    { SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 64, 0, 1, {0xE9, 0, 0}, 0, 1, 672 },
+    { SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xE9, 0, 0}, 0, 1, 673 },
+    { SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 64, 0, 1, {0xE9, 0, 0}, 0, 1, 673 },
+    { SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0xE9, 0, 0}, 0, 1, 674 },
+    { SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 64, 0, 1, {0xFF, 0, 0}, 4, 1, 281 },
+    { SUF_L, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xFF, 0, 0}, 4, 1, 277 },
+    { SUF_Q, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 64, 0, 1, {0xFF, 0, 0}, 4, 1, 280 },
+    { GAS_ONLY|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0xFF, 0, 0}, 4, 1, 675 },
+    { SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0xFF, 0, 0}, 4, 1, 668 },
+    { GAS_ILLEGAL|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 64, 0, 1, {0xFF, 0, 0}, 4, 1, 676 },
+    { GAS_ILLEGAL|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xFF, 0, 0}, 4, 1, 677 },
+    { GAS_ILLEGAL|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 64, 0, 1, {0xFF, 0, 0}, 4, 1, 678 },
+    { GAS_ILLEGAL|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0xFF, 0, 0}, 4, 1, 679 },
+    { SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xFF, 0, 0}, 5, 1, 680 },
+    { SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xFF, 0, 0}, 5, 1, 681 },
+    { SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xFF, 0, 0}, 5, 1, 682 },
+    { SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xFF, 0, 0}, 5, 1, 683 },
+    { SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xEA, 0, 0}, 0, 1, 684 },
+    { SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xEA, 0, 0}, 0, 1, 685 },
+    { SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xEA, 0, 0}, 0, 1, 686 },
+    { GAS_ILLEGAL|SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xEA, 0, 0}, 0, 1, 687 },
+    { GAS_ILLEGAL|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xEA, 0, 0}, 0, 1, 688 },
+    { GAS_ILLEGAL|SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xEA, 0, 0}, 0, 1, 689 },
+    { GAS_ONLY|GAS_NO_REV|SUF_W, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xEA, 0, 0}, 0, 2, 563 },
+    { GAS_ONLY|GAS_NO_REV|SUF_L, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xEA, 0, 0}, 0, 2, 565 },
+    { GAS_ONLY|GAS_NO_REV|SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xEA, 0, 0}, 0, 2, 567 }
 };
 
 static const x86_insn_info ljmpcall_insn[] = {
-   { SUF_W, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 16, 0, 0, 1, {0xFF, 0, 0}, 0, 1, 22 },
-    { SUF_L, 0, CPU_386, 0, 0, {MOD_SpAdd, 0, 0}, 32, 0, 0, 1, {0xFF, 0, 0}, 0, 1, 50 },
+   { SUF_W, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 16, 0, 0, 1, {0xFF, 0, 0}, 0, 1, 34 },
+    { SUF_L, 0, CPU_386, 0, 0, {MOD_SpAdd, 0, 0}, 32, 0, 0, 1, {0xFF, 0, 0}, 0, 1, 58 },
     { SUF_Q, ONLY_64, 0, 0, 0, {MOD_SpAdd, 0, 0}, 64, 0, 0, 1, {0xFF, 0, 0}, 0, 1, 6 },
-    { SUF_Z, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 1, {0xFF, 0, 0}, 0, 1, 621 },
-    { GAS_NO_REV|SUF_W, NOT_64, 0, 0, 0, {MOD_Gap, MOD_Op0Add, 0}, 16, 0, 0, 1, {0x00, 0, 0}, 0, 2, 499 },
-    { GAS_NO_REV|SUF_L, NOT_64, CPU_386, 0, 0, {MOD_Gap, MOD_Op0Add, 0}, 32, 0, 0, 1, {0x00, 0, 0}, 0, 2, 501 },
-    { GAS_NO_REV|SUF_Z, NOT_64, 0, 0, 0, {MOD_Gap, MOD_Op0Add, 0}, 0, 0, 0, 1, {0x00, 0, 0}, 0, 2, 503 }
+    { SUF_Z, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 1, {0xFF, 0, 0}, 0, 1, 693 },
+    { GAS_NO_REV|SUF_W, NOT_64, 0, 0, 0, {MOD_Gap, MOD_Op0Add, 0}, 16, 0, 0, 1, {0x00, 0, 0}, 0, 2, 563 },
+    { GAS_NO_REV|SUF_L, NOT_64, CPU_386, 0, 0, {MOD_Gap, MOD_Op0Add, 0}, 32, 0, 0, 1, {0x00, 0, 0}, 0, 2, 565 },
+    { GAS_NO_REV|SUF_Z, NOT_64, 0, 0, 0, {MOD_Gap, MOD_Op0Add, 0}, 0, 0, 0, 1, {0x00, 0, 0}, 0, 2, 567 }
 };
 
 static const x86_insn_info retnf_insn[] = {
    { SUF_Z, NOT_64, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 0, 0, 1, {0x01, 0, 0}, 0, 0, 0 },
-    { SUF_Z, NOT_64, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 0, 0, 1, {0x00, 0, 0}, 0, 1, 358 },
+    { SUF_Z, NOT_64, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 0, 0, 1, {0x00, 0, 0}, 0, 1, 400 },
     { SUF_Z, ONLY_64, 0, 0, 0, {MOD_Op0Add, MOD_OpSizeR, 0}, 0, 0, 0, 1, {0x01, 0, 0}, 0, 0, 0 },
-    { SUF_Z, ONLY_64, 0, 0, 0, {MOD_Op0Add, MOD_OpSizeR, 0}, 0, 0, 0, 1, {0x00, 0, 0}, 0, 1, 358 },
+    { SUF_Z, ONLY_64, 0, 0, 0, {MOD_Op0Add, MOD_OpSizeR, 0}, 0, 0, 0, 1, {0x00, 0, 0}, 0, 1, 400 },
     { SUF_L|SUF_Q|SUF_W|SUF_Z, 0, 0, 0, 0, {MOD_Op0Add, MOD_OpSizeR, 0}, 0, 0, 0, 1, {0x01, 0, 0}, 0, 0, 0 },
-    { SUF_L|SUF_Q|SUF_W|SUF_Z, 0, 0, 0, 0, {MOD_Op0Add, MOD_OpSizeR, 0}, 0, 0, 0, 1, {0x00, 0, 0}, 0, 1, 358 }
+    { SUF_L|SUF_Q|SUF_W|SUF_Z, 0, 0, 0, 0, {MOD_Op0Add, MOD_OpSizeR, 0}, 0, 0, 0, 1, {0x00, 0, 0}, 0, 1, 400 }
 };
 
 static const x86_insn_info enter_insn[] = {
-   { GAS_NO_REV|SUF_L|SUF_Z, NOT_64, CPU_186, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xC8, 0, 0}, 0, 2, 569 },
-    { GAS_NO_REV|SUF_Q|SUF_Z, ONLY_64, CPU_186, 0, 0, {0, 0, 0}, 64, 64, 0, 1, {0xC8, 0, 0}, 0, 2, 569 },
-    { GAS_ONLY|GAS_NO_REV|SUF_W|SUF_Z, 0, CPU_186, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xC8, 0, 0}, 0, 2, 569 }
+   { GAS_NO_REV|SUF_L|SUF_Z, NOT_64, CPU_186, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xC8, 0, 0}, 0, 2, 639 },
+    { GAS_NO_REV|SUF_Q|SUF_Z, ONLY_64, CPU_186, 0, 0, {0, 0, 0}, 64, 64, 0, 1, {0xC8, 0, 0}, 0, 2, 639 },
+    { GAS_ONLY|GAS_NO_REV|SUF_W|SUF_Z, 0, CPU_186, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xC8, 0, 0}, 0, 2, 639 }
 };
 
 static const x86_insn_info jcc_insn[] = {
-   { SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, {0, 0, 0}, 0, 1, 419 },
-    { SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, {0, 0, 0}, 0, 1, 622 },
-    { SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, {0, 0, 0}, 0, 1, 623 },
-    { SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 0, {0, 0, 0}, 0, 1, 623 },
-    { SUF_Z, 0, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 64, 0, 1, {0x70, 0, 0}, 0, 1, 421 },
-    { SUF_Z, 0, CPU_186, 0, 0, {MOD_Op1Add, 0, 0}, 16, 64, 0, 2, {0x0F, 0x80, 0}, 0, 1, 600 },
-    { SUF_Z, NOT_64, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 2, {0x0F, 0x80, 0}, 0, 1, 601 },
-    { SUF_Z, ONLY_64, 0, 0, 0, {MOD_Op1Add, 0, 0}, 64, 64, 0, 2, {0x0F, 0x80, 0}, 0, 1, 601 },
-    { SUF_Z, 0, CPU_186, 0, 0, {MOD_Op1Add, 0, 0}, 0, 64, 0, 2, {0x0F, 0x80, 0}, 0, 1, 602 }
+   { SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, {0, 0, 0}, 0, 1, 475 },
+    { SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, {0, 0, 0}, 0, 1, 694 },
+    { SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, {0, 0, 0}, 0, 1, 695 },
+    { SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 0, {0, 0, 0}, 0, 1, 695 },
+    { SUF_Z, 0, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 64, 0, 1, {0x70, 0, 0}, 0, 1, 477 },
+    { SUF_Z, 0, CPU_186, 0, 0, {MOD_Op1Add, 0, 0}, 16, 64, 0, 2, {0x0F, 0x80, 0}, 0, 1, 672 },
+    { SUF_Z, NOT_64, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 2, {0x0F, 0x80, 0}, 0, 1, 673 },
+    { SUF_Z, ONLY_64, 0, 0, 0, {MOD_Op1Add, 0, 0}, 64, 64, 0, 2, {0x0F, 0x80, 0}, 0, 1, 673 },
+    { SUF_Z, 0, CPU_186, 0, 0, {MOD_Op1Add, 0, 0}, 0, 64, 0, 2, {0x0F, 0x80, 0}, 0, 1, 674 }
 };
 
 static const x86_insn_info jcxz_insn[] = {
-   { SUF_Z, 0, 0, 0, 0, {MOD_AdSizeR, 0, 0}, 0, 0, 0, 0, {0, 0, 0}, 0, 1, 419 },
-    { SUF_Z, 0, 0, 0, 0, {MOD_AdSizeR, 0, 0}, 0, 64, 0, 1, {0xE3, 0, 0}, 0, 1, 421 }
+   { SUF_Z, 0, 0, 0, 0, {MOD_AdSizeR, 0, 0}, 0, 0, 0, 0, {0, 0, 0}, 0, 1, 475 },
+    { SUF_Z, 0, 0, 0, 0, {MOD_AdSizeR, 0, 0}, 0, 64, 0, 1, {0xE3, 0, 0}, 0, 1, 477 }
 };
 
 static const x86_insn_info loop_insn[] = {
-   { SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, {0, 0, 0}, 0, 1, 419 },
-    { SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, {0, 0, 0}, 0, 2, 433 },
-    { SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 0, 64, 0, 0, {0, 0, 0}, 0, 2, 419 },
-    { SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 0, {0, 0, 0}, 0, 2, 429 },
-    { SUF_Z, NOT_64, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 0, 0, 1, {0xE0, 0, 0}, 0, 1, 421 },
-    { SUF_Z, 0, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 64, 0, 1, {0xE0, 0, 0}, 0, 2, 435 },
-    { SUF_Z, 0, CPU_386, 0, 0, {MOD_Op0Add, 0, 0}, 0, 64, 0, 1, {0xE0, 0, 0}, 0, 2, 421 },
-    { SUF_Z, ONLY_64, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 64, 0, 1, {0xE0, 0, 0}, 0, 2, 431 }
+   { SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, {0, 0, 0}, 0, 1, 475 },
+    { SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, {0, 0, 0}, 0, 2, 487 },
+    { SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 0, 64, 0, 0, {0, 0, 0}, 0, 2, 475 },
+    { SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 0, {0, 0, 0}, 0, 2, 483 },
+    { SUF_Z, NOT_64, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 0, 0, 1, {0xE0, 0, 0}, 0, 1, 477 },
+    { SUF_Z, 0, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 64, 0, 1, {0xE0, 0, 0}, 0, 2, 489 },
+    { SUF_Z, 0, CPU_386, 0, 0, {MOD_Op0Add, 0, 0}, 0, 64, 0, 1, {0xE0, 0, 0}, 0, 2, 477 },
+    { SUF_Z, ONLY_64, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 64, 0, 1, {0xE0, 0, 0}, 0, 2, 485 }
 };
 
 static const x86_insn_info loopw_insn[] = {
-   { SUF_Z, NOT_64, 0, 0, 0, {MOD_Gap, MOD_AdSizeR, 0}, 0, 64, 0, 0, {0, 0, 0}, 0, 1, 419 },
-    { SUF_Z, NOT_64, 0, 0, 0, {MOD_Op0Add, MOD_AdSizeR, 0}, 0, 64, 0, 1, {0xE0, 0, 0}, 0, 1, 421 },
-    { SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 0, {0, 0, 0}, 0, 2, 433 },
-    { SUF_Z, NOT_64, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 64, 0, 1, {0xE0, 0, 0}, 0, 2, 435 }
+   { SUF_Z, NOT_64, 0, 0, 0, {MOD_Gap, MOD_AdSizeR, 0}, 0, 64, 0, 0, {0, 0, 0}, 0, 1, 475 },
+    { SUF_Z, NOT_64, 0, 0, 0, {MOD_Op0Add, MOD_AdSizeR, 0}, 0, 64, 0, 1, {0xE0, 0, 0}, 0, 1, 477 },
+    { SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 0, {0, 0, 0}, 0, 2, 487 },
+    { SUF_Z, NOT_64, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 64, 0, 1, {0xE0, 0, 0}, 0, 2, 489 }
 };
 
 static const x86_insn_info loopl_insn[] = {
-   { SUF_Z, 0, 0, 0, 0, {MOD_Gap, MOD_AdSizeR, 0}, 0, 64, 0, 0, {0, 0, 0}, 0, 1, 419 },
-    { SUF_Z, 0, 0, 0, 0, {MOD_Op0Add, MOD_AdSizeR, 0}, 0, 64, 0, 1, {0xE0, 0, 0}, 0, 1, 421 },
-    { SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 0, 64, 0, 0, {0, 0, 0}, 0, 2, 419 },
-    { SUF_Z, 0, CPU_386, 0, 0, {MOD_Op0Add, 0, 0}, 0, 64, 0, 1, {0xE0, 0, 0}, 0, 2, 421 }
+   { SUF_Z, 0, 0, 0, 0, {MOD_Gap, MOD_AdSizeR, 0}, 0, 64, 0, 0, {0, 0, 0}, 0, 1, 475 },
+    { SUF_Z, 0, 0, 0, 0, {MOD_Op0Add, MOD_AdSizeR, 0}, 0, 64, 0, 1, {0xE0, 0, 0}, 0, 1, 477 },
+    { SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 0, 64, 0, 0, {0, 0, 0}, 0, 2, 475 },
+    { SUF_Z, 0, CPU_386, 0, 0, {MOD_Op0Add, 0, 0}, 0, 64, 0, 1, {0xE0, 0, 0}, 0, 2, 477 }
 };
 
 static const x86_insn_info loopq_insn[] = {
-   { SUF_Z, ONLY_64, 0, 0, 0, {MOD_Gap, MOD_AdSizeR, 0}, 0, 64, 0, 0, {0, 0, 0}, 0, 1, 419 },
-    { SUF_Z, ONLY_64, 0, 0, 0, {MOD_Op0Add, MOD_AdSizeR, 0}, 0, 64, 0, 1, {0xE0, 0, 0}, 0, 1, 421 },
-    { SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 0, {0, 0, 0}, 0, 2, 429 },
-    { SUF_Z, ONLY_64, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 64, 0, 1, {0xE0, 0, 0}, 0, 2, 431 }
+   { SUF_Z, ONLY_64, 0, 0, 0, {MOD_Gap, MOD_AdSizeR, 0}, 0, 64, 0, 0, {0, 0, 0}, 0, 1, 475 },
+    { SUF_Z, ONLY_64, 0, 0, 0, {MOD_Op0Add, MOD_AdSizeR, 0}, 0, 64, 0, 1, {0xE0, 0, 0}, 0, 1, 477 },
+    { SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 0, {0, 0, 0}, 0, 2, 483 },
+    { SUF_Z, ONLY_64, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 64, 0, 1, {0xE0, 0, 0}, 0, 2, 485 }
 };
 
 static const x86_insn_info setcc_insn[] = {
-   { SUF_B|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0x0F, 0x90, 0}, 2, 1, 275 }
+   { SUF_B|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0x0F, 0x90, 0}, 2, 1, 317 }
 };
 
 static const x86_insn_info cmpsd_insn[] = {
@@ -1174,18 +1251,18 @@ static const x86_insn_info cmpsd_insn[] = {
 static const x86_insn_info movsd_insn[] = {
    { SUF_Z, NOT_AVX, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xA5, 0, 0}, 0, 0, 0 },
     { SUF_Z, 0, CPU_SSE2, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0xF2, 2, {0x0F, 0x10, 0}, 0, 2, 92 },
-    { SUF_Z, 0, CPU_SSE2, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0xF2, 2, {0x0F, 0x10, 0}, 0, 2, 401 },
-    { SUF_Z, 0, CPU_SSE2, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0xF2, 2, {0x0F, 0x11, 0}, 0, 2, 39 },
+    { SUF_Z, 0, CPU_SSE2, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0xF2, 2, {0x0F, 0x10, 0}, 0, 2, 445 },
+    { SUF_Z, 0, CPU_SSE2, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0xF2, 2, {0x0F, 0x11, 0}, 0, 2, 47 },
     { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC3, 2, {0x0F, 0x10, 0}, 0, 3, 0 }
 };
 
 static const x86_insn_info bittest_insn[] = {
-   { SUF_W|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 16, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 212 },
-    { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 218 },
-    { SUF_Q|SUF_Z, ONLY_64, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 64, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 224 },
-    { SUF_W|SUF_Z, 0, CPU_386, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 16, 0, 0, 2, {0x0F, 0xBA, 0}, 0, 2, 239 },
-    { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 32, 0, 0, 2, {0x0F, 0xBA, 0}, 0, 2, 241 },
-    { SUF_Q|SUF_Z, ONLY_64, CPU_386, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 64, 0, 0, 2, {0x0F, 0xBA, 0}, 0, 2, 243 }
+   { SUF_W|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 16, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 254 },
+    { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 260 },
+    { SUF_Q|SUF_Z, ONLY_64, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 64, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 266 },
+    { SUF_W|SUF_Z, 0, CPU_386, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 16, 0, 0, 2, {0x0F, 0xBA, 0}, 0, 2, 281 },
+    { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 32, 0, 0, 2, {0x0F, 0xBA, 0}, 0, 2, 283 },
+    { SUF_Q|SUF_Z, ONLY_64, CPU_386, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 64, 0, 0, 2, {0x0F, 0xBA, 0}, 0, 2, 285 }
 };
 
 static const x86_insn_info bsfr_insn[] = {
@@ -1199,18 +1276,27 @@ static const x86_insn_info int_insn[] = {
 };
 
 static const x86_insn_info bound_insn[] = {
-   { SUF_W|SUF_Z, NOT_64, CPU_186, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x62, 0, 0}, 0, 2, 405 },
-    { SUF_L|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x62, 0, 0}, 0, 2, 311 }
+   { SUF_W|SUF_Z, NOT_64, CPU_186, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x62, 0, 0}, 0, 2, 459 },
+    { SUF_L|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x62, 0, 0}, 0, 2, 353 }
+};
+
+static const x86_insn_info larlsl_insn[] = {
+   { SUF_W|SUF_Z, 0, 0, 0, 0, {MOD_Op1Add, 0, 0}, 16, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 449 },
+    { SUF_W|SUF_Z, 0, 0, 0, 0, {MOD_Op1Add, 0, 0}, 16, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 98 },
+    { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 451 },
+    { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 453 },
+    { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {MOD_Op1Add, 0, 0}, 64, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 455 },
+    { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {MOD_Op1Add, 0, 0}, 64, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 457 }
 };
 
 static const x86_insn_info arpl_insn[] = {
-   { SUF_W|SUF_Z, NOT_64, CPU_286, CPU_Prot, 0, {0, 0, 0}, 0, 0, 0, 1, {0x63, 0, 0}, 0, 2, 212 }
+   { SUF_W|SUF_Z, NOT_64, CPU_286, CPU_Prot, 0, {0, 0, 0}, 0, 0, 0, 1, {0x63, 0, 0}, 0, 2, 254 }
 };
 
 static const x86_insn_info str_insn[] = {
-   { SUF_W|SUF_Z, 0, CPU_286, CPU_Prot, 0, {0, 0, 0}, 16, 0, 0, 2, {0x0F, 0x00, 0}, 1, 1, 347 },
-    { SUF_L|SUF_Z, 0, CPU_386, CPU_Prot, 0, {0, 0, 0}, 32, 0, 0, 2, {0x0F, 0x00, 0}, 1, 1, 14 },
-    { SUF_Q|SUF_Z, ONLY_64, CPU_286, CPU_Prot, 0, {0, 0, 0}, 64, 0, 0, 2, {0x0F, 0x00, 0}, 1, 1, 18 },
+   { SUF_W|SUF_Z, 0, CPU_286, CPU_Prot, 0, {0, 0, 0}, 16, 0, 0, 2, {0x0F, 0x00, 0}, 1, 1, 389 },
+    { SUF_L|SUF_Z, 0, CPU_386, CPU_Prot, 0, {0, 0, 0}, 32, 0, 0, 2, {0x0F, 0x00, 0}, 1, 1, 26 },
+    { SUF_Q|SUF_Z, ONLY_64, CPU_286, CPU_Prot, 0, {0, 0, 0}, 64, 0, 0, 2, {0x0F, 0x00, 0}, 1, 1, 30 },
     { SUF_L|SUF_W|SUF_Z, 0, CPU_286, CPU_Prot, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x00, 0}, 1, 1, 99 }
 };
 
@@ -1219,123 +1305,123 @@ static const x86_insn_info prot286_insn[] = {
 };
 
 static const x86_insn_info sldtmsw_insn[] = {
-   { SUF_W|SUF_Z, 0, CPU_286, 0, 0, {MOD_SpAdd, MOD_Op1Add, 0}, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 1, 22 },
-    { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_SpAdd, MOD_Op1Add, 0}, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 1, 50 },
+   { SUF_W|SUF_Z, 0, CPU_286, 0, 0, {MOD_SpAdd, MOD_Op1Add, 0}, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 1, 34 },
+    { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_SpAdd, MOD_Op1Add, 0}, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 1, 58 },
     { SUF_Q|SUF_Z, ONLY_64, CPU_286, 0, 0, {MOD_SpAdd, MOD_Op1Add, 0}, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 1, 6 },
-    { SUF_W|SUF_Z, 0, CPU_286, 0, 0, {MOD_SpAdd, MOD_Op1Add, 0}, 16, 0, 0, 2, {0x0F, 0x00, 0}, 0, 1, 347 },
-    { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_SpAdd, MOD_Op1Add, 0}, 32, 0, 0, 2, {0x0F, 0x00, 0}, 0, 1, 14 },
-    { SUF_Q|SUF_Z, ONLY_64, CPU_286, 0, 0, {MOD_SpAdd, MOD_Op1Add, 0}, 64, 0, 0, 2, {0x0F, 0x00, 0}, 0, 1, 18 }
+    { SUF_W|SUF_Z, 0, CPU_286, 0, 0, {MOD_SpAdd, MOD_Op1Add, 0}, 16, 0, 0, 2, {0x0F, 0x00, 0}, 0, 1, 389 },
+    { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_SpAdd, MOD_Op1Add, 0}, 32, 0, 0, 2, {0x0F, 0x00, 0}, 0, 1, 26 },
+    { SUF_Q|SUF_Z, ONLY_64, CPU_286, 0, 0, {MOD_SpAdd, MOD_Op1Add, 0}, 64, 0, 0, 2, {0x0F, 0x00, 0}, 0, 1, 30 }
 };
 
 static const x86_insn_info fld_insn[] = {
-   { SUF_S|SUF_Z, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xD9, 0, 0}, 0, 1, 578 },
-    { SUF_L|SUF_Z, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xDD, 0, 0}, 0, 1, 197 },
-    { SUF_Z, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xDB, 0, 0}, 5, 1, 580 },
-    { SUF_Z, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0xD9, 0xC0, 0}, 0, 1, 280 }
+   { SUF_S|SUF_Z, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xD9, 0, 0}, 0, 1, 648 },
+    { SUF_L|SUF_Z, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xDD, 0, 0}, 0, 1, 212 },
+    { SUF_Z, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xDB, 0, 0}, 5, 1, 650 },
+    { SUF_Z, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0xD9, 0xC0, 0}, 0, 1, 322 }
 };
 
 static const x86_insn_info fstp_insn[] = {
-   { SUF_S|SUF_Z, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xD9, 0, 0}, 3, 1, 578 },
-    { SUF_L|SUF_Z, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xDD, 0, 0}, 3, 1, 197 },
-    { SUF_Z, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xDB, 0, 0}, 7, 1, 580 },
-    { SUF_Z, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0xDD, 0xD8, 0}, 0, 1, 280 }
+   { SUF_S|SUF_Z, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xD9, 0, 0}, 3, 1, 648 },
+    { SUF_L|SUF_Z, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xDD, 0, 0}, 3, 1, 212 },
+    { SUF_Z, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xDB, 0, 0}, 7, 1, 650 },
+    { SUF_Z, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0xDD, 0xD8, 0}, 0, 1, 322 }
 };
 
 static const x86_insn_info fldstpt_insn[] = {
-   { SUF_Z, 0, CPU_FPU, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 1, {0xDB, 0, 0}, 0, 1, 498 }
+   { SUF_Z, 0, CPU_FPU, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 1, {0xDB, 0, 0}, 0, 1, 562 }
 };
 
 static const x86_insn_info fildstp_insn[] = {
-   { SUF_S|SUF_Z, 0, CPU_FPU, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 1, {0xDF, 0, 0}, 0, 1, 577 },
-    { SUF_L|SUF_Z, 0, CPU_FPU, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 1, {0xDB, 0, 0}, 0, 1, 578 },
-    { SUF_Q|SUF_Z, 0, CPU_FPU, 0, 0, {MOD_Gap, MOD_Op0Add, MOD_SpAdd}, 0, 0, 0, 1, {0xDD, 0, 0}, 0, 1, 197 },
-    { GAS_ONLY|SUF_Z, 0, CPU_FPU, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 1, {0xDF, 0, 0}, 0, 1, 22 }
+   { SUF_S|SUF_Z, 0, CPU_FPU, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 1, {0xDF, 0, 0}, 0, 1, 647 },
+    { SUF_L|SUF_Z, 0, CPU_FPU, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 1, {0xDB, 0, 0}, 0, 1, 648 },
+    { SUF_Q|SUF_Z, 0, CPU_FPU, 0, 0, {MOD_Gap, MOD_Op0Add, MOD_SpAdd}, 0, 0, 0, 1, {0xDD, 0, 0}, 0, 1, 212 },
+    { GAS_ONLY|SUF_Z, 0, CPU_FPU, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 1, {0xDF, 0, 0}, 0, 1, 34 }
 };
 
 static const x86_insn_info fbldstp_insn[] = {
-   { SUF_Z, 0, CPU_FPU, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 1, {0xDF, 0, 0}, 0, 1, 498 }
+   { SUF_Z, 0, CPU_FPU, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 1, {0xDF, 0, 0}, 0, 1, 562 }
 };
 
 static const x86_insn_info fst_insn[] = {
-   { SUF_S|SUF_Z, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xD9, 0, 0}, 2, 1, 578 },
-    { SUF_L|SUF_Z, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xDD, 0, 0}, 2, 1, 197 },
-    { SUF_Z, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0xDD, 0xD0, 0}, 0, 1, 280 }
+   { SUF_S|SUF_Z, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xD9, 0, 0}, 2, 1, 648 },
+    { SUF_L|SUF_Z, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xDD, 0, 0}, 2, 1, 212 },
+    { SUF_Z, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0xDD, 0xD0, 0}, 0, 1, 322 }
 };
 
 static const x86_insn_info fxch_insn[] = {
-   { SUF_Z, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0xD9, 0xC8, 0}, 0, 1, 280 },
-    { SUF_Z, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0xD9, 0xC8, 0}, 0, 2, 279 },
-    { SUF_Z, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0xD9, 0xC8, 0}, 0, 2, 281 },
+   { SUF_Z, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0xD9, 0xC8, 0}, 0, 1, 322 },
+    { SUF_Z, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0xD9, 0xC8, 0}, 0, 2, 321 },
+    { SUF_Z, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0xD9, 0xC8, 0}, 0, 2, 323 },
     { SUF_Z, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0xD9, 0xC9, 0}, 0, 0, 0 }
 };
 
 static const x86_insn_info fcom_insn[] = {
-   { SUF_S|SUF_Z, 0, CPU_FPU, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 0, 0, 0, 1, {0xD8, 0, 0}, 0, 1, 578 },
-    { SUF_L|SUF_Z, 0, CPU_FPU, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 0, 0, 0, 1, {0xDC, 0, 0}, 0, 1, 197 },
-    { SUF_Z, 0, CPU_FPU, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0xD8, 0x00, 0}, 0, 1, 280 },
-    { GAS_ONLY|SUF_Z, 0, CPU_FPU, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 0, 0, 0, 1, {0xD8, 0, 0}, 0, 1, 50 },
+   { SUF_S|SUF_Z, 0, CPU_FPU, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 0, 0, 0, 1, {0xD8, 0, 0}, 0, 1, 648 },
+    { SUF_L|SUF_Z, 0, CPU_FPU, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 0, 0, 0, 1, {0xDC, 0, 0}, 0, 1, 212 },
+    { SUF_Z, 0, CPU_FPU, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0xD8, 0x00, 0}, 0, 1, 322 },
+    { GAS_ONLY|SUF_Z, 0, CPU_FPU, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 0, 0, 0, 1, {0xD8, 0, 0}, 0, 1, 58 },
     { GAS_ONLY|SUF_Z, 0, CPU_FPU, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0xD8, 0x01, 0}, 0, 0, 0 },
-    { GAS_ILLEGAL|SUF_Z, 0, CPU_FPU, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0xD8, 0x00, 0}, 0, 2, 279 }
+    { GAS_ILLEGAL|SUF_Z, 0, CPU_FPU, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0xD8, 0x00, 0}, 0, 2, 321 }
 };
 
 static const x86_insn_info fcom2_insn[] = {
-   { SUF_Z, 0, CPU_286, CPU_FPU, 0, {MOD_Op0Add, MOD_Op1Add, 0}, 0, 0, 0, 2, {0x00, 0x00, 0}, 0, 1, 280 },
-    { SUF_Z, 0, CPU_286, CPU_FPU, 0, {MOD_Op0Add, MOD_Op1Add, 0}, 0, 0, 0, 2, {0x00, 0x00, 0}, 0, 2, 279 }
+   { SUF_Z, 0, CPU_286, CPU_FPU, 0, {MOD_Op0Add, MOD_Op1Add, 0}, 0, 0, 0, 2, {0x00, 0x00, 0}, 0, 1, 322 },
+    { SUF_Z, 0, CPU_286, CPU_FPU, 0, {MOD_Op0Add, MOD_Op1Add, 0}, 0, 0, 0, 2, {0x00, 0x00, 0}, 0, 2, 321 }
 };
 
 static const x86_insn_info farith_insn[] = {
-   { SUF_S|SUF_Z, 0, CPU_FPU, 0, 0, {MOD_Gap, MOD_Gap, MOD_SpAdd}, 0, 0, 0, 1, {0xD8, 0, 0}, 0, 1, 578 },
-    { SUF_L|SUF_Z, 0, CPU_FPU, 0, 0, {MOD_Gap, MOD_Gap, MOD_SpAdd}, 0, 0, 0, 1, {0xDC, 0, 0}, 0, 1, 197 },
-    { SUF_Z, 0, CPU_FPU, 0, 0, {MOD_Gap, MOD_Op1Add, 0}, 0, 0, 0, 2, {0xD8, 0x00, 0}, 0, 1, 280 },
-    { SUF_Z, 0, CPU_FPU, 0, 0, {MOD_Gap, MOD_Op1Add, 0}, 0, 0, 0, 2, {0xD8, 0x00, 0}, 0, 2, 279 },
-    { SUF_Z, 0, CPU_FPU, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0xDC, 0x00, 0}, 0, 1, 618 },
-    { GAS_ILLEGAL|SUF_Z, 0, CPU_FPU, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0xDC, 0x00, 0}, 0, 2, 281 },
-    { GAS_ONLY|SUF_Z, 0, CPU_FPU, 0, 0, {MOD_Gap, MOD_Op1Add, 0}, 0, 0, 0, 2, {0xDC, 0x00, 0}, 0, 2, 281 }
+   { SUF_S|SUF_Z, 0, CPU_FPU, 0, 0, {MOD_Gap, MOD_Gap, MOD_SpAdd}, 0, 0, 0, 1, {0xD8, 0, 0}, 0, 1, 648 },
+    { SUF_L|SUF_Z, 0, CPU_FPU, 0, 0, {MOD_Gap, MOD_Gap, MOD_SpAdd}, 0, 0, 0, 1, {0xDC, 0, 0}, 0, 1, 212 },
+    { SUF_Z, 0, CPU_FPU, 0, 0, {MOD_Gap, MOD_Op1Add, 0}, 0, 0, 0, 2, {0xD8, 0x00, 0}, 0, 1, 322 },
+    { SUF_Z, 0, CPU_FPU, 0, 0, {MOD_Gap, MOD_Op1Add, 0}, 0, 0, 0, 2, {0xD8, 0x00, 0}, 0, 2, 321 },
+    { SUF_Z, 0, CPU_FPU, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0xDC, 0x00, 0}, 0, 1, 690 },
+    { GAS_ILLEGAL|SUF_Z, 0, CPU_FPU, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0xDC, 0x00, 0}, 0, 2, 323 },
+    { GAS_ONLY|SUF_Z, 0, CPU_FPU, 0, 0, {MOD_Gap, MOD_Op1Add, 0}, 0, 0, 0, 2, {0xDC, 0x00, 0}, 0, 2, 323 }
 };
 
 static const x86_insn_info farithp_insn[] = {
    { SUF_Z, 0, CPU_FPU, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0xDE, 0x01, 0}, 0, 0, 0 },
-    { SUF_Z, 0, CPU_FPU, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0xDE, 0x00, 0}, 0, 1, 280 },
-    { SUF_Z, 0, CPU_FPU, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0xDE, 0x00, 0}, 0, 2, 281 }
+    { SUF_Z, 0, CPU_FPU, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0xDE, 0x00, 0}, 0, 1, 322 },
+    { SUF_Z, 0, CPU_FPU, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0xDE, 0x00, 0}, 0, 2, 323 }
 };
 
 static const x86_insn_info fiarith_insn[] = {
-   { SUF_S|SUF_Z, 0, CPU_FPU, 0, 0, {MOD_SpAdd, MOD_Op0Add, 0}, 0, 0, 0, 1, {0x04, 0, 0}, 0, 1, 577 },
-    { SUF_L|SUF_Z, 0, CPU_FPU, 0, 0, {MOD_SpAdd, MOD_Op0Add, 0}, 0, 0, 0, 1, {0x00, 0, 0}, 0, 1, 578 }
+   { SUF_S|SUF_Z, 0, CPU_FPU, 0, 0, {MOD_SpAdd, MOD_Op0Add, 0}, 0, 0, 0, 1, {0x04, 0, 0}, 0, 1, 647 },
+    { SUF_L|SUF_Z, 0, CPU_FPU, 0, 0, {MOD_SpAdd, MOD_Op0Add, 0}, 0, 0, 0, 1, {0x00, 0, 0}, 0, 1, 648 }
 };
 
 static const x86_insn_info fldnstcw_insn[] = {
-   { SUF_W|SUF_Z, 0, CPU_FPU, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 1, {0xD9, 0, 0}, 0, 1, 22 }
+   { SUF_W|SUF_Z, 0, CPU_FPU, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 1, {0xD9, 0, 0}, 0, 1, 34 }
 };
 
 static const x86_insn_info fstcw_insn[] = {
-   { SUF_W|SUF_Z, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x9B, 0xD9, 0}, 7, 1, 22 }
+   { SUF_W|SUF_Z, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x9B, 0xD9, 0}, 7, 1, 34 }
 };
 
 static const x86_insn_info fnstsw_insn[] = {
-   { SUF_W|SUF_Z, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xDD, 0, 0}, 7, 1, 22 },
-    { SUF_W|SUF_Z, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0xDF, 0xE0, 0}, 0, 1, 295 }
+   { SUF_W|SUF_Z, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xDD, 0, 0}, 7, 1, 34 },
+    { SUF_W|SUF_Z, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0xDF, 0xE0, 0}, 0, 1, 337 }
 };
 
 static const x86_insn_info fstsw_insn[] = {
-   { SUF_W|SUF_Z, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x9B, 0xDD, 0}, 7, 1, 22 },
-    { SUF_W|SUF_Z, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 3, {0x9B, 0xDF, 0xE0}, 0, 1, 295 }
+   { SUF_W|SUF_Z, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x9B, 0xDD, 0}, 7, 1, 34 },
+    { SUF_W|SUF_Z, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 3, {0x9B, 0xDF, 0xE0}, 0, 1, 337 }
 };
 
 static const x86_insn_info ffree_insn[] = {
-   { SUF_Z, 0, CPU_FPU, 0, 0, {MOD_Op0Add, 0, 0}, 0, 0, 0, 2, {0x00, 0xC0, 0}, 0, 1, 280 }
+   { SUF_Z, 0, CPU_FPU, 0, 0, {MOD_Op0Add, 0, 0}, 0, 0, 0, 2, {0x00, 0xC0, 0}, 0, 1, 322 }
 };
 
 static const x86_insn_info bswap_insn[] = {
-   { SUF_L|SUF_Z, 0, CPU_486, 0, 0, {0, 0, 0}, 32, 0, 0, 2, {0x0F, 0xC8, 0}, 0, 1, 619 },
-    { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 2, {0x0F, 0xC8, 0}, 0, 1, 620 }
+   { SUF_L|SUF_Z, 0, CPU_486, 0, 0, {0, 0, 0}, 32, 0, 0, 2, {0x0F, 0xC8, 0}, 0, 1, 691 },
+    { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 2, {0x0F, 0xC8, 0}, 0, 1, 692 }
 };
 
 static const x86_insn_info cmpxchgxadd_insn[] = {
-   { SUF_B|SUF_Z, 0, CPU_486, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 275 },
-    { SUF_W|SUF_Z, 0, CPU_486, 0, 0, {MOD_Op1Add, 0, 0}, 16, 0, 0, 2, {0x0F, 0x01, 0}, 0, 2, 212 },
-    { SUF_L|SUF_Z, 0, CPU_486, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 2, {0x0F, 0x01, 0}, 0, 2, 218 },
-    { SUF_Q|SUF_Z, ONLY_64, CPU_486, 0, 0, {MOD_Op1Add, 0, 0}, 64, 0, 0, 2, {0x0F, 0x01, 0}, 0, 2, 224 }
+   { SUF_B|SUF_Z, 0, CPU_486, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 317 },
+    { SUF_W|SUF_Z, 0, CPU_486, 0, 0, {MOD_Op1Add, 0, 0}, 16, 0, 0, 2, {0x0F, 0x01, 0}, 0, 2, 254 },
+    { SUF_L|SUF_Z, 0, CPU_486, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 2, {0x0F, 0x01, 0}, 0, 2, 260 },
+    { SUF_Q|SUF_Z, ONLY_64, CPU_486, 0, 0, {MOD_Op1Add, 0, 0}, 64, 0, 0, 2, {0x0F, 0x01, 0}, 0, 2, 266 }
 };
 
 static const x86_insn_info cmpxchg8b_insn[] = {
@@ -1349,148 +1435,165 @@ static const x86_insn_info cmovcc_insn[] = {
 };
 
 static const x86_insn_info fcmovcc_insn[] = {
-   { SUF_Z, 0, CPU_686, CPU_FPU, 0, {MOD_Op0Add, MOD_Op1Add, 0}, 0, 0, 0, 2, {0x00, 0x00, 0}, 0, 2, 279 }
+   { SUF_Z, 0, CPU_686, CPU_FPU, 0, {MOD_Op0Add, MOD_Op1Add, 0}, 0, 0, 0, 2, {0x00, 0x00, 0}, 0, 2, 321 }
 };
 
 static const x86_insn_info movnti_insn[] = {
-   { SUF_L|SUF_Z, 0, CPU_P4, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0xC3, 0}, 0, 2, 289 },
-    { SUF_Q|SUF_Z, ONLY_64, CPU_P4, 0, 0, {0, 0, 0}, 64, 0, 0, 2, {0x0F, 0xC3, 0}, 0, 2, 291 }
+   { SUF_L|SUF_Z, 0, CPU_P4, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0xC3, 0}, 0, 2, 331 },
+    { SUF_Q|SUF_Z, ONLY_64, CPU_P4, 0, 0, {0, 0, 0}, 64, 0, 0, 2, {0x0F, 0xC3, 0}, 0, 2, 333 }
 };
 
 static const x86_insn_info clflush_insn[] = {
-   { SUF_Z, 0, CPU_P3, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0xAE, 0}, 7, 1, 42 }
+   { SUF_Z, 0, CPU_P3, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0xAE, 0}, 7, 1, 50 }
 };
 
 static const x86_insn_info movd_insn[] = {
-   { SUF_Z, 0, CPU_386, CPU_MMX, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x6E, 0}, 0, 2, 245 },
-    { SUF_Z, ONLY_64, CPU_MMX, 0, 0, {0, 0, 0}, 64, 0, 0, 2, {0x0F, 0x6E, 0}, 0, 2, 247 },
-    { SUF_Z, 0, CPU_386, CPU_MMX, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x7E, 0}, 0, 2, 246 },
-    { SUF_Z, ONLY_64, CPU_MMX, 0, 0, {0, 0, 0}, 64, 0, 0, 2, {0x0F, 0x7E, 0}, 0, 2, 249 },
-    { SUF_Z, 0, CPU_386, CPU_SSE2, 0, {0, 0, 0}, 0, 0, 0x66, 2, {0x0F, 0x6E, 0}, 0, 2, 251 },
-    { SUF_Z, ONLY_64, CPU_SSE2, 0, 0, {0, 0, 0}, 64, 0, 0x66, 2, {0x0F, 0x6E, 0}, 0, 2, 253 },
-    { SUF_Z, 0, CPU_386, CPU_SSE2, 0, {0, 0, 0}, 0, 0, 0x66, 2, {0x0F, 0x7E, 0}, 0, 2, 173 },
-    { SUF_Z, ONLY_64, CPU_SSE2, 0, 0, {0, 0, 0}, 64, 0, 0x66, 2, {0x0F, 0x7E, 0}, 0, 2, 167 }
+   { SUF_Z, 0, CPU_386, CPU_MMX, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x6E, 0}, 0, 2, 287 },
+    { SUF_Z, ONLY_64, CPU_MMX, 0, 0, {0, 0, 0}, 64, 0, 0, 2, {0x0F, 0x6E, 0}, 0, 2, 289 },
+    { SUF_Z, 0, CPU_386, CPU_MMX, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x7E, 0}, 0, 2, 288 },
+    { SUF_Z, ONLY_64, CPU_MMX, 0, 0, {0, 0, 0}, 64, 0, 0, 2, {0x0F, 0x7E, 0}, 0, 2, 291 },
+    { SUF_Z, 0, CPU_386, CPU_SSE2, 0, {0, 0, 0}, 0, 0, 0x66, 2, {0x0F, 0x6E, 0}, 0, 2, 293 },
+    { SUF_Z, ONLY_64, CPU_SSE2, 0, 0, {0, 0, 0}, 64, 0, 0x66, 2, {0x0F, 0x6E, 0}, 0, 2, 295 },
+    { SUF_Z, 0, CPU_386, CPU_SSE2, 0, {0, 0, 0}, 0, 0, 0x66, 2, {0x0F, 0x7E, 0}, 0, 2, 188 },
+    { SUF_Z, ONLY_64, CPU_SSE2, 0, 0, {0, 0, 0}, 64, 0, 0x66, 2, {0x0F, 0x7E, 0}, 0, 2, 182 }
 };
 
 static const x86_insn_info movq_insn[] = {
-   { GAS_ILLEGAL|SUF_Z, 0, CPU_MMX, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x6F, 0}, 0, 2, 185 },
-    { GAS_ILLEGAL|SUF_Z, ONLY_64, CPU_MMX, 0, 0, {0, 0, 0}, 64, 0, 0, 2, {0x0F, 0x6E, 0}, 0, 2, 247 },
-    { GAS_ILLEGAL|SUF_Z, 0, CPU_MMX, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x7F, 0}, 0, 2, 283 },
-    { GAS_ILLEGAL|SUF_Z, ONLY_64, CPU_MMX, 0, 0, {0, 0, 0}, 64, 0, 0, 2, {0x0F, 0x7E, 0}, 0, 2, 249 },
-    { GAS_ILLEGAL|SUF_Z, 0, CPU_SSE2, 0, 0, {0, 0, 0}, 0, 0, 0xF3, 2, {0x0F, 0x7E, 0}, 0, 2, 88 },
-    { GAS_ILLEGAL|SUF_Z, 0, CPU_SSE2, 0, 0, {0, 0, 0}, 0, 0, 0xF3, 2, {0x0F, 0x7E, 0}, 0, 2, 285 },
-    { GAS_ILLEGAL|SUF_Z, ONLY_64, CPU_SSE2, 0, 0, {0, 0, 0}, 64, 0, 0x66, 2, {0x0F, 0x6E, 0}, 0, 2, 253 },
-    { GAS_ILLEGAL|SUF_Z, 0, CPU_SSE2, 0, 0, {0, 0, 0}, 0, 0, 0x66, 2, {0x0F, 0xD6, 0}, 0, 2, 287 },
-    { GAS_ILLEGAL|SUF_Z, ONLY_64, CPU_SSE2, 0, 0, {0, 0, 0}, 64, 0, 0x66, 2, {0x0F, 0x7E, 0}, 0, 2, 167 }
+   { GAS_ILLEGAL|SUF_Z, 0, CPU_MMX, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x6F, 0}, 0, 2, 140 },
+    { GAS_ILLEGAL|SUF_Z, ONLY_64, CPU_MMX, 0, 0, {0, 0, 0}, 64, 0, 0, 2, {0x0F, 0x6E, 0}, 0, 2, 289 },
+    { GAS_ILLEGAL|SUF_Z, 0, CPU_MMX, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x7F, 0}, 0, 2, 325 },
+    { GAS_ILLEGAL|SUF_Z, ONLY_64, CPU_MMX, 0, 0, {0, 0, 0}, 64, 0, 0, 2, {0x0F, 0x7E, 0}, 0, 2, 291 },
+    { GAS_ILLEGAL|SUF_Z, 0, CPU_SSE2, 0, 0, {0, 0, 0}, 0, 0, 0xF3, 2, {0x0F, 0x7E, 0}, 0, 2, 64 },
+    { GAS_ILLEGAL|SUF_Z, 0, CPU_SSE2, 0, 0, {0, 0, 0}, 0, 0, 0xF3, 2, {0x0F, 0x7E, 0}, 0, 2, 327 },
+    { GAS_ILLEGAL|SUF_Z, ONLY_64, CPU_SSE2, 0, 0, {0, 0, 0}, 64, 0, 0x66, 2, {0x0F, 0x6E, 0}, 0, 2, 295 },
+    { GAS_ILLEGAL|SUF_Z, 0, CPU_SSE2, 0, 0, {0, 0, 0}, 0, 0, 0x66, 2, {0x0F, 0xD6, 0}, 0, 2, 329 },
+    { GAS_ILLEGAL|SUF_Z, ONLY_64, CPU_SSE2, 0, 0, {0, 0, 0}, 64, 0, 0x66, 2, {0x0F, 0x7E, 0}, 0, 2, 182 }
 };
 
 static const x86_insn_info mmxsse2_insn[] = {
-   { SUF_Z, 0, CPU_MMX, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 185 },
-    { SUF_Z, 0, CPU_SSE2, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0x66, 2, {0x0F, 0x00, 0}, 0, 2, 170 }
+   { SUF_Z, 0, CPU_MMX, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 140 },
+    { SUF_Z, 0, CPU_SSE2, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0x66, 2, {0x0F, 0x00, 0}, 0, 2, 155 }
 };
 
 static const x86_insn_info pshift_insn[] = {
-   { SUF_Z, 0, CPU_MMX, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 185 },
-    { SUF_Z, 0, CPU_MMX, 0, 0, {MOD_Gap, MOD_Op1Add, MOD_SpAdd}, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 147 },
-    { SUF_Z, 0, CPU_SSE2, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0x66, 2, {0x0F, 0x00, 0}, 0, 2, 170 },
+   { SUF_Z, 0, CPU_MMX, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 140 },
+    { SUF_Z, 0, CPU_MMX, 0, 0, {MOD_Gap, MOD_Op1Add, MOD_SpAdd}, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 162 },
+    { SUF_Z, 0, CPU_SSE2, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0x66, 2, {0x0F, 0x00, 0}, 0, 2, 155 },
     { SUF_Z, 0, CPU_SSE2, 0, 0, {MOD_Gap, MOD_Op1Add, MOD_SpAdd}, 0, 0, 0x66, 2, {0x0F, 0x00, 0}, 0, 2, 2 }
 };
 
 static const x86_insn_info vpshift_insn[] = {
-   { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0xC1, 2, {0x0F, 0x00, 0}, 0, 2, 143 },
-    { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Gap, MOD_Op1Add, MOD_SpAdd}, 0, 0, 0xC1, 2, {0x0F, 0x00, 0}, 0, 2, 451 },
-    { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0xC1, 2, {0x0F, 0x00, 0}, 0, 3, 52 },
-    { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Gap, MOD_Op1Add, MOD_SpAdd}, 0, 0, 0xC1, 2, {0x0F, 0x00, 0}, 0, 3, 1 }
+   { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0xC1, 2, {0x0F, 0x00, 0}, 0, 2, 158 },
+    { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Gap, MOD_Op1Add, MOD_SpAdd}, 0, 0, 0xC1, 2, {0x0F, 0x00, 0}, 0, 2, 505 },
+    { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0xC1, 2, {0x0F, 0x00, 0}, 0, 3, 12 },
+    { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Gap, MOD_Op1Add, MOD_SpAdd}, 0, 0, 0xC1, 2, {0x0F, 0x00, 0}, 0, 3, 1 },
+    { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0xC5, 2, {0x0F, 0x00, 0}, 0, 2, 633 },
+    { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {MOD_Gap, MOD_Op1Add, MOD_SpAdd}, 0, 0, 0xC5, 2, {0x0F, 0x00, 0}, 0, 2, 507 },
+    { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0xC5, 2, {0x0F, 0x00, 0}, 0, 3, 8 },
+    { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {MOD_Gap, MOD_Op1Add, MOD_SpAdd}, 0, 0, 0xC5, 2, {0x0F, 0x00, 0}, 0, 3, 200 }
 };
 
 static const x86_insn_info xmm_xmm128_256_insn[] = {
-   { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 143 },
-    { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 3, 52 },
-    { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC4, 2, {0x0F, 0x00, 0}, 0, 3, 8 }
+   { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 158 },
+    { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 3, 12 },
+    { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC4, 2, {0x0F, 0x00, 0}, 0, 2, 197 },
+    { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC4, 2, {0x0F, 0x00, 0}, 0, 3, 16 }
+};
+
+static const x86_insn_info xmm_xmm128_256avx2_insn[] = {
+   { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 158 },
+    { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 3, 12 },
+    { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC4, 2, {0x0F, 0x00, 0}, 0, 2, 197 },
+    { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC4, 2, {0x0F, 0x00, 0}, 0, 3, 16 }
 };
 
 static const x86_insn_info xmm_xmm128_insn[] = {
-   { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 143 },
-    { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 3, 52 }
+   { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 158 },
+    { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 3, 12 }
 };
 
 static const x86_insn_info cvt_rx_xmm32_insn[] = {
-   { SUF_L|SUF_Z, 0, CPU_386, CPU_SSE, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 149 },
-    { SUF_L|SUF_Z, 0, CPU_386, CPU_SSE, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 311 },
-    { SUF_Q|SUF_Z, ONLY_64, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 64, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 155 },
-    { SUF_Q|SUF_Z, ONLY_64, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 64, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 313 }
+   { SUF_L|SUF_Z, 0, CPU_386, CPU_SSE, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 164 },
+    { SUF_L|SUF_Z, 0, CPU_386, CPU_SSE, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 353 },
+    { SUF_Q|SUF_Z, ONLY_64, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 64, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 170 },
+    { SUF_Q|SUF_Z, ONLY_64, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 64, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 355 }
 };
 
 static const x86_insn_info cvt_mm_xmm64_insn[] = {
-   { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 267 },
-    { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 269 }
+   { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 309 },
+    { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 311 }
 };
 
 static const x86_insn_info cvt_xmm_mm_ps_insn[] = {
-   { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 285 }
+   { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 327 }
 };
 
 static const x86_insn_info cvt_xmm_rmx_insn[] = {
-   { SUF_L|SUF_Z, 0, CPU_386, CPU_SSE, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 573 },
-    { SUF_L|SUF_Z, NOT_64, CPU_386, CPU_SSE, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 134 },
-    { SUF_Q|SUF_Z, ONLY_64, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 64, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 575 },
-    { SUF_L|SUF_Z, ONLY_AVX|NOT_64, CPU_386, CPU_AVX, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 3, 24 },
-    { SUF_L|SUF_Z, ONLY_AVX, CPU_386, CPU_AVX, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 3, 233 },
-    { SUF_Q|SUF_Z, ONLY_64|ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 64, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 3, 236 }
+   { SUF_L|SUF_Z, 0, CPU_386, CPU_SSE, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 643 },
+    { SUF_L|SUF_Z, NOT_64, CPU_386, CPU_SSE, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 233 },
+    { SUF_Q|SUF_Z, ONLY_64, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 64, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 645 },
+    { SUF_L|SUF_Z, ONLY_AVX|NOT_64, CPU_386, CPU_AVX, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 3, 88 },
+    { SUF_L|SUF_Z, ONLY_AVX, CPU_386, CPU_AVX, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 3, 275 },
+    { SUF_Q|SUF_Z, ONLY_64|ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 64, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 3, 278 }
 };
 
 static const x86_insn_info xmm_xmm32_insn[] = {
    { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 92 },
-    { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 140 },
+    { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 146 },
     { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 3, 0 },
-    { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 3, 48 }
+    { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 3, 56 }
 };
 
 static const x86_insn_info ssecmp_128_insn[] = {
-   { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_Imm8, MOD_PreAdd, MOD_SetVEX}, 0, 0, 0, 2, {0x0F, 0xC2, 0}, 0, 2, 143 },
-    { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Imm8, MOD_PreAdd, 0}, 0, 0, 0xC0, 2, {0x0F, 0xC2, 0}, 0, 3, 52 },
-    { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Imm8, MOD_PreAdd, 0}, 0, 0, 0xC4, 2, {0x0F, 0xC2, 0}, 0, 3, 8 }
+   { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_Imm8, MOD_PreAdd, MOD_SetVEX}, 0, 0, 0, 2, {0x0F, 0xC2, 0}, 0, 2, 158 },
+    { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Imm8, MOD_PreAdd, 0}, 0, 0, 0xC0, 2, {0x0F, 0xC2, 0}, 0, 3, 12 },
+    { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Imm8, MOD_PreAdd, 0}, 0, 0, 0xC4, 2, {0x0F, 0xC2, 0}, 0, 3, 16 }
 };
 
 static const x86_insn_info ssecmp_32_insn[] = {
    { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_Imm8, MOD_PreAdd, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0xC2, 0}, 0, 2, 92 },
-    { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_Imm8, MOD_PreAdd, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0xC2, 0}, 0, 2, 140 },
+    { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_Imm8, MOD_PreAdd, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0xC2, 0}, 0, 2, 146 },
     { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Imm8, MOD_PreAdd, 0}, 0, 0, 0xC0, 2, {0x0F, 0xC2, 0}, 0, 3, 0 },
-    { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Imm8, MOD_PreAdd, 0}, 0, 0, 0xC0, 2, {0x0F, 0xC2, 0}, 0, 3, 48 }
+    { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Imm8, MOD_PreAdd, 0}, 0, 0, 0xC0, 2, {0x0F, 0xC2, 0}, 0, 3, 56 }
 };
 
 static const x86_insn_info xmm_xmm128_imm_insn[] = {
-   { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 3, 170 }
+   { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 3, 185 }
+};
+
+static const x86_insn_info xmm_xmm128_imm_256avx2_insn[] = {
+   { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 3, 185 },
+    { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC4, 2, {0x0F, 0x00, 0}, 0, 3, 191 }
 };
 
 static const x86_insn_info xmm_xmm128_imm_256_insn[] = {
-   { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 3, 143 },
-    { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 4, 52 },
-    { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC4, 2, {0x0F, 0x00, 0}, 0, 4, 8 }
+   { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 3, 158 },
+    { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 4, 60 },
+    { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC4, 2, {0x0F, 0x00, 0}, 0, 4, 20 }
 };
 
 static const x86_insn_info xmm_xmm32_imm_insn[] = {
    { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 3, 92 },
-    { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 3, 140 },
+    { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 3, 146 },
     { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 4, 0 },
-    { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 4, 48 }
+    { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 4, 56 }
 };
 
 static const x86_insn_info ldstmxcsr_insn[] = {
-   { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_SpAdd, MOD_SetVEX, 0}, 0, 0, 0, 2, {0x0F, 0xAE, 0}, 0, 1, 50 }
+   { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_SpAdd, MOD_SetVEX, 0}, 0, 0, 0, 2, {0x0F, 0xAE, 0}, 0, 1, 58 }
 };
 
 static const x86_insn_info maskmovq_insn[] = {
-   { SUF_Z, 0, CPU_MMX, CPU_P3, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0xF7, 0}, 0, 2, 567 }
+   { SUF_Z, 0, CPU_MMX, CPU_P3, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0xF7, 0}, 0, 2, 635 }
 };
 
 static const x86_insn_info movau_insn[] = {
-   { SUF_Z, NOT_AVX, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 170 },
-    { SUF_Z, NOT_AVX, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_Op1Add}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 425 },
-    { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 2, 170 },
-    { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_Op1Add}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 2, 425 },
-    { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC4, 2, {0x0F, 0x00, 0}, 0, 2, 176 },
-    { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_Op1Add}, 0, 0, 0xC4, 2, {0x0F, 0x00, 0}, 0, 2, 427 }
+   { SUF_Z, NOT_AVX, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 155 },
+    { SUF_Z, NOT_AVX, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_Op1Add}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 479 },
+    { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 2, 155 },
+    { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_Op1Add}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 2, 479 },
+    { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC4, 2, {0x0F, 0x00, 0}, 0, 2, 191 },
+    { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_Op1Add}, 0, 0, 0xC4, 2, {0x0F, 0x00, 0}, 0, 2, 481 }
 };
 
 static const x86_insn_info movhllhps_insn[] = {
@@ -1500,41 +1603,41 @@ static const x86_insn_info movhllhps_insn[] = {
 
 static const x86_insn_info movhlp_insn[] = {
    { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 95 },
-    { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0x01, 0}, 0, 2, 39 },
+    { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0x01, 0}, 0, 2, 47 },
     { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 3, 4 }
 };
 
 static const x86_insn_info movmsk_insn[] = {
-   { SUF_L|SUF_Z, 0, CPU_386, CPU_SSE, 0, {MOD_PreAdd, MOD_SetVEX, 0}, 0, 0, 0x00, 2, {0x0F, 0x50, 0}, 0, 2, 149 },
-    { SUF_Q|SUF_Z, ONLY_64, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_SetVEX, 0}, 64, 0, 0x00, 2, {0x0F, 0x50, 0}, 0, 2, 155 },
-    { SUF_L|SUF_Z, ONLY_AVX, CPU_386, CPU_AVX, 0, {MOD_PreAdd, 0, 0}, 0, 0, 0xC4, 2, {0x0F, 0x50, 0}, 0, 2, 271 },
-    { SUF_Q|SUF_Z, ONLY_64|ONLY_AVX, CPU_SSE, 0, 0, {MOD_PreAdd, 0, 0}, 64, 0, 0xC4, 2, {0x0F, 0x50, 0}, 0, 2, 273 }
+   { SUF_L|SUF_Z, 0, CPU_386, CPU_SSE, 0, {MOD_PreAdd, MOD_SetVEX, 0}, 0, 0, 0x00, 2, {0x0F, 0x50, 0}, 0, 2, 164 },
+    { SUF_Q|SUF_Z, ONLY_64, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_SetVEX, 0}, 64, 0, 0x00, 2, {0x0F, 0x50, 0}, 0, 2, 170 },
+    { SUF_L|SUF_Z, ONLY_AVX, CPU_386, CPU_AVX, 0, {MOD_PreAdd, 0, 0}, 0, 0, 0xC4, 2, {0x0F, 0x50, 0}, 0, 2, 313 },
+    { SUF_Q|SUF_Z, ONLY_64|ONLY_AVX, CPU_SSE, 0, 0, {MOD_PreAdd, 0, 0}, 64, 0, 0xC4, 2, {0x0F, 0x50, 0}, 0, 2, 315 }
 };
 
 static const x86_insn_info movnt_insn[] = {
-   { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 531 },
-    { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC4, 2, {0x0F, 0x00, 0}, 0, 2, 533 }
+   { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 595 },
+    { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC4, 2, {0x0F, 0x00, 0}, 0, 2, 597 }
 };
 
 static const x86_insn_info movntq_insn[] = {
-   { SUF_Z, 0, CPU_SSE, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0xE7, 0}, 0, 2, 315 }
+   { SUF_Z, 0, CPU_SSE, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0xE7, 0}, 0, 2, 357 }
 };
 
 static const x86_insn_info movss_insn[] = {
    { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0xF3, 2, {0x0F, 0x10, 0}, 0, 2, 92 },
-    { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0xF3, 2, {0x0F, 0x10, 0}, 0, 2, 288 },
-    { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0xF3, 2, {0x0F, 0x11, 0}, 0, 2, 529 },
+    { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0xF3, 2, {0x0F, 0x10, 0}, 0, 2, 330 },
+    { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0xF3, 2, {0x0F, 0x11, 0}, 0, 2, 444 },
     { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC2, 2, {0x0F, 0x10, 0}, 0, 3, 0 }
 };
 
 static const x86_insn_info pextrw_insn[] = {
-   { SUF_L|SUF_Z, NOT_AVX, CPU_MMX, CPU_P3, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0xC5, 0}, 0, 3, 146 },
-    { SUF_L|SUF_Z, 0, CPU_386, CPU_SSE2, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 2, {0x0F, 0xC5, 0}, 0, 3, 149 },
-    { SUF_Q|SUF_Z, ONLY_64|NOT_AVX, CPU_MMX, CPU_P3, 0, {0, 0, 0}, 64, 0, 0, 2, {0x0F, 0xC5, 0}, 0, 3, 152 },
-    { SUF_Q|SUF_Z, ONLY_64, CPU_SSE2, 0, 0, {MOD_SetVEX, 0, 0}, 64, 0, 0x66, 2, {0x0F, 0xC5, 0}, 0, 3, 155 },
-    { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x15}, 0, 3, 158 },
-    { SUF_Z, 0, CPU_386, CPU_SSE41, 0, {MOD_SetVEX, 0, 0}, 32, 0, 0x66, 3, {0x0F, 0x3A, 0x15}, 0, 3, 161 },
-    { SUF_Z, ONLY_64, CPU_SSE41, 0, 0, {MOD_SetVEX, 0, 0}, 64, 0, 0x66, 3, {0x0F, 0x3A, 0x15}, 0, 3, 164 }
+   { SUF_L|SUF_Z, NOT_AVX, CPU_MMX, CPU_P3, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0xC5, 0}, 0, 3, 161 },
+    { SUF_L|SUF_Z, 0, CPU_386, CPU_SSE2, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 2, {0x0F, 0xC5, 0}, 0, 3, 164 },
+    { SUF_Q|SUF_Z, ONLY_64|NOT_AVX, CPU_MMX, CPU_P3, 0, {0, 0, 0}, 64, 0, 0, 2, {0x0F, 0xC5, 0}, 0, 3, 167 },
+    { SUF_Q|SUF_Z, ONLY_64, CPU_SSE2, 0, 0, {MOD_SetVEX, 0, 0}, 64, 0, 0x66, 2, {0x0F, 0xC5, 0}, 0, 3, 170 },
+    { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x15}, 0, 3, 173 },
+    { SUF_Z, 0, CPU_386, CPU_SSE41, 0, {MOD_SetVEX, 0, 0}, 32, 0, 0x66, 3, {0x0F, 0x3A, 0x15}, 0, 3, 176 },
+    { SUF_Z, ONLY_64, CPU_SSE41, 0, 0, {MOD_SetVEX, 0, 0}, 64, 0, 0x66, 3, {0x0F, 0x3A, 0x15}, 0, 3, 179 }
 };
 
 static const x86_insn_info pinsrw_insn[] = {
@@ -1544,20 +1647,22 @@ static const x86_insn_info pinsrw_insn[] = {
     { SUF_L|SUF_Z, 0, CPU_386, CPU_SSE2, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 2, {0x0F, 0xC4, 0}, 0, 3, 125 },
     { SUF_Q|SUF_Z, ONLY_64, CPU_SSE2, 0, 0, {MOD_SetVEX, 0, 0}, 64, 64, 0x66, 2, {0x0F, 0xC4, 0}, 0, 3, 128 },
     { SUF_L|SUF_Z, 0, CPU_SSE2, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 2, {0x0F, 0xC4, 0}, 0, 3, 131 },
-    { SUF_L|SUF_Z, ONLY_AVX, CPU_386, CPU_AVX, 0, {0, 0, 0}, 0, 0, 0xC1, 2, {0x0F, 0xC4, 0}, 0, 4, 12 },
-    { SUF_Q|SUF_Z, ONLY_64|ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 64, 64, 0xC1, 2, {0x0F, 0xC4, 0}, 0, 4, 16 },
-    { SUF_L|SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC1, 2, {0x0F, 0xC4, 0}, 0, 4, 20 }
+    { SUF_L|SUF_Z, ONLY_AVX, CPU_386, CPU_AVX, 0, {0, 0, 0}, 0, 0, 0xC1, 2, {0x0F, 0xC4, 0}, 0, 4, 24 },
+    { SUF_Q|SUF_Z, ONLY_64|ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 64, 64, 0xC1, 2, {0x0F, 0xC4, 0}, 0, 4, 28 },
+    { SUF_L|SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC1, 2, {0x0F, 0xC4, 0}, 0, 4, 32 }
 };
 
 static const x86_insn_info pmovmskb_insn[] = {
-   { SUF_L|SUF_Z, NOT_AVX, CPU_MMX, CPU_P3, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0xD7, 0}, 0, 2, 146 },
-    { SUF_L|SUF_Z, 0, CPU_386, CPU_SSE2, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 2, {0x0F, 0xD7, 0}, 0, 2, 149 },
-    { SUF_Q|SUF_Z, ONLY_64|NOT_AVX, CPU_MMX, CPU_P3, 0, {0, 0, 0}, 64, 0, 0, 2, {0x0F, 0xD7, 0}, 0, 2, 152 },
-    { SUF_Q|SUF_Z, ONLY_64, CPU_SSE2, 0, 0, {MOD_SetVEX, 0, 0}, 64, 0, 0x66, 2, {0x0F, 0xD7, 0}, 0, 2, 155 }
+   { SUF_L|SUF_Z, NOT_AVX, CPU_MMX, CPU_P3, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0xD7, 0}, 0, 2, 161 },
+    { SUF_L|SUF_Z, 0, CPU_386, CPU_SSE2, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 2, {0x0F, 0xD7, 0}, 0, 2, 164 },
+    { SUF_L|SUF_Z, ONLY_AVX, CPU_386, CPU_AVX2, 0, {0, 0, 0}, 0, 0, 0xC5, 2, {0x0F, 0xD7, 0}, 0, 2, 313 },
+    { SUF_Q|SUF_Z, ONLY_64|NOT_AVX, CPU_MMX, CPU_P3, 0, {0, 0, 0}, 64, 64, 0, 2, {0x0F, 0xD7, 0}, 0, 2, 167 },
+    { SUF_Q|SUF_Z, ONLY_64, CPU_SSE2, 0, 0, {MOD_SetVEX, 0, 0}, 64, 64, 0x66, 2, {0x0F, 0xD7, 0}, 0, 2, 170 },
+    { SUF_Q|SUF_Z, ONLY_64|ONLY_AVX, CPU_SSE2, 0, 0, {0, 0, 0}, 64, 64, 0xC5, 2, {0x0F, 0xD7, 0}, 0, 2, 315 }
 };
 
 static const x86_insn_info pshufw_insn[] = {
-   { SUF_Z, 0, CPU_MMX, CPU_P3, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x70, 0}, 0, 3, 185 }
+   { SUF_Z, 0, CPU_MMX, CPU_P3, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x70, 0}, 0, 3, 140 }
 };
 
 static const x86_insn_info xmm_xmm64_insn[] = {
@@ -1575,28 +1680,28 @@ static const x86_insn_info ssecmp_64_insn[] = {
 };
 
 static const x86_insn_info cvt_rx_xmm64_insn[] = {
-   { SUF_L|SUF_Z, 0, CPU_386, CPU_SSE2, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 149 },
-    { SUF_L|SUF_Z, 0, CPU_386, CPU_SSE2, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 290 },
-    { SUF_Q|SUF_Z, ONLY_64, CPU_SSE2, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 64, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 155 },
-    { SUF_Q|SUF_Z, ONLY_64, CPU_SSE2, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 64, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 409 }
+   { SUF_L|SUF_Z, 0, CPU_386, CPU_SSE2, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 164 },
+    { SUF_L|SUF_Z, 0, CPU_386, CPU_SSE2, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 332 },
+    { SUF_Q|SUF_Z, ONLY_64, CPU_SSE2, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 64, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 170 },
+    { SUF_Q|SUF_Z, ONLY_64, CPU_SSE2, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 64, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 463 }
 };
 
 static const x86_insn_info cvt_mm_xmm_insn[] = {
-   { SUF_Z, 0, CPU_SSE2, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 543 }
+   { SUF_Z, 0, CPU_SSE2, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 611 }
 };
 
 static const x86_insn_info cvt_xmm_mm_ss_insn[] = {
-   { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 285 }
+   { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 327 }
 };
 
 static const x86_insn_info eptvpid_insn[] = {
-   { SUF_L|SUF_Z, NOT_64, CPU_386, CPU_EPTVPID, 0, {MOD_Op2Add, 0, 0}, 32, 0, 0x66, 3, {0x0F, 0x38, 0x80}, 0, 2, 551 },
-    { SUF_Q|SUF_Z, ONLY_64, CPU_EPTVPID, 0, 0, {MOD_Op2Add, 0, 0}, 64, 0, 0x66, 3, {0x0F, 0x38, 0x80}, 0, 2, 553 }
+   { SUF_L|SUF_Z, NOT_64, CPU_386, CPU_EPTVPID, 0, {MOD_Op2Add, 0, 0}, 32, 0, 0x66, 3, {0x0F, 0x38, 0x80}, 0, 2, 607 },
+    { SUF_Q|SUF_Z, ONLY_64, CPU_EPTVPID, 0, 0, {MOD_Op2Add, 0, 0}, 64, 0, 0x66, 3, {0x0F, 0x38, 0x80}, 0, 2, 609 }
 };
 
 static const x86_insn_info vmxmemrd_insn[] = {
-   { SUF_L|SUF_Z, NOT_64, CPU_P4, 0, 0, {0, 0, 0}, 32, 0, 0, 2, {0x0F, 0x78, 0}, 0, 2, 218 },
-    { SUF_Q|SUF_Z, ONLY_64, CPU_P4, 0, 0, {0, 0, 0}, 64, 64, 0, 2, {0x0F, 0x78, 0}, 0, 2, 224 }
+   { SUF_L|SUF_Z, NOT_64, CPU_P4, 0, 0, {0, 0, 0}, 32, 0, 0, 2, {0x0F, 0x78, 0}, 0, 2, 260 },
+    { SUF_Q|SUF_Z, ONLY_64, CPU_P4, 0, 0, {0, 0, 0}, 64, 64, 0, 2, {0x0F, 0x78, 0}, 0, 2, 266 }
 };
 
 static const x86_insn_info vmxmemwr_insn[] = {
@@ -1613,59 +1718,71 @@ static const x86_insn_info vmxthreebytemem_insn[] = {
 };
 
 static const x86_insn_info maskmovdqu_insn[] = {
-   { SUF_Z, 0, CPU_SSE2, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 2, {0x0F, 0xF7, 0}, 0, 2, 88 }
+   { SUF_Z, 0, CPU_SSE2, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 2, {0x0F, 0xF7, 0}, 0, 2, 64 }
 };
 
 static const x86_insn_info movdq2q_insn[] = {
-   { SUF_Z, 0, CPU_SSE2, 0, 0, {0, 0, 0}, 0, 0, 0xF2, 2, {0x0F, 0xD6, 0}, 0, 2, 267 }
+   { SUF_Z, 0, CPU_SSE2, 0, 0, {0, 0, 0}, 0, 0, 0xF2, 2, {0x0F, 0xD6, 0}, 0, 2, 309 }
 };
 
 static const x86_insn_info movq2dq_insn[] = {
-   { SUF_Z, 0, CPU_SSE2, 0, 0, {0, 0, 0}, 0, 0, 0xF3, 2, {0x0F, 0xD6, 0}, 0, 2, 397 }
+   { SUF_Z, 0, CPU_SSE2, 0, 0, {0, 0, 0}, 0, 0, 0xF3, 2, {0x0F, 0xD6, 0}, 0, 2, 439 }
 };
 
 static const x86_insn_info pslrldq_insn[] = {
-   { SUF_Z, 0, CPU_SSE2, 0, 0, {MOD_SpAdd, MOD_SetVEX, 0}, 0, 0, 0x66, 2, {0x0F, 0x73, 0}, 0, 2, 451 },
-    { SUF_Z, 0, CPU_SSE2, 0, 0, {MOD_SpAdd, MOD_SetVEX, 0}, 0, 0, 0x66, 2, {0x0F, 0x73, 0}, 0, 3, 1 }
+   { SUF_Z, 0, CPU_SSE2, 0, 0, {MOD_SpAdd, MOD_SetVEX, 0}, 0, 0, 0x66, 2, {0x0F, 0x73, 0}, 0, 2, 505 },
+    { SUF_Z, 0, CPU_SSE2, 0, 0, {MOD_SpAdd, MOD_SetVEX, 0}, 0, 0, 0x66, 2, {0x0F, 0x73, 0}, 0, 3, 1 },
+    { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0xC5, 2, {0x0F, 0x73, 0}, 0, 2, 507 },
+    { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0xC5, 2, {0x0F, 0x73, 0}, 0, 3, 200 }
 };
 
 static const x86_insn_info lddqu_insn[] = {
-   { SUF_Z, 0, CPU_SSE3, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0xF2, 2, {0x0F, 0xF0, 0}, 0, 2, 527 },
-    { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC7, 2, {0x0F, 0xF0, 0}, 0, 2, 565 }
+   { SUF_Z, 0, CPU_SSE3, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0xF2, 2, {0x0F, 0xF0, 0}, 0, 2, 591 },
+    { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC7, 2, {0x0F, 0xF0, 0}, 0, 2, 593 }
 };
 
 static const x86_insn_info ssse3_insn[] = {
-   { SUF_Z, NOT_AVX, CPU_SSSE3, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 3, {0x0F, 0x38, 0x00}, 0, 2, 185 },
-    { SUF_Z, 0, CPU_SSSE3, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 3, {0x0F, 0x38, 0x00}, 0, 2, 143 },
-    { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x38, 0x00}, 0, 3, 52 }
+   { SUF_Z, NOT_AVX, CPU_SSSE3, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 3, {0x0F, 0x38, 0x00}, 0, 2, 140 },
+    { SUF_Z, 0, CPU_SSSE3, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 3, {0x0F, 0x38, 0x00}, 0, 2, 158 },
+    { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x38, 0x00}, 0, 3, 12 },
+    { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x38, 0x00}, 0, 2, 197 },
+    { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x38, 0x00}, 0, 3, 16 }
 };
 
 static const x86_insn_info ssse3imm_insn[] = {
-   { SUF_Z, 0, CPU_SSSE3, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 3, {0x0F, 0x3A, 0x00}, 0, 3, 185 },
-    { SUF_Z, 0, CPU_SSSE3, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x00}, 0, 3, 170 }
+   { SUF_Z, 0, CPU_SSSE3, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 3, {0x0F, 0x3A, 0x00}, 0, 3, 140 },
+    { SUF_Z, 0, CPU_SSSE3, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x00}, 0, 3, 185 }
 };
 
 static const x86_insn_info sse4_insn[] = {
-   { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 3, {0x0F, 0x38, 0x00}, 0, 2, 170 },
-    { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x38, 0x00}, 0, 2, 176 }
+   { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 3, {0x0F, 0x38, 0x00}, 0, 2, 155 },
+    { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x38, 0x00}, 0, 2, 191 }
 };
 
 static const x86_insn_info sse4imm_256_insn[] = {
-   { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x00}, 0, 3, 143 },
-    { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x00}, 0, 4, 52 },
-    { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x3A, 0x00}, 0, 4, 8 }
+   { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x00}, 0, 3, 158 },
+    { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x00}, 0, 4, 60 },
+    { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x3A, 0x00}, 0, 3, 197 },
+    { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x3A, 0x00}, 0, 4, 20 }
+};
+
+static const x86_insn_info sse4imm_256avx2_insn[] = {
+   { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x00}, 0, 3, 158 },
+    { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x00}, 0, 4, 60 },
+    { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x3A, 0x00}, 0, 3, 197 },
+    { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x3A, 0x00}, 0, 4, 20 }
 };
 
 static const x86_insn_info sse4imm_insn[] = {
-   { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x00}, 0, 3, 143 },
-    { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x00}, 0, 4, 52 }
+   { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x00}, 0, 3, 158 },
+    { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x00}, 0, 4, 60 }
 };
 
 static const x86_insn_info sse4m32imm_insn[] = {
    { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x00}, 0, 3, 92 },
-    { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x00}, 0, 3, 140 },
+    { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x00}, 0, 3, 146 },
     { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x00}, 0, 4, 0 },
-    { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x00}, 0, 4, 48 }
+    { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x00}, 0, 4, 56 }
 };
 
 static const x86_insn_info sse4m64imm_insn[] = {
@@ -1676,91 +1793,99 @@ static const x86_insn_info sse4m64imm_insn[] = {
 };
 
 static const x86_insn_info sse4xmm0_insn[] = {
-   { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0x66, 3, {0x0F, 0x38, 0x00}, 0, 2, 170 },
-    { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0x66, 3, {0x0F, 0x38, 0x00}, 0, 3, 209 }
+   { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0x66, 3, {0x0F, 0x38, 0x00}, 0, 2, 155 },
+    { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0x66, 3, {0x0F, 0x38, 0x00}, 0, 3, 236 }
 };
 
 static const x86_insn_info avx_sse4xmm0_insn[] = {
-   { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x00}, 0, 4, 60 },
-    { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x3A, 0x00}, 0, 4, 64 }
+   { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x00}, 0, 4, 12 },
+    { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x3A, 0x00}, 0, 4, 16 }
 };
 
-static const x86_insn_info avx_sse4xmm0_128_insn[] = {
-   { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x00}, 0, 4, 60 }
+static const x86_insn_info avx2_sse4xmm0_insn[] = {
+   { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x00}, 0, 4, 12 },
+    { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x3A, 0x00}, 0, 4, 16 }
 };
 
 static const x86_insn_info crc32_insn[] = {
-   { SUF_B|SUF_Z, 0, CPU_386, CPU_SSE42, 0, {0, 0, 0}, 0, 0, 0xF2, 3, {0x0F, 0x38, 0xF0}, 0, 2, 475 },
-    { SUF_W|SUF_Z, 0, CPU_386, CPU_SSE42, 0, {0, 0, 0}, 16, 0, 0xF2, 3, {0x0F, 0x38, 0xF1}, 0, 2, 477 },
+   { SUF_B|SUF_Z, 0, CPU_386, CPU_SSE42, 0, {0, 0, 0}, 0, 0, 0xF2, 3, {0x0F, 0x38, 0xF0}, 0, 2, 531 },
+    { SUF_W|SUF_Z, 0, CPU_386, CPU_SSE42, 0, {0, 0, 0}, 16, 0, 0xF2, 3, {0x0F, 0x38, 0xF1}, 0, 2, 533 },
     { SUF_L|SUF_Z, 0, CPU_386, CPU_SSE42, 0, {0, 0, 0}, 32, 0, 0xF2, 3, {0x0F, 0x38, 0xF1}, 0, 2, 101 },
-    { SUF_B|SUF_Z, ONLY_64, CPU_SSE42, 0, 0, {0, 0, 0}, 64, 0, 0xF2, 3, {0x0F, 0x38, 0xF0}, 0, 2, 479 },
+    { SUF_B|SUF_Z, ONLY_64, CPU_SSE42, 0, 0, {0, 0, 0}, 64, 0, 0xF2, 3, {0x0F, 0x38, 0xF0}, 0, 2, 535 },
     { SUF_Q|SUF_Z, ONLY_64, CPU_SSE42, 0, 0, {0, 0, 0}, 64, 0, 0xF2, 3, {0x0F, 0x38, 0xF1}, 0, 2, 104 }
 };
 
 static const x86_insn_info extractps_insn[] = {
-   { SUF_Z, 0, CPU_386, CPU_SSE41, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x17}, 0, 3, 173 },
-    { SUF_Z, ONLY_64, CPU_SSE41, 0, 0, {MOD_SetVEX, 0, 0}, 64, 0, 0x66, 3, {0x0F, 0x3A, 0x17}, 0, 3, 164 }
+   { SUF_Z, 0, CPU_386, CPU_SSE41, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x17}, 0, 3, 188 },
+    { SUF_Z, ONLY_64, CPU_SSE41, 0, 0, {MOD_SetVEX, 0, 0}, 64, 0, 0x66, 3, {0x0F, 0x3A, 0x17}, 0, 3, 179 }
 };
 
 static const x86_insn_info insertps_insn[] = {
-   { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x21}, 0, 3, 140 },
+   { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x21}, 0, 3, 146 },
     { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x21}, 0, 3, 92 },
-    { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x21}, 0, 4, 48 },
+    { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x21}, 0, 4, 56 },
     { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x21}, 0, 4, 0 }
 };
 
 static const x86_insn_info movntdqa_insn[] = {
-   { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 3, {0x0F, 0x38, 0x2A}, 0, 2, 527 }
+   { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 3, {0x0F, 0x38, 0x2A}, 0, 2, 591 },
+    { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {0, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x38, 0x2A}, 0, 2, 593 }
 };
 
 static const x86_insn_info sse4pcmpstr_insn[] = {
-   { SUF_Z, 0, CPU_SSE42, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x00}, 0, 3, 170 }
+   { SUF_Z, 0, CPU_SSE42, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x00}, 0, 3, 185 }
 };
 
 static const x86_insn_info pextrb_insn[] = {
-   { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x14}, 0, 3, 179 },
-    { SUF_Z, 0, CPU_386, CPU_SSE41, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x14}, 0, 3, 161 },
-    { SUF_Z, ONLY_64, CPU_SSE41, 0, 0, {MOD_SetVEX, 0, 0}, 64, 0, 0x66, 3, {0x0F, 0x3A, 0x14}, 0, 3, 164 }
+   { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x14}, 0, 3, 194 },
+    { SUF_Z, 0, CPU_386, CPU_SSE41, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x14}, 0, 3, 176 },
+    { SUF_Z, ONLY_64, CPU_SSE41, 0, 0, {MOD_SetVEX, 0, 0}, 64, 0, 0x66, 3, {0x0F, 0x3A, 0x14}, 0, 3, 179 }
 };
 
 static const x86_insn_info pextrd_insn[] = {
-   { SUF_Z, 0, CPU_386, CPU_SSE41, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x16}, 0, 3, 173 }
+   { SUF_Z, 0, CPU_386, CPU_SSE41, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x16}, 0, 3, 188 }
 };
 
 static const x86_insn_info pextrq_insn[] = {
-   { SUF_Z, ONLY_64, CPU_SSE41, 0, 0, {MOD_SetVEX, 0, 0}, 64, 0, 0x66, 3, {0x0F, 0x3A, 0x16}, 0, 3, 167 }
+   { SUF_Z, ONLY_64, CPU_SSE41, 0, 0, {MOD_SetVEX, 0, 0}, 64, 0, 0x66, 3, {0x0F, 0x3A, 0x16}, 0, 3, 182 }
 };
 
 static const x86_insn_info pinsrb_insn[] = {
-   { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x20}, 0, 3, 137 },
+   { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x20}, 0, 3, 143 },
     { SUF_Z, 0, CPU_386, CPU_SSE41, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x20}, 0, 3, 125 },
-    { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x20}, 0, 4, 40 },
-    { SUF_Z, ONLY_AVX, CPU_386, CPU_AVX, 0, {0, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x20}, 0, 4, 44 }
+    { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x20}, 0, 4, 48 },
+    { SUF_Z, ONLY_AVX, CPU_386, CPU_AVX, 0, {0, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x20}, 0, 4, 52 }
 };
 
 static const x86_insn_info pinsrd_insn[] = {
-   { SUF_Z, 0, CPU_386, CPU_SSE41, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x22}, 0, 3, 134 },
-    { SUF_Z, ONLY_AVX, CPU_386, CPU_AVX, 0, {0, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x22}, 0, 4, 24 }
+   { SUF_Z, 0, CPU_386, CPU_SSE41, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x22}, 0, 3, 233 },
+    { SUF_Z, ONLY_AVX, CPU_386, CPU_AVX, 0, {0, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x22}, 0, 4, 88 }
 };
 
 static const x86_insn_info pinsrq_insn[] = {
-   { SUF_Z, ONLY_64, CPU_SSE41, 0, 0, {MOD_SetVEX, 0, 0}, 64, 0, 0x66, 3, {0x0F, 0x3A, 0x22}, 0, 3, 206 },
-    { SUF_Z, ONLY_64|ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 64, 0, 0xC1, 3, {0x0F, 0x3A, 0x22}, 0, 4, 76 }
+   { SUF_Z, ONLY_64, CPU_SSE41, 0, 0, {MOD_SetVEX, 0, 0}, 64, 0, 0x66, 3, {0x0F, 0x3A, 0x22}, 0, 3, 227 },
+    { SUF_Z, ONLY_64|ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 64, 0, 0xC1, 3, {0x0F, 0x3A, 0x22}, 0, 4, 84 }
 };
 
 static const x86_insn_info sse4m16_insn[] = {
-   { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 3, {0x0F, 0x38, 0x00}, 0, 2, 399 },
-    { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 3, {0x0F, 0x38, 0x00}, 0, 2, 88 }
+   { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 3, {0x0F, 0x38, 0x00}, 0, 2, 441 },
+    { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 3, {0x0F, 0x38, 0x00}, 0, 2, 64 },
+    { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x38, 0x00}, 0, 2, 443 },
+    { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x38, 0x00}, 0, 2, 208 }
 };
 
 static const x86_insn_info sse4m32_insn[] = {
-   { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 3, {0x0F, 0x38, 0x00}, 0, 2, 288 },
-    { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 3, {0x0F, 0x38, 0x00}, 0, 2, 88 }
+   { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 3, {0x0F, 0x38, 0x00}, 0, 2, 330 },
+    { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 3, {0x0F, 0x38, 0x00}, 0, 2, 64 },
+    { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x38, 0x00}, 0, 2, 473 },
+    { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x38, 0x00}, 0, 2, 208 }
 };
 
 static const x86_insn_info sse4m64_insn[] = {
-   { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 3, {0x0F, 0x38, 0x00}, 0, 2, 401 },
-    { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 3, {0x0F, 0x38, 0x00}, 0, 2, 88 }
+   { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 3, {0x0F, 0x38, 0x00}, 0, 2, 445 },
+    { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 3, {0x0F, 0x38, 0x00}, 0, 2, 64 },
+    { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x38, 0x00}, 0, 2, 503 },
+    { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x38, 0x00}, 0, 2, 208 }
 };
 
 static const x86_insn_info cnt_insn[] = {
@@ -1770,87 +1895,95 @@ static const x86_insn_info cnt_insn[] = {
 };
 
 static const x86_insn_info vmovd_insn[] = {
-   { SUF_Z, ONLY_AVX, CPU_386, CPU_AVX, 0, {0, 0, 0}, 0, 0, 0xC1, 2, {0x0F, 0x6E, 0}, 0, 2, 251 },
-    { SUF_Z, ONLY_AVX, CPU_386, CPU_AVX, 0, {0, 0, 0}, 0, 0, 0xC1, 2, {0x0F, 0x7E, 0}, 0, 2, 173 }
+   { SUF_Z, ONLY_AVX, CPU_386, CPU_AVX, 0, {0, 0, 0}, 0, 0, 0xC1, 2, {0x0F, 0x6E, 0}, 0, 2, 293 },
+    { SUF_Z, ONLY_AVX, CPU_386, CPU_AVX, 0, {0, 0, 0}, 0, 0, 0xC1, 2, {0x0F, 0x7E, 0}, 0, 2, 188 }
 };
 
 static const x86_insn_info vmovq_insn[] = {
-   { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC2, 2, {0x0F, 0x7E, 0}, 0, 2, 88 },
-    { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC2, 2, {0x0F, 0x7E, 0}, 0, 2, 401 },
-    { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC1, 2, {0x0F, 0xD6, 0}, 0, 2, 39 },
-    { SUF_Z, ONLY_64|ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 64, 0, 0xC1, 2, {0x0F, 0x6E, 0}, 0, 2, 253 },
-    { SUF_Z, ONLY_64|ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 64, 0, 0xC1, 2, {0x0F, 0x7E, 0}, 0, 2, 167 }
+   { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC2, 2, {0x0F, 0x7E, 0}, 0, 2, 64 },
+    { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC2, 2, {0x0F, 0x7E, 0}, 0, 2, 445 },
+    { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC1, 2, {0x0F, 0xD6, 0}, 0, 2, 47 },
+    { SUF_Z, ONLY_64|ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 64, 0, 0xC1, 2, {0x0F, 0x6E, 0}, 0, 2, 295 },
+    { SUF_Z, ONLY_64|ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 64, 0, 0xC1, 2, {0x0F, 0x7E, 0}, 0, 2, 182 }
 };
 
 static const x86_insn_info avx_xmm_xmm128_insn[] = {
-   { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 2, 170 },
-    { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC4, 2, {0x0F, 0x00, 0}, 0, 2, 176 }
+   { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 2, 155 },
+    { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC4, 2, {0x0F, 0x00, 0}, 0, 2, 191 }
 };
 
 static const x86_insn_info avx_sse4imm_insn[] = {
-   { SUF_Z, ONLY_AVX, CPU_SSE41, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x00}, 0, 3, 170 },
-    { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x00}, 0, 3, 170 },
-    { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x3A, 0x00}, 0, 3, 176 }
+   { SUF_Z, ONLY_AVX, CPU_SSE41, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x00}, 0, 3, 185 },
+    { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x00}, 0, 3, 185 },
+    { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x3A, 0x00}, 0, 3, 191 }
 };
 
 static const x86_insn_info vmovddup_insn[] = {
-   { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 2, 88 },
-    { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 2, 401 },
-    { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC4, 2, {0x0F, 0x00, 0}, 0, 2, 176 }
+   { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 2, 64 },
+    { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 2, 445 },
+    { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC4, 2, {0x0F, 0x00, 0}, 0, 2, 191 }
 };
 
 static const x86_insn_info avx_xmm_xmm64_insn[] = {
-   { SUF_Z, ONLY_AVX, CPU_SSE2, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 2, 88 },
-    { SUF_Z, ONLY_AVX, CPU_SSE2, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 2, 401 }
+   { SUF_Z, ONLY_AVX, CPU_SSE2, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 2, 64 },
+    { SUF_Z, ONLY_AVX, CPU_SSE2, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 2, 445 }
 };
 
 static const x86_insn_info avx_xmm_xmm32_insn[] = {
-   { SUF_Z, ONLY_AVX, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 2, 88 },
-    { SUF_Z, ONLY_AVX, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 2, 288 }
+   { SUF_Z, ONLY_AVX, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 2, 64 },
+    { SUF_Z, ONLY_AVX, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 2, 330 }
 };
 
 static const x86_insn_info avx_cvt_xmm64_insn[] = {
-   { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 2, 88 },
-    { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 2, 401 },
-    { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC4, 2, {0x0F, 0x00, 0}, 0, 2, 403 }
+   { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 2, 64 },
+    { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 2, 445 },
+    { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC4, 2, {0x0F, 0x00, 0}, 0, 2, 447 }
 };
 
 static const x86_insn_info avx_ssse3_2op_insn[] = {
-   { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x38, 0x00}, 0, 2, 170 }
+   { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x38, 0x00}, 0, 2, 155 }
+};
+
+static const x86_insn_info avx2_ssse3_2op_insn[] = {
+   { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x38, 0x00}, 0, 2, 155 },
+    { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x38, 0x00}, 0, 2, 191 }
 };
 
 static const x86_insn_info avx_cvt_xmm128_x_insn[] = {
-   { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 2, 170 }
+   { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 2, 155 }
 };
 
 static const x86_insn_info avx_cvt_xmm128_y_insn[] = {
-   { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC4, 2, {0x0F, 0x00, 0}, 0, 2, 190 }
+   { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC4, 2, {0x0F, 0x00, 0}, 0, 2, 205 }
 };
 
 static const x86_insn_info avx_cvt_xmm128_insn[] = {
-   { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 2, 539 },
-    { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC4, 2, {0x0F, 0x00, 0}, 0, 2, 541 }
+   { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 2, 603 },
+    { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC4, 2, {0x0F, 0x00, 0}, 0, 2, 605 }
 };
 
 static const x86_insn_info vbroadcastss_insn[] = {
-   { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x38, 0x18}, 0, 2, 288 },
-    { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x38, 0x18}, 0, 2, 437 }
+   { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x38, 0x18}, 0, 2, 330 },
+    { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x38, 0x18}, 0, 2, 443 },
+    { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {0, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x38, 0x18}, 0, 2, 64 },
+    { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {0, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x38, 0x18}, 0, 2, 208 }
 };
 
 static const x86_insn_info vbroadcastsd_insn[] = {
-   { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x38, 0x19}, 0, 2, 423 }
+   { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x38, 0x19}, 0, 2, 473 },
+    { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {0, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x38, 0x19}, 0, 2, 208 }
 };
 
-static const x86_insn_info vbroadcastf128_insn[] = {
-   { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x38, 0x1A}, 0, 2, 547 }
+static const x86_insn_info vbroadcastif128_insn[] = {
+   { SUF_Z, ONLY_AVX, 0, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x38, 0x00}, 0, 2, 503 }
 };
 
-static const x86_insn_info vextractf128_insn[] = {
-   { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x3A, 0x19}, 0, 3, 230 }
+static const x86_insn_info vextractif128_insn[] = {
+   { SUF_Z, ONLY_AVX, 0, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x3A, 0x00}, 0, 3, 230 }
 };
 
-static const x86_insn_info vinsertf128_insn[] = {
-   { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x3A, 0x18}, 0, 4, 56 }
+static const x86_insn_info vinsertif128_insn[] = {
+   { SUF_Z, ONLY_AVX, 0, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x3A, 0x00}, 0, 4, 8 }
 };
 
 static const x86_insn_info vzero_insn[] = {
@@ -1858,36 +1991,118 @@ static const x86_insn_info vzero_insn[] = {
 };
 
 static const x86_insn_info vmaskmov_insn[] = {
-   { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x38, 0x00}, 0, 3, 52 },
-    { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x38, 0x00}, 0, 3, 8 },
-    { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x38, 0x02}, 0, 3, 188 },
-    { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x38, 0x02}, 0, 3, 191 }
+   { SUF_Z, ONLY_AVX, 0, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x38, 0x00}, 0, 3, 12 },
+    { SUF_Z, ONLY_AVX, 0, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x38, 0x00}, 0, 3, 16 },
+    { SUF_Z, ONLY_AVX, 0, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x38, 0x02}, 0, 3, 203 },
+    { SUF_Z, ONLY_AVX, 0, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x38, 0x02}, 0, 3, 206 }
 };
 
 static const x86_insn_info vpermil_insn[] = {
-   { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x38, 0x08}, 0, 3, 52 },
-    { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x38, 0x08}, 0, 3, 8 },
-    { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x00}, 0, 3, 170 },
-    { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x3A, 0x00}, 0, 3, 176 }
+   { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x38, 0x08}, 0, 3, 12 },
+    { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x38, 0x08}, 0, 3, 16 },
+    { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x00}, 0, 3, 185 },
+    { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x3A, 0x00}, 0, 3, 191 }
 };
 
 static const x86_insn_info vperm2f128_insn[] = {
-   { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x3A, 0x06}, 0, 4, 8 }
+   { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x3A, 0x06}, 0, 4, 20 }
+};
+
+static const x86_insn_info vperm_var_avx2_insn[] = {
+   { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x38, 0x00}, 0, 3, 16 }
+};
+
+static const x86_insn_info vperm_imm_avx2_insn[] = {
+   { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xCD, 3, {0x0F, 0x3A, 0x00}, 0, 3, 191 }
+};
+
+static const x86_insn_info vperm2i128_avx2_insn[] = {
+   { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {0, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x3A, 0x46}, 0, 4, 20 }
+};
+
+static const x86_insn_info vpbroadcastb_avx2_insn[] = {
+   { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {0, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x38, 0x78}, 0, 2, 537 },
+    { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {0, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x38, 0x78}, 0, 2, 539 },
+    { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {0, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x38, 0x78}, 0, 2, 629 },
+    { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {0, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x38, 0x78}, 0, 2, 631 }
+};
+
+static const x86_insn_info vpbroadcastw_avx2_insn[] = {
+   { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {0, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x38, 0x79}, 0, 2, 537 },
+    { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {0, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x38, 0x79}, 0, 2, 539 },
+    { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {0, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x38, 0x79}, 0, 2, 541 },
+    { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {0, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x38, 0x79}, 0, 2, 543 }
+};
+
+static const x86_insn_info vpbroadcastd_avx2_insn[] = {
+   { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {0, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x38, 0x58}, 0, 2, 537 },
+    { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {0, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x38, 0x58}, 0, 2, 539 },
+    { SUF_Z, ONLY_AVX, CPU_386, CPU_AVX2, 0, {0, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x38, 0x58}, 0, 2, 293 },
+    { SUF_Z, ONLY_AVX, CPU_386, CPU_AVX2, 0, {0, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x38, 0x58}, 0, 2, 637 }
+};
+
+static const x86_insn_info vpbroadcastq_avx2_insn[] = {
+   { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {0, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x38, 0x59}, 0, 2, 537 },
+    { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {0, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x38, 0x59}, 0, 2, 539 },
+    { SUF_Z, ONLY_64|ONLY_AVX, CPU_AVX2, 0, 0, {0, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x38, 0x59}, 0, 2, 295 },
+    { SUF_Z, ONLY_64|ONLY_AVX, CPU_AVX2, 0, 0, {0, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x38, 0x59}, 0, 2, 617 }
+};
+
+static const x86_insn_info vpshiftv_vexw0_avx2_insn[] = {
+   { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x38, 0x00}, 0, 3, 12 },
+    { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x38, 0x00}, 0, 3, 16 }
+};
+
+static const x86_insn_info vpshiftv_vexw1_avx2_insn[] = {
+   { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC9, 3, {0x0F, 0x38, 0x00}, 0, 3, 12 },
+    { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xCD, 3, {0x0F, 0x38, 0x00}, 0, 3, 16 }
+};
+
+static const x86_insn_info vmaskmov_vexw1_avx2_insn[] = {
+   { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC9, 3, {0x0F, 0x38, 0x00}, 0, 3, 12 },
+    { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xCD, 3, {0x0F, 0x38, 0x00}, 0, 3, 16 },
+    { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC9, 3, {0x0F, 0x38, 0x02}, 0, 3, 203 },
+    { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xCD, 3, {0x0F, 0x38, 0x02}, 0, 3, 206 }
+};
+
+static const x86_insn_info vex_66_0F3A_imm8_avx2_insn[] = {
+   { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x00}, 0, 4, 60 },
+    { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x3A, 0x00}, 0, 4, 20 }
+};
+
+static const x86_insn_info gather_64x_64x_insn[] = {
+   { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC9, 3, {0x0F, 0x38, 0x00}, 0, 3, 221 },
+    { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xCD, 3, {0x0F, 0x38, 0x00}, 0, 3, 224 }
+};
+
+static const x86_insn_info gather_64x_64y_insn[] = {
+   { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC9, 3, {0x0F, 0x38, 0x00}, 0, 3, 221 },
+    { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xCD, 3, {0x0F, 0x38, 0x00}, 0, 3, 272 }
+};
+
+static const x86_insn_info gather_32x_32y_insn[] = {
+   { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x38, 0x00}, 0, 3, 239 },
+    { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x38, 0x00}, 0, 3, 245 }
+};
+
+static const x86_insn_info gather_32x_32y_128_insn[] = {
+   { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x38, 0x00}, 0, 3, 239 },
+    { SUF_Z, ONLY_AVX, CPU_AVX2, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x38, 0x00}, 0, 3, 242 }
 };
 
 static const x86_insn_info vfma_ps_insn[] = {
-   { SUF_Z, ONLY_AVX, CPU_FMA, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x38, 0x00}, 0, 3, 52 },
-    { SUF_Z, ONLY_AVX, CPU_FMA, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x38, 0x00}, 0, 3, 8 }
+   { SUF_Z, ONLY_AVX, CPU_FMA, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x38, 0x00}, 0, 3, 12 },
+    { SUF_Z, ONLY_AVX, CPU_FMA, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x38, 0x00}, 0, 3, 16 }
 };
 
 static const x86_insn_info vfma_pd_insn[] = {
-   { SUF_Z, ONLY_AVX, CPU_FMA, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC9, 3, {0x0F, 0x38, 0x00}, 0, 3, 52 },
-    { SUF_Z, ONLY_AVX, CPU_FMA, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xCD, 3, {0x0F, 0x38, 0x00}, 0, 3, 8 }
+   { SUF_Z, ONLY_AVX, CPU_FMA, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC9, 3, {0x0F, 0x38, 0x00}, 0, 3, 12 },
+    { SUF_Z, ONLY_AVX, CPU_FMA, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xCD, 3, {0x0F, 0x38, 0x00}, 0, 3, 16 }
 };
 
 static const x86_insn_info vfma_ss_insn[] = {
    { SUF_Z, ONLY_AVX, CPU_FMA, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x38, 0x00}, 0, 3, 0 },
-    { SUF_Z, ONLY_AVX, CPU_FMA, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x38, 0x00}, 0, 3, 48 }
+    { SUF_Z, ONLY_AVX, CPU_FMA, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x38, 0x00}, 0, 3, 56 }
 };
 
 static const x86_insn_info vfma_sd_insn[] = {
@@ -1896,178 +2111,203 @@ static const x86_insn_info vfma_sd_insn[] = {
 };
 
 static const x86_insn_info aes_insn[] = {
-   { SUF_Z, 0, CPU_AES, 0, 0, {MOD_Op1Add, MOD_Op2Add, MOD_SetVEX}, 0, 0, 0x66, 3, {0x0F, 0x00, 0x00}, 0, 2, 143 },
-    { SUF_Z, ONLY_AVX, CPU_AES, CPU_AVX, 0, {MOD_Op1Add, MOD_Op2Add, 0}, 0, 0, 0xC1, 3, {0x0F, 0x00, 0x00}, 0, 3, 52 }
+   { SUF_Z, 0, CPU_AES, 0, 0, {MOD_Op1Add, MOD_Op2Add, MOD_SetVEX}, 0, 0, 0x66, 3, {0x0F, 0x00, 0x00}, 0, 2, 158 },
+    { SUF_Z, ONLY_AVX, CPU_AES, CPU_AVX, 0, {MOD_Op1Add, MOD_Op2Add, 0}, 0, 0, 0xC1, 3, {0x0F, 0x00, 0x00}, 0, 3, 12 }
 };
 
 static const x86_insn_info aesimc_insn[] = {
-   { SUF_Z, 0, CPU_AES, 0, 0, {MOD_Op1Add, MOD_Op2Add, MOD_SetVEX}, 0, 0, 0x66, 3, {0x0F, 0x00, 0x00}, 0, 2, 170 }
+   { SUF_Z, 0, CPU_AES, 0, 0, {MOD_Op1Add, MOD_Op2Add, MOD_SetVEX}, 0, 0, 0x66, 3, {0x0F, 0x00, 0x00}, 0, 2, 155 }
 };
 
 static const x86_insn_info aes_imm_insn[] = {
-   { SUF_Z, 0, CPU_AES, 0, 0, {MOD_Op1Add, MOD_Op2Add, MOD_SetVEX}, 0, 0, 0x66, 3, {0x0F, 0x00, 0x00}, 0, 3, 170 }
+   { SUF_Z, 0, CPU_AES, 0, 0, {MOD_Op1Add, MOD_Op2Add, MOD_SetVEX}, 0, 0, 0x66, 3, {0x0F, 0x00, 0x00}, 0, 3, 185 }
 };
 
 static const x86_insn_info pclmulqdq_insn[] = {
-   { SUF_Z, 0, CPU_CLMUL, 0, 0, {MOD_Op1Add, MOD_Op2Add, MOD_SetVEX}, 0, 0, 0x66, 3, {0x0F, 0x00, 0x00}, 0, 3, 143 },
-    { SUF_Z, ONLY_AVX, CPU_AVX, CPU_CLMUL, 0, {MOD_Op1Add, MOD_Op2Add, 0}, 0, 0, 0xC1, 3, {0x0F, 0x00, 0x00}, 0, 4, 52 }
+   { SUF_Z, 0, CPU_CLMUL, 0, 0, {MOD_Op1Add, MOD_Op2Add, MOD_SetVEX}, 0, 0, 0x66, 3, {0x0F, 0x00, 0x00}, 0, 3, 158 },
+    { SUF_Z, ONLY_AVX, CPU_AVX, CPU_CLMUL, 0, {MOD_Op1Add, MOD_Op2Add, 0}, 0, 0, 0xC1, 3, {0x0F, 0x00, 0x00}, 0, 4, 60 }
 };
 
 static const x86_insn_info pclmulqdq_fixed_insn[] = {
-   { SUF_Z, 0, CPU_CLMUL, 0, 0, {MOD_Imm8, MOD_SetVEX, 0}, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x44}, 0, 2, 143 },
-    { SUF_Z, ONLY_AVX, CPU_AVX, CPU_CLMUL, 0, {MOD_Imm8, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x44}, 0, 3, 52 }
+   { SUF_Z, 0, CPU_CLMUL, 0, 0, {MOD_Imm8, MOD_SetVEX, 0}, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x44}, 0, 2, 158 },
+    { SUF_Z, ONLY_AVX, CPU_AVX, CPU_CLMUL, 0, {MOD_Imm8, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x44}, 0, 3, 12 }
 };
 
 static const x86_insn_info rdrand_insn[] = {
-   { SUF_Z, 0, CPU_RDRAND, 0, 0, {0, 0, 0}, 16, 0, 0, 2, {0x0F, 0xC7, 0}, 6, 1, 347 },
-    { SUF_Z, 0, CPU_386, CPU_RDRAND, 0, {0, 0, 0}, 32, 0, 0, 2, {0x0F, 0xC7, 0}, 6, 1, 14 },
-    { SUF_Z, ONLY_64, CPU_RDRAND, 0, 0, {0, 0, 0}, 64, 0, 0, 2, {0x0F, 0xC7, 0}, 6, 1, 18 }
+   { SUF_Z, 0, CPU_RDRAND, 0, 0, {0, 0, 0}, 16, 0, 0, 2, {0x0F, 0xC7, 0}, 6, 1, 389 },
+    { SUF_Z, 0, CPU_386, CPU_RDRAND, 0, {0, 0, 0}, 32, 0, 0, 2, {0x0F, 0xC7, 0}, 6, 1, 26 },
+    { SUF_Z, ONLY_64, CPU_RDRAND, 0, 0, {0, 0, 0}, 64, 0, 0, 2, {0x0F, 0xC7, 0}, 6, 1, 30 }
 };
 
 static const x86_insn_info fs_gs_base_insn[] = {
-   { SUF_Z, ONLY_64, CPU_FSGSBASE, 0, 0, {MOD_SpAdd, 0, 0}, 32, 0, 0xF3, 2, {0x0F, 0xAE, 0}, 0, 1, 14 },
-    { SUF_Z, ONLY_64, CPU_FSGSBASE, 0, 0, {MOD_SpAdd, 0, 0}, 64, 0, 0xF3, 2, {0x0F, 0xAE, 0}, 0, 1, 18 }
+   { SUF_Z, ONLY_64, CPU_FSGSBASE, 0, 0, {MOD_SpAdd, 0, 0}, 32, 0, 0xF3, 2, {0x0F, 0xAE, 0}, 0, 1, 26 },
+    { SUF_Z, ONLY_64, CPU_FSGSBASE, 0, 0, {MOD_SpAdd, 0, 0}, 64, 0, 0xF3, 2, {0x0F, 0xAE, 0}, 0, 1, 30 }
 };
 
 static const x86_insn_info avx_cvtps2ph_insn[] = {
-   { SUF_Z, ONLY_AVX, CPU_AVX, CPU_F16C, 0, {MOD_PreAdd, MOD_Op2Add, 0}, 0, 0, 0xC0, 3, {0x0F, 0x3A, 0x00}, 0, 3, 194 },
-    { SUF_Z, ONLY_AVX, CPU_AVX, CPU_F16C, 0, {MOD_PreAdd, MOD_Op2Add, 0}, 0, 0, 0xC0, 3, {0x0F, 0x3A, 0x00}, 0, 3, 197 },
-    { SUF_Z, ONLY_AVX, CPU_AVX, CPU_F16C, 0, {MOD_PreAdd, MOD_Op2Add, 0}, 0, 0, 0xC4, 3, {0x0F, 0x3A, 0x00}, 0, 3, 200 },
-    { SUF_Z, ONLY_AVX, CPU_AVX, CPU_F16C, 0, {MOD_PreAdd, MOD_Op2Add, 0}, 0, 0, 0xC4, 3, {0x0F, 0x3A, 0x00}, 0, 3, 203 }
+   { SUF_Z, ONLY_AVX, CPU_AVX, CPU_F16C, 0, {MOD_PreAdd, MOD_Op2Add, 0}, 0, 0, 0xC0, 3, {0x0F, 0x3A, 0x00}, 0, 3, 209 },
+    { SUF_Z, ONLY_AVX, CPU_AVX, CPU_F16C, 0, {MOD_PreAdd, MOD_Op2Add, 0}, 0, 0, 0xC0, 3, {0x0F, 0x3A, 0x00}, 0, 3, 212 },
+    { SUF_Z, ONLY_AVX, CPU_AVX, CPU_F16C, 0, {MOD_PreAdd, MOD_Op2Add, 0}, 0, 0, 0xC4, 3, {0x0F, 0x3A, 0x00}, 0, 3, 215 },
+    { SUF_Z, ONLY_AVX, CPU_AVX, CPU_F16C, 0, {MOD_PreAdd, MOD_Op2Add, 0}, 0, 0, 0xC4, 3, {0x0F, 0x3A, 0x00}, 0, 3, 218 }
 };
 
 static const x86_insn_info avx_cvtph2ps_insn[] = {
-   { SUF_Z, ONLY_AVX, CPU_AVX, CPU_F16C, 0, {MOD_PreAdd, MOD_Op2Add, 0}, 0, 0, 0xC0, 3, {0x0F, 0x38, 0x00}, 0, 2, 88 },
-    { SUF_Z, ONLY_AVX, CPU_AVX, CPU_F16C, 0, {MOD_PreAdd, MOD_Op2Add, 0}, 0, 0, 0xC0, 3, {0x0F, 0x38, 0x00}, 0, 2, 561 },
-    { SUF_Z, ONLY_AVX, CPU_AVX, CPU_F16C, 0, {MOD_PreAdd, MOD_Op2Add, 0}, 0, 0, 0xC4, 3, {0x0F, 0x38, 0x00}, 0, 2, 193 },
-    { SUF_Z, ONLY_AVX, CPU_AVX, CPU_F16C, 0, {MOD_PreAdd, MOD_Op2Add, 0}, 0, 0, 0xC4, 3, {0x0F, 0x38, 0x00}, 0, 2, 563 }
+   { SUF_Z, ONLY_AVX, CPU_AVX, CPU_F16C, 0, {MOD_PreAdd, MOD_Op2Add, 0}, 0, 0, 0xC0, 3, {0x0F, 0x38, 0x00}, 0, 2, 64 },
+    { SUF_Z, ONLY_AVX, CPU_AVX, CPU_F16C, 0, {MOD_PreAdd, MOD_Op2Add, 0}, 0, 0, 0xC0, 3, {0x0F, 0x38, 0x00}, 0, 2, 625 },
+    { SUF_Z, ONLY_AVX, CPU_AVX, CPU_F16C, 0, {MOD_PreAdd, MOD_Op2Add, 0}, 0, 0, 0xC4, 3, {0x0F, 0x38, 0x00}, 0, 2, 208 },
+    { SUF_Z, ONLY_AVX, CPU_AVX, CPU_F16C, 0, {MOD_PreAdd, MOD_Op2Add, 0}, 0, 0, 0xC4, 3, {0x0F, 0x38, 0x00}, 0, 2, 627 }
 };
 
 static const x86_insn_info extrq_insn[] = {
-   { SUF_Z, 0, CPU_SSE4a, 0, 0, {0, 0, 0}, 0, 0, 0x66, 2, {0x0F, 0x78, 0}, 0, 3, 89 },
-    { SUF_Z, 0, CPU_SSE4a, 0, 0, {0, 0, 0}, 0, 0, 0x66, 2, {0x0F, 0x79, 0}, 0, 2, 88 }
+   { SUF_Z, 0, CPU_SSE4a, 0, 0, {0, 0, 0}, 0, 0, 0x66, 2, {0x0F, 0x78, 0}, 0, 3, 65 },
+    { SUF_Z, 0, CPU_SSE4a, 0, 0, {0, 0, 0}, 0, 0, 0x66, 2, {0x0F, 0x79, 0}, 0, 2, 64 }
 };
 
 static const x86_insn_info insertq_insn[] = {
-   { SUF_Z, 0, CPU_SSE4a, 0, 0, {0, 0, 0}, 0, 0, 0xF2, 2, {0x0F, 0x78, 0}, 0, 4, 88 },
-    { SUF_Z, 0, CPU_SSE4a, 0, 0, {0, 0, 0}, 0, 0, 0xF2, 2, {0x0F, 0x79, 0}, 0, 2, 88 }
+   { SUF_Z, 0, CPU_SSE4a, 0, 0, {0, 0, 0}, 0, 0, 0xF2, 2, {0x0F, 0x78, 0}, 0, 4, 64 },
+    { SUF_Z, 0, CPU_SSE4a, 0, 0, {0, 0, 0}, 0, 0, 0xF2, 2, {0x0F, 0x79, 0}, 0, 2, 64 }
 };
 
 static const x86_insn_info movntsd_insn[] = {
-   { SUF_Z, 0, CPU_SSE4a, 0, 0, {0, 0, 0}, 0, 0, 0xF2, 2, {0x0F, 0x2B, 0}, 0, 2, 39 }
+   { SUF_Z, 0, CPU_SSE4a, 0, 0, {0, 0, 0}, 0, 0, 0xF2, 2, {0x0F, 0x2B, 0}, 0, 2, 47 }
 };
 
 static const x86_insn_info movntss_insn[] = {
-   { SUF_Z, 0, CPU_SSE4a, 0, 0, {0, 0, 0}, 0, 0, 0xF3, 2, {0x0F, 0x2B, 0}, 0, 2, 529 }
+   { SUF_Z, 0, CPU_SSE4a, 0, 0, {0, 0, 0}, 0, 0, 0xF3, 2, {0x0F, 0x2B, 0}, 0, 2, 444 }
 };
 
 static const x86_insn_info vfrc_pdps_insn[] = {
-   { SUF_Z, 0, CPU_XOP, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0x80, 2, {0x09, 0x80, 0}, 0, 2, 170 },
-    { SUF_Z, 0, CPU_XOP, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0x84, 2, {0x09, 0x80, 0}, 0, 2, 176 }
+   { SUF_Z, 0, CPU_XOP, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0x80, 2, {0x09, 0x80, 0}, 0, 2, 155 },
+    { SUF_Z, 0, CPU_XOP, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0x84, 2, {0x09, 0x80, 0}, 0, 2, 191 }
 };
 
 static const x86_insn_info vfrczsd_insn[] = {
-   { SUF_Z, 0, CPU_XOP, 0, 0, {0, 0, 0}, 0, 0, 0x80, 2, {0x09, 0x83, 0}, 0, 2, 88 },
-    { SUF_Z, 0, CPU_XOP, 0, 0, {0, 0, 0}, 0, 0, 0x80, 2, {0x09, 0x83, 0}, 0, 2, 401 }
+   { SUF_Z, 0, CPU_XOP, 0, 0, {0, 0, 0}, 0, 0, 0x80, 2, {0x09, 0x83, 0}, 0, 2, 64 },
+    { SUF_Z, 0, CPU_XOP, 0, 0, {0, 0, 0}, 0, 0, 0x80, 2, {0x09, 0x83, 0}, 0, 2, 445 }
 };
 
 static const x86_insn_info vfrczss_insn[] = {
-   { SUF_Z, 0, CPU_XOP, 0, 0, {0, 0, 0}, 0, 0, 0x80, 2, {0x09, 0x82, 0}, 0, 2, 88 },
-    { SUF_Z, 0, CPU_XOP, 0, 0, {0, 0, 0}, 0, 0, 0x80, 2, {0x09, 0x82, 0}, 0, 2, 288 }
+   { SUF_Z, 0, CPU_XOP, 0, 0, {0, 0, 0}, 0, 0, 0x80, 2, {0x09, 0x82, 0}, 0, 2, 64 },
+    { SUF_Z, 0, CPU_XOP, 0, 0, {0, 0, 0}, 0, 0, 0x80, 2, {0x09, 0x82, 0}, 0, 2, 330 }
 };
 
 static const x86_insn_info vpcmov_insn[] = {
-   { SUF_Z, 0, CPU_XOP, 0, 0, {0, 0, 0}, 0, 0, 0x80, 2, {0x08, 0xA2, 0}, 0, 4, 60 },
-    { SUF_Z, 0, CPU_XOP, 0, 0, {0, 0, 0}, 0, 0, 0x88, 2, {0x08, 0xA2, 0}, 0, 4, 80 },
-    { SUF_Z, 0, CPU_XOP, 0, 0, {0, 0, 0}, 0, 0, 0x84, 2, {0x08, 0xA2, 0}, 0, 4, 64 },
-    { SUF_Z, 0, CPU_XOP, 0, 0, {0, 0, 0}, 0, 0, 0x8C, 2, {0x08, 0xA2, 0}, 0, 4, 84 }
+   { SUF_Z, 0, CPU_XOP, 0, 0, {0, 0, 0}, 0, 0, 0x80, 2, {0x08, 0xA2, 0}, 0, 4, 12 },
+    { SUF_Z, 0, CPU_XOP, 0, 0, {0, 0, 0}, 0, 0, 0x88, 2, {0x08, 0xA2, 0}, 0, 4, 68 },
+    { SUF_Z, 0, CPU_XOP, 0, 0, {0, 0, 0}, 0, 0, 0x84, 2, {0x08, 0xA2, 0}, 0, 4, 16 },
+    { SUF_Z, 0, CPU_XOP, 0, 0, {0, 0, 0}, 0, 0, 0x8C, 2, {0x08, 0xA2, 0}, 0, 4, 72 }
 };
 
 static const x86_insn_info vpcom_insn[] = {
-   { SUF_Z, 0, CPU_XOP, 0, 0, {MOD_Op1Add, MOD_Imm8, 0}, 0, 0, 0x80, 2, {0x08, 0x00, 0}, 0, 3, 52 }
+   { SUF_Z, 0, CPU_XOP, 0, 0, {MOD_Op1Add, MOD_Imm8, 0}, 0, 0, 0x80, 2, {0x08, 0x00, 0}, 0, 3, 12 }
 };
 
 static const x86_insn_info vpcom_imm_insn[] = {
-   { SUF_Z, 0, CPU_XOP, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0x80, 2, {0x08, 0x00, 0}, 0, 4, 52 }
+   { SUF_Z, 0, CPU_XOP, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0x80, 2, {0x08, 0x00, 0}, 0, 4, 60 }
 };
 
 static const x86_insn_info vphaddsub_insn[] = {
-   { SUF_Z, 0, CPU_XOP, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0x80, 2, {0x09, 0x00, 0}, 0, 2, 170 }
+   { SUF_Z, 0, CPU_XOP, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0x80, 2, {0x09, 0x00, 0}, 0, 2, 155 }
 };
 
 static const x86_insn_info vpma_insn[] = {
-   { SUF_Z, 0, CPU_XOP, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0x80, 2, {0x08, 0x00, 0}, 0, 4, 60 }
+   { SUF_Z, 0, CPU_XOP, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0x80, 2, {0x08, 0x00, 0}, 0, 4, 12 }
 };
 
 static const x86_insn_info vpperm_insn[] = {
-   { SUF_Z, 0, CPU_XOP, 0, 0, {0, 0, 0}, 0, 0, 0x80, 2, {0x08, 0xA3, 0}, 0, 4, 60 },
-    { SUF_Z, 0, CPU_XOP, 0, 0, {0, 0, 0}, 0, 0, 0x88, 2, {0x08, 0xA3, 0}, 0, 4, 80 }
+   { SUF_Z, 0, CPU_XOP, 0, 0, {0, 0, 0}, 0, 0, 0x80, 2, {0x08, 0xA3, 0}, 0, 4, 12 },
+    { SUF_Z, 0, CPU_XOP, 0, 0, {0, 0, 0}, 0, 0, 0x88, 2, {0x08, 0xA3, 0}, 0, 4, 68 }
 };
 
 static const x86_insn_info vprot_insn[] = {
-   { SUF_Z, 0, CPU_XOP, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0x80, 2, {0x09, 0x90, 0}, 0, 3, 182 },
-    { SUF_Z, 0, CPU_XOP, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0x88, 2, {0x09, 0x90, 0}, 0, 3, 52 },
-    { SUF_Z, 0, CPU_XOP, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0x80, 2, {0x08, 0xC0, 0}, 0, 3, 170 }
+   { SUF_Z, 0, CPU_XOP, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0x80, 2, {0x09, 0x90, 0}, 0, 3, 155 },
+    { SUF_Z, 0, CPU_XOP, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0x88, 2, {0x09, 0x90, 0}, 0, 3, 12 },
+    { SUF_Z, 0, CPU_XOP, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0x80, 2, {0x08, 0xC0, 0}, 0, 3, 185 }
 };
 
 static const x86_insn_info amd_vpshift_insn[] = {
-   { SUF_Z, 0, CPU_XOP, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0x80, 2, {0x09, 0x00, 0}, 0, 3, 182 },
-    { SUF_Z, 0, CPU_XOP, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0x88, 2, {0x09, 0x00, 0}, 0, 3, 52 }
+   { SUF_Z, 0, CPU_XOP, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0x80, 2, {0x09, 0x00, 0}, 0, 3, 155 },
+    { SUF_Z, 0, CPU_XOP, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0x88, 2, {0x09, 0x00, 0}, 0, 3, 12 }
 };
 
 static const x86_insn_info fma_128_256_insn[] = {
-   { SUF_Z, ONLY_AVX, CPU_FMA4, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x00}, 0, 4, 60 },
-    { SUF_Z, ONLY_AVX, CPU_FMA4, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC9, 3, {0x0F, 0x3A, 0x00}, 0, 4, 80 },
-    { SUF_Z, ONLY_AVX, CPU_FMA4, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x3A, 0x00}, 0, 4, 64 },
-    { SUF_Z, ONLY_AVX, CPU_FMA4, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xCD, 3, {0x0F, 0x3A, 0x00}, 0, 4, 84 }
+   { SUF_Z, ONLY_AVX, CPU_FMA4, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x00}, 0, 4, 12 },
+    { SUF_Z, ONLY_AVX, CPU_FMA4, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC9, 3, {0x0F, 0x3A, 0x00}, 0, 4, 68 },
+    { SUF_Z, ONLY_AVX, CPU_FMA4, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x3A, 0x00}, 0, 4, 16 },
+    { SUF_Z, ONLY_AVX, CPU_FMA4, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xCD, 3, {0x0F, 0x3A, 0x00}, 0, 4, 72 }
 };
 
 static const x86_insn_info fma_128_m32_insn[] = {
-   { SUF_Z, ONLY_AVX, CPU_FMA4, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x00}, 0, 4, 28 },
-    { SUF_Z, ONLY_AVX, CPU_FMA4, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x00}, 0, 4, 68 },
-    { SUF_Z, ONLY_AVX, CPU_FMA4, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC9, 3, {0x0F, 0x3A, 0x00}, 0, 4, 72 }
+   { SUF_Z, ONLY_AVX, CPU_FMA4, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x00}, 0, 4, 36 },
+    { SUF_Z, ONLY_AVX, CPU_FMA4, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x00}, 0, 4, 76 },
+    { SUF_Z, ONLY_AVX, CPU_FMA4, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC9, 3, {0x0F, 0x3A, 0x00}, 0, 4, 80 }
 };
 
 static const x86_insn_info fma_128_m64_insn[] = {
-   { SUF_Z, ONLY_AVX, CPU_FMA4, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x00}, 0, 4, 28 },
-    { SUF_Z, ONLY_AVX, CPU_FMA4, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x00}, 0, 4, 32 },
-    { SUF_Z, ONLY_AVX, CPU_FMA4, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC9, 3, {0x0F, 0x3A, 0x00}, 0, 4, 36 }
+   { SUF_Z, ONLY_AVX, CPU_FMA4, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x00}, 0, 4, 36 },
+    { SUF_Z, ONLY_AVX, CPU_FMA4, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x00}, 0, 4, 40 },
+    { SUF_Z, ONLY_AVX, CPU_FMA4, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC9, 3, {0x0F, 0x3A, 0x00}, 0, 4, 44 }
 };
 
 static const x86_insn_info xsaveopt64_insn[] = {
-   { SUF_Z, ONLY_64, 0, 0, 0, {MOD_SpAdd, MOD_Op0Add, MOD_Op1Add}, 64, 0, 0, 2, {0x00, 0x00, 0}, 0, 1, 470 }
+   { SUF_Z, ONLY_64, 0, 0, 0, {MOD_SpAdd, MOD_Op0Add, MOD_Op1Add}, 64, 0, 0, 2, {0x00, 0x00, 0}, 0, 1, 526 }
 };
 
 static const x86_insn_info movbe_insn[] = {
-   { SUF_Z, 0, CPU_MOVBE, 0, 0, {0, 0, 0}, 16, 0, 0, 3, {0x0F, 0x38, 0xF0}, 0, 2, 405 },
-    { SUF_Z, 0, CPU_MOVBE, 0, 0, {0, 0, 0}, 16, 0, 0, 3, {0x0F, 0x38, 0xF1}, 0, 2, 407 },
-    { SUF_Z, 0, CPU_386, CPU_MOVBE, 0, {0, 0, 0}, 32, 0, 0, 3, {0x0F, 0x38, 0xF0}, 0, 2, 311 },
-    { SUF_Z, 0, CPU_386, CPU_MOVBE, 0, {0, 0, 0}, 32, 0, 0, 3, {0x0F, 0x38, 0xF1}, 0, 2, 289 },
-    { SUF_Z, ONLY_64, CPU_MOVBE, 0, 0, {0, 0, 0}, 64, 0, 0, 3, {0x0F, 0x38, 0xF0}, 0, 2, 409 },
-    { SUF_Z, ONLY_64, CPU_MOVBE, 0, 0, {0, 0, 0}, 64, 0, 0, 3, {0x0F, 0x38, 0xF1}, 0, 2, 291 }
+   { SUF_Z, 0, CPU_MOVBE, 0, 0, {0, 0, 0}, 16, 0, 0, 3, {0x0F, 0x38, 0xF0}, 0, 2, 459 },
+    { SUF_Z, 0, CPU_MOVBE, 0, 0, {0, 0, 0}, 16, 0, 0, 3, {0x0F, 0x38, 0xF1}, 0, 2, 461 },
+    { SUF_Z, 0, CPU_386, CPU_MOVBE, 0, {0, 0, 0}, 32, 0, 0, 3, {0x0F, 0x38, 0xF0}, 0, 2, 353 },
+    { SUF_Z, 0, CPU_386, CPU_MOVBE, 0, {0, 0, 0}, 32, 0, 0, 3, {0x0F, 0x38, 0xF1}, 0, 2, 331 },
+    { SUF_Z, ONLY_64, CPU_MOVBE, 0, 0, {0, 0, 0}, 64, 0, 0, 3, {0x0F, 0x38, 0xF0}, 0, 2, 463 },
+    { SUF_Z, ONLY_64, CPU_MOVBE, 0, 0, {0, 0, 0}, 64, 0, 0, 3, {0x0F, 0x38, 0xF1}, 0, 2, 333 }
+};
+
+static const x86_insn_info vex_gpr_ndd_rm_0F38_regext_insn[] = {
+   { SUF_W|SUF_Z, ONLY_AVX, CPU_386, 0, 0, {MOD_PreAdd, MOD_Op2Add, MOD_SpAdd}, 32, 0, 0xC0, 3, {0x0F, 0x38, 0x00}, 0, 2, 249 },
+    { SUF_L|SUF_Z, ONLY_64|ONLY_AVX, 0, 0, 0, {MOD_PreAdd, MOD_Op2Add, MOD_SpAdd}, 64, 0, 0xC0, 3, {0x0F, 0x38, 0x00}, 0, 2, 252 }
+};
+
+static const x86_insn_info vex_gpr_reg_rm_0F_imm8_insn[] = {
+   { SUF_W|SUF_Z, ONLY_AVX, CPU_386, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_Op2Add}, 32, 0, 0xC0, 3, {0x0F, 0x00, 0x00}, 0, 3, 134 },
+    { SUF_L|SUF_Z, ONLY_64|ONLY_AVX, 0, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_Op2Add}, 64, 0, 0xC0, 3, {0x0F, 0x00, 0x00}, 0, 3, 137 }
+};
+
+static const x86_insn_info vex_gpr_reg_nds_rm_0F_insn[] = {
+   { SUF_L|SUF_Z, ONLY_AVX, CPU_386, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_Op2Add}, 32, 0, 0xC0, 3, {0x0F, 0x00, 0x00}, 0, 3, 248 },
+    { SUF_Q|SUF_Z, ONLY_64|ONLY_AVX, 0, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_Op2Add}, 64, 0, 0xC0, 3, {0x0F, 0x00, 0x00}, 0, 3, 251 }
+};
+
+static const x86_insn_info vex_gpr_reg_rm_nds_0F_insn[] = {
+   { SUF_L|SUF_Z, ONLY_AVX, CPU_386, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_Op2Add}, 32, 0, 0xC0, 3, {0x0F, 0x00, 0x00}, 0, 3, 149 },
+    { SUF_Q|SUF_Z, ONLY_64|ONLY_AVX, 0, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_Op2Add}, 64, 0, 0xC0, 3, {0x0F, 0x00, 0x00}, 0, 3, 152 }
+};
+
+static const x86_insn_info invpcid_insn[] = {
+   { SUF_Z, NOT_64, CPU_386, CPU_INVPCID, CPU_Priv, {0, 0, 0}, 0, 0, 0x66, 3, {0x0F, 0x38, 0x82}, 0, 2, 607 },
+    { SUF_Z, ONLY_64, CPU_INVPCID, CPU_Priv, 0, {0, 0, 0}, 0, 64, 0x66, 3, {0x0F, 0x38, 0x82}, 0, 2, 609 }
 };
 
 static const x86_insn_info now3d_insn[] = {
-   { SUF_Z, 0, CPU_3DNow, 0, 0, {MOD_Imm8, 0, 0}, 0, 0, 0, 2, {0x0F, 0x0F, 0}, 0, 2, 185 }
+   { SUF_Z, 0, CPU_3DNow, 0, 0, {MOD_Imm8, 0, 0}, 0, 0, 0, 2, {0x0F, 0x0F, 0}, 0, 2, 140 }
 };
 
 static const x86_insn_info cmpxchg16b_insn[] = {
-   { SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 2, {0x0F, 0xC7, 0}, 1, 1, 528 }
+   { SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 2, {0x0F, 0xC7, 0}, 1, 1, 504 }
 };
 
 static const x86_insn_info invlpga_insn[] = {
    { SUF_Z, 0, CPU_SVM, 0, 0, {0, 0, 0}, 0, 0, 0, 3, {0x0F, 0x01, 0xDF}, 0, 0, 0 },
-    { SUF_Z, 0, CPU_386, CPU_SVM, 0, {0, 0, 0}, 0, 0, 0, 3, {0x0F, 0x01, 0xDF}, 0, 2, 453 }
+    { SUF_Z, 0, CPU_386, CPU_SVM, 0, {0, 0, 0}, 0, 0, 0, 3, {0x0F, 0x01, 0xDF}, 0, 2, 509 }
 };
 
 static const x86_insn_info skinit_insn[] = {
    { SUF_Z, 0, CPU_SVM, 0, 0, {0, 0, 0}, 0, 0, 0, 3, {0x0F, 0x01, 0xDE}, 0, 0, 0 },
-    { SUF_Z, 0, CPU_SVM, 0, 0, {0, 0, 0}, 0, 0, 0, 3, {0x0F, 0x01, 0xDE}, 0, 1, 579 }
+    { SUF_Z, 0, CPU_SVM, 0, 0, {0, 0, 0}, 0, 0, 0, 3, {0x0F, 0x01, 0xDE}, 0, 1, 649 }
 };
 
 static const x86_insn_info svm_rax_insn[] = {
    { SUF_Z, 0, CPU_SVM, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 3, {0x0F, 0x01, 0x00}, 0, 0, 0 },
-    { SUF_Z, 0, CPU_SVM, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 3, {0x0F, 0x01, 0x00}, 0, 1, 453 }
+    { SUF_Z, 0, CPU_SVM, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 3, {0x0F, 0x01, 0x00}, 0, 1, 509 }
 };
 
 static const x86_insn_info padlock_insn[] = {
@@ -2075,45 +2315,45 @@ static const x86_insn_info padlock_insn[] = {
 };
 
 static const x86_insn_info cyrixmmx_insn[] = {
-   { SUF_Z, 0, CPU_Cyrix, CPU_MMX, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 185 }
+   { SUF_Z, 0, CPU_Cyrix, CPU_MMX, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 140 }
 };
 
 static const x86_insn_info pmachriw_insn[] = {
-   { SUF_Z, 0, CPU_Cyrix, CPU_MMX, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x5E, 0}, 0, 2, 269 }
+   { SUF_Z, 0, CPU_Cyrix, CPU_MMX, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x5E, 0}, 0, 2, 311 }
 };
 
 static const x86_insn_info rdwrshr_insn[] = {
-   { SUF_Z, 0, CPU_686, CPU_Cyrix, CPU_SMM, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0x0F, 0x36, 0}, 0, 1, 26 }
+   { SUF_Z, 0, CPU_686, CPU_Cyrix, CPU_SMM, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0x0F, 0x36, 0}, 0, 1, 90 }
 };
 
 static const x86_insn_info rsdc_insn[] = {
-   { SUF_Z, 0, CPU_486, CPU_Cyrix, CPU_SMM, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x79, 0}, 0, 2, 497 }
+   { SUF_Z, 0, CPU_486, CPU_Cyrix, CPU_SMM, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x79, 0}, 0, 2, 561 }
 };
 
 static const x86_insn_info cyrixsmm_insn[] = {
-   { SUF_Z, 0, CPU_486, CPU_Cyrix, CPU_SMM, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 1, 498 }
+   { SUF_Z, 0, CPU_486, CPU_Cyrix, CPU_SMM, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 1, 562 }
 };
 
 static const x86_insn_info svdc_insn[] = {
-   { SUF_Z, 0, CPU_486, CPU_Cyrix, CPU_SMM, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x78, 0}, 0, 2, 549 }
+   { SUF_Z, 0, CPU_486, CPU_Cyrix, CPU_SMM, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x78, 0}, 0, 2, 615 }
 };
 
 static const x86_insn_info ibts_insn[] = {
-   { SUF_Z, 0, CPU_386, CPU_Obs, CPU_Undoc, {0, 0, 0}, 16, 0, 0, 2, {0x0F, 0xA7, 0}, 0, 2, 212 },
-    { SUF_Z, 0, CPU_386, CPU_Obs, CPU_Undoc, {0, 0, 0}, 32, 0, 0, 2, {0x0F, 0xA7, 0}, 0, 2, 218 }
+   { SUF_Z, 0, CPU_386, CPU_Obs, CPU_Undoc, {0, 0, 0}, 16, 0, 0, 2, {0x0F, 0xA7, 0}, 0, 2, 254 },
+    { SUF_Z, 0, CPU_386, CPU_Obs, CPU_Undoc, {0, 0, 0}, 32, 0, 0, 2, {0x0F, 0xA7, 0}, 0, 2, 260 }
 };
 
 static const x86_insn_info umov_insn[] = {
-   { SUF_Z, 0, CPU_386, CPU_Undoc, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x10, 0}, 0, 2, 275 },
-    { SUF_Z, 0, CPU_386, CPU_Undoc, 0, {0, 0, 0}, 16, 0, 0, 2, {0x0F, 0x11, 0}, 0, 2, 212 },
-    { SUF_Z, 0, CPU_386, CPU_Undoc, 0, {0, 0, 0}, 32, 0, 0, 2, {0x0F, 0x11, 0}, 0, 2, 218 },
-    { SUF_Z, 0, CPU_386, CPU_Undoc, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x12, 0}, 0, 2, 277 },
+   { SUF_Z, 0, CPU_386, CPU_Undoc, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x10, 0}, 0, 2, 317 },
+    { SUF_Z, 0, CPU_386, CPU_Undoc, 0, {0, 0, 0}, 16, 0, 0, 2, {0x0F, 0x11, 0}, 0, 2, 254 },
+    { SUF_Z, 0, CPU_386, CPU_Undoc, 0, {0, 0, 0}, 32, 0, 0, 2, {0x0F, 0x11, 0}, 0, 2, 260 },
+    { SUF_Z, 0, CPU_386, CPU_Undoc, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x12, 0}, 0, 2, 319 },
     { SUF_Z, 0, CPU_386, CPU_Undoc, 0, {0, 0, 0}, 16, 0, 0, 2, {0x0F, 0x13, 0}, 0, 2, 98 },
     { SUF_Z, 0, CPU_386, CPU_Undoc, 0, {0, 0, 0}, 32, 0, 0, 2, {0x0F, 0x13, 0}, 0, 2, 101 }
 };
 
 static const x86_insn_info xbts_insn[] = {
-   { SUF_Z, 0, CPU_386, CPU_Obs, CPU_Undoc, {0, 0, 0}, 16, 0, 0, 2, {0x0F, 0xA6, 0}, 0, 2, 405 },
-    { SUF_Z, 0, CPU_386, CPU_Obs, CPU_Undoc, {0, 0, 0}, 32, 0, 0, 2, {0x0F, 0xA6, 0}, 0, 2, 311 }
+   { SUF_Z, 0, CPU_386, CPU_Obs, CPU_Undoc, {0, 0, 0}, 16, 0, 0, 2, {0x0F, 0xA6, 0}, 0, 2, 459 },
+    { SUF_Z, 0, CPU_386, CPU_Obs, CPU_Undoc, {0, 0, 0}, 32, 0, 0, 2, {0x0F, 0xA6, 0}, 0, 2, 353 }
 };
author	hbono@chromium.org <hbono@chromium.org@4ff67af0-8c30-449e-8e8b-ad334ec8d88c>	2012-11-14 05:26:34 +0000
committer	hbono@chromium.org <hbono@chromium.org@4ff67af0-8c30-449e-8e8b-ad334ec8d88c>	2012-11-14 05:26:34 +0000
commit	d65182f1818d1c19e6f3866ab6e68a262fad5185 (patch)
tree	641f34f2ec8c652a523034a533dc6c57e7ef853b
parent	6b5f1af666c0fad6e4282d07267ff5ae84e7df9d (diff)
download	patched-yasm-d65182f1818d1c19e6f3866ab6e68a262fad5185.tar.gz