diff options
author | Mike J. Chen <mjchen@google.com> | 2012-04-02 17:08:21 -0700 |
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committer | Mike J. Chen <mjchen@google.com> | 2012-04-02 17:08:21 -0700 |
commit | 61be87ffa9c6e5aad33a6b689fecbb172c77b8cf (patch) | |
tree | 95742afe4b722379a735764da826616125b29007 | |
parent | ac7d3bf815036042bdf0e920ca0e4435d5a4cdad (diff) | |
parent | 11c8c96d1cb9f1afef03ff496880945ada7c3d62 (diff) | |
download | uboot-61be87ffa9c6e5aad33a6b689fecbb172c77b8cf.tar.gz |
Merge remote-tracking branch 'goog/android-master' into android-omap-tungsten
-rw-r--r-- | arch/arm/cpu/armv7/omap4/clocks.c | 108 | ||||
-rw-r--r-- | arch/arm/cpu/armv7/omap4/emif.c | 4 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-omap4/emif.h | 6 | ||||
-rw-r--r-- | drivers/mmc/omap_hsmmc.c | 4 | ||||
-rw-r--r-- | drivers/usb/phy/twl4030.c | 16 |
5 files changed, 83 insertions, 55 deletions
diff --git a/arch/arm/cpu/armv7/omap4/clocks.c b/arch/arm/cpu/armv7/omap4/clocks.c index c8777580e..ae91fc1e0 100644 --- a/arch/arm/cpu/armv7/omap4/clocks.c +++ b/arch/arm/cpu/armv7/omap4/clocks.c @@ -36,15 +36,13 @@ #include <asm/arch/sys_proto.h> #include <asm/utils.h> #include <asm/omap_gpio.h> +#include <asm/arch/emif.h> -#ifndef CONFIG_OMAP4430_ES1_0_MPU_DPLL -#define CONFIG_OMAP4430_ES1_0_MPU_DPLL mpu_dpll_params_1200mhz -#endif -#ifndef CONFIG_OMAP4430_non_ES1_0_MPU_DPLL -#define CONFIG_OMAP4430_non_ES1_0_MPU_DPLL mpu_dpll_params_1584mhz +#ifndef CONFIG_OMAP4430_MPU_DPLL +#define CONFIG_OMAP4430_MPU_DPLL mpu_dpll_params_1200mhz #endif #ifndef CONFIG_OMAP4460_MPU_DPLL -#define CONFIG_OMAP4460_MPU_DPLL mpu_dpll_params_1840mhz +#define CONFIG_OMAP4460_MPU_DPLL mpu_dpll_params_1400mhz #endif #define str(s) #s @@ -85,15 +83,15 @@ static const u32 sys_clk_array[8] = { * Please use this tool for creating the table for any new frequency. */ -/* dpll locked at 1840 MHz MPU clk at 920 MHz(OPP Turbo 4460) - DCC OFF */ -static const struct dpll_params mpu_dpll_params_1840mhz[NUM_SYS_CLKS] = { - {230, 2, 1, -1, -1, -1, -1, -1}, /* 12 MHz */ - {920, 12, 1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {219, 3, 1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ - {575, 11, 1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ - {460, 12, 1, -1, -1, -1, -1, -1}, /* 26 MHz */ - {920, 26, 1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {575, 23, 1, -1, -1, -1, -1, -1} /* 38.4 MHz */ +/* dpll locked at 1400 MHz MPU clk at 700 MHz(OPP100) - DCC OFF */ +static const struct dpll_params mpu_dpll_params_1400mhz[NUM_SYS_CLKS] = { + {175, 2, 1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {700, 12, 1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {125, 2, 1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {401, 10, 1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {350, 12, 1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {700, 26, 1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {638, 34, 1, -1, -1, -1, -1, -1} /* 38.4 MHz */ }; /* dpll locked at 700 MHz MPU clk at 350 MHz(OPP50 4460) - DCC OFF */ @@ -130,34 +128,34 @@ static const struct dpll_params mpu_dpll_params_1200mhz[NUM_SYS_CLKS] = { }; static const struct dpll_params core_dpll_params_1600mhz[NUM_SYS_CLKS] = { - {200, 2, 1, 5, 8, 4, 6, 5}, /* 12 MHz */ - {800, 12, 1, 5, 8, 4, 6, 5}, /* 13 MHz */ - {619, 12, 1, 5, 8, 4, 6, 5}, /* 16.8 MHz */ - {125, 2, 1, 5, 8, 4, 6, 5}, /* 19.2 MHz */ - {400, 12, 1, 5, 8, 4, 6, 5}, /* 26 MHz */ - {800, 26, 1, 5, 8, 4, 6, 5}, /* 27 MHz */ - {125, 5, 1, 5, 8, 4, 6, 5} /* 38.4 MHz */ + {200, 2, 1, 5, 8, 4, 6, 6}, /* 12 MHz */ + {800, 12, 1, 5, 8, 4, 6, 6}, /* 13 MHz */ + {619, 12, 1, 5, 8, 4, 6, 6}, /* 16.8 MHz */ + {125, 2, 1, 5, 8, 4, 6, 6}, /* 19.2 MHz */ + {400, 12, 1, 5, 8, 4, 6, 6}, /* 26 MHz */ + {800, 26, 1, 5, 8, 4, 6, 6}, /* 27 MHz */ + {125, 5, 1, 5, 8, 4, 6, 6} /* 38.4 MHz */ }; static const struct dpll_params core_dpll_params_es1_1524mhz[NUM_SYS_CLKS] = { - {127, 1, 1, 5, 8, 4, 6, 5}, /* 12 MHz */ - {762, 12, 1, 5, 8, 4, 6, 5}, /* 13 MHz */ - {635, 13, 1, 5, 8, 4, 6, 5}, /* 16.8 MHz */ - {635, 15, 1, 5, 8, 4, 6, 5}, /* 19.2 MHz */ - {381, 12, 1, 5, 8, 4, 6, 5}, /* 26 MHz */ - {254, 8, 1, 5, 8, 4, 6, 5}, /* 27 MHz */ - {496, 24, 1, 5, 8, 4, 6, 5} /* 38.4 MHz */ + {127, 1, 1, 5, 8, 4, 6, 6}, /* 12 MHz */ + {762, 12, 1, 5, 8, 4, 6, 6}, /* 13 MHz */ + {635, 13, 1, 5, 8, 4, 6, 6}, /* 16.8 MHz */ + {635, 15, 1, 5, 8, 4, 6, 6}, /* 19.2 MHz */ + {381, 12, 1, 5, 8, 4, 6, 6}, /* 26 MHz */ + {254, 8, 1, 5, 8, 4, 6, 6}, /* 27 MHz */ + {496, 24, 1, 5, 8, 4, 6, 6} /* 38.4 MHz */ }; static const struct dpll_params core_dpll_params_es2_1600mhz_ddr200mhz[NUM_SYS_CLKS] = { - {200, 2, 2, 5, 8, 4, 6, 5}, /* 12 MHz */ - {800, 12, 2, 5, 8, 4, 6, 5}, /* 13 MHz */ - {619, 12, 2, 5, 8, 4, 6, 5}, /* 16.8 MHz */ - {125, 2, 2, 5, 8, 4, 6, 5}, /* 19.2 MHz */ - {400, 12, 2, 5, 8, 4, 6, 5}, /* 26 MHz */ - {800, 26, 2, 5, 8, 4, 6, 5}, /* 27 MHz */ - {125, 5, 2, 5, 8, 4, 6, 5} /* 38.4 MHz */ + {200, 2, 2, 5, 8, 4, 6, 6}, /* 12 MHz */ + {800, 12, 2, 5, 8, 4, 6, 6}, /* 13 MHz */ + {619, 12, 2, 5, 8, 4, 6, 6}, /* 16.8 MHz */ + {125, 2, 2, 5, 8, 4, 6, 6}, /* 19.2 MHz */ + {400, 12, 2, 5, 8, 4, 6, 6}, /* 26 MHz */ + {800, 26, 2, 5, 8, 4, 6, 6}, /* 27 MHz */ + {125, 5, 2, 5, 8, 4, 6, 6} /* 38.4 MHz */ }; static const struct dpll_params per_dpll_params_1536mhz[NUM_SYS_CLKS] = { @@ -381,10 +379,10 @@ static void print_current_freq(u32 *const base) /* * Lock MPU dpll * - * Resulting MPU frequencies: + * Resulting MPU frequencies (OPP_NUM): * 4430 ES1.0 : 600 MHz - * 4430 ES2.x : 792 MHz (OPP Turbo) - * 4460 : 920 MHz (OPP Turbo) - DCC disabled + * 4430 ES2.x : 600 MHz + * 4460 : 700 MHz */ void configure_mpu_dpll(void) { @@ -395,11 +393,8 @@ void configure_mpu_dpll(void) omap4_rev = omap_revision(); sysclk_ind = get_sys_clk_index(); - if (omap4_rev == OMAP4430_ES1_0) - SET_MPU_DPLL_PARAMS(params, CONFIG_OMAP4430_ES1_0_MPU_DPLL, - sysclk_ind); - else if (omap4_rev < OMAP4460_ES1_0) - SET_MPU_DPLL_PARAMS(params, CONFIG_OMAP4430_non_ES1_0_MPU_DPLL, + if (omap4_rev < OMAP4460_ES1_0) + SET_MPU_DPLL_PARAMS(params, CONFIG_OMAP4430_MPU_DPLL, sysclk_ind); else SET_MPU_DPLL_PARAMS(params, CONFIG_OMAP4460_MPU_DPLL, @@ -425,6 +420,13 @@ void configure_mpu_dpll(void) debug("MPU DPLL locked\n"); } +static void init_m2_core_dpll(u32 *const base, int m2) +{ + struct dpll_regs *const dpll_regs = (struct dpll_regs *)base; + + writel(m2, &dpll_regs->cm_div_m2_dpll); +} + static void setup_dplls(void) { u32 sysclk_ind, temp; @@ -435,12 +437,17 @@ static void setup_dplls(void) /* CORE dpll */ params = get_core_dpll_params(); /* default - safest */ + /* - * Do not lock the core DPLL now. Just set it up. - * Core DPLL will be locked after setting up EMIF - * using the FREQ_UPDATE method(freq_update_core()) + * Lock the core DPLL here to get the right sequence. + * But set the M2 post divider to a maximum value so that + * emif/ddr freqeuncy is at a low value for the beginning. + * FREQ_UPDATE method(freq_update_core()) updates the correct + * m2 later. */ - do_setup_dpll(&prcm->cm_clkmode_dpll_core, params, DPLL_NO_LOCK); + do_setup_dpll(&prcm->cm_clkmode_dpll_core, params, DPLL_LOCK); + init_m2_core_dpll(&prcm->cm_clkmode_dpll_core, CORE_DPLL_M2_INIT); + /* Set the ratios for CORE_CLK, L3_CLK, L4_CLK */ temp = (CLKSEL_CORE_X2_DIV_1 << CLKSEL_CORE_SHIFT) | (CLKSEL_L3_CORE_DIV_2 << CLKSEL_L3_SHIFT) | @@ -448,13 +455,14 @@ static void setup_dplls(void) writel(temp, &prcm->cm_clksel_core); debug("Core DPLL configured\n"); + /* MPU dpll */ + configure_mpu_dpll(); + /* lock PER dpll */ do_setup_dpll(&prcm->cm_clkmode_dpll_per, &per_dpll_params_1536mhz[sysclk_ind], DPLL_LOCK); debug("PER DPLL locked\n"); - /* MPU dpll */ - configure_mpu_dpll(); } static void setup_non_essential_dplls(void) diff --git a/arch/arm/cpu/armv7/omap4/emif.c b/arch/arm/cpu/armv7/omap4/emif.c index 45c88aba8..77fcc2029 100644 --- a/arch/arm/cpu/armv7/omap4/emif.c +++ b/arch/arm/cpu/armv7/omap4/emif.c @@ -1230,10 +1230,6 @@ void sdram_init(void) in_sdram = running_from_sdram(); debug("in_sdram = %d\n", in_sdram); - if (!in_sdram) { - bypass_dpll(&prcm->cm_clkmode_dpll_core); - } - do_sdram_init(OMAP44XX_EMIF1); do_sdram_init(OMAP44XX_EMIF2); diff --git a/arch/arm/include/asm/arch-omap4/emif.h b/arch/arm/include/asm/arch-omap4/emif.h index 3a549bad5..35a7a4d5c 100644 --- a/arch/arm/include/asm/arch-omap4/emif.h +++ b/arch/arm/include/asm/arch-omap4/emif.h @@ -907,6 +907,12 @@ struct dmm_lisa_map_regs { #define MR8_IO_WIDTH_SHIFT 0x6 #define MR8_IO_WIDTH_MASK (0x3 << 0x6) +/* + * CORE DPLL m2 divider init, set to maximum + * to have the lowest possible frequency. + */ +#define CORE_DPLL_M2_INIT 0x1F + struct lpddr2_addressing { u8 num_banks; u8 t_REFI_us_x10; diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c index fbac289a5..b65f72cca 100644 --- a/drivers/mmc/omap_hsmmc.c +++ b/drivers/mmc/omap_hsmmc.c @@ -734,6 +734,10 @@ int omap_mmc_init(int dev_index) */ if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21)) mmc->b_max = 1; + + /* MMC1 and MMC2 support 8-bit, but MMC0 only supports 4-bit */ + if (dev_index != 0) + mmc->host_caps |= MMC_MODE_8BIT; #endif mmc_register(mmc); diff --git a/drivers/usb/phy/twl4030.c b/drivers/usb/phy/twl4030.c index 54d2e615c..6dcf6c92e 100644 --- a/drivers/usb/phy/twl4030.c +++ b/drivers/usb/phy/twl4030.c @@ -118,10 +118,22 @@ static void twl4030_phy_power(void) { u8 pwr, clk; - /* Power the PHY */ + /* First make sure PHY is powered down to + * clear any state from a previous reboot and + * force unenumeration. Otherwise, sometimes + * the device doesn't enumerate properly on + * a warm reboot. + */ + + /* Power down the PHY */ pwr = twl4030_usb_read(TWL4030_USB_PHY_PWR_CTRL); + pwr |= PHYPWD; + twl4030_usb_write(TWL4030_USB_PHY_PWR_CTRL, pwr); + + /* Power the PHY */ pwr &= ~PHYPWD; twl4030_usb_write(TWL4030_USB_PHY_PWR_CTRL, pwr); + /* Enable clocks */ clk = twl4030_usb_read(TWL4030_USB_PHY_CLK_CTRL); clk |= CLOCKGATING_EN | CLK32K_EN; @@ -139,6 +151,8 @@ int twl4030_usb_ulpi_init(void) long timeout = 1000 * 1000; /* 1 sec */; u8 clk, sts, pwr; + i2c_set_bus_num(0); + /* twl4030 ldo init */ twl4030_usb_ldo_init(); |