diff options
Diffstat (limited to 'libc/kernel/uapi/drm/amdgpu_drm.h')
| -rw-r--r-- | libc/kernel/uapi/drm/amdgpu_drm.h | 38 |
1 files changed, 37 insertions, 1 deletions
diff --git a/libc/kernel/uapi/drm/amdgpu_drm.h b/libc/kernel/uapi/drm/amdgpu_drm.h index f8eb023d8..3764d51da 100644 --- a/libc/kernel/uapi/drm/amdgpu_drm.h +++ b/libc/kernel/uapi/drm/amdgpu_drm.h @@ -65,13 +65,13 @@ extern "C" { #define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1) #define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2) #define AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3) -#define AMDGPU_GEM_CREATE_SHADOW (1 << 4) #define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5) #define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6) #define AMDGPU_GEM_CREATE_EXPLICIT_SYNC (1 << 7) #define AMDGPU_GEM_CREATE_CP_MQD_GFX9 (1 << 8) #define AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE (1 << 9) #define AMDGPU_GEM_CREATE_ENCRYPTED (1 << 10) +#define AMDGPU_GEM_CREATE_PREEMPTIBLE (1 << 11) struct drm_amdgpu_gem_create_in { __u64 bo_size; __u64 alignment; @@ -452,6 +452,7 @@ struct drm_amdgpu_cs_chunk_data { #define AMDGPU_INFO_VBIOS 0x1B #define AMDGPU_INFO_VBIOS_SIZE 0x1 #define AMDGPU_INFO_VBIOS_IMAGE 0x2 +#define AMDGPU_INFO_VBIOS_INFO 0x3 #define AMDGPU_INFO_NUM_HANDLES 0x1C #define AMDGPU_INFO_SENSOR 0x1D #define AMDGPU_INFO_SENSOR_GFX_SCLK 0x1 @@ -480,6 +481,9 @@ struct drm_amdgpu_cs_chunk_data { #define AMDGPU_INFO_RAS_ENABLED_MP0 (1 << 11) #define AMDGPU_INFO_RAS_ENABLED_MP1 (1 << 12) #define AMDGPU_INFO_RAS_ENABLED_FUSE (1 << 13) +#define AMDGPU_INFO_VIDEO_CAPS 0x21 +#define AMDGPU_INFO_VIDEO_CAPS_DECODE 0 +#define AMDGPU_INFO_VIDEO_CAPS_ENCODE 1 #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff #define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8 @@ -517,6 +521,9 @@ struct drm_amdgpu_info { struct { __u32 type; } sensor_info; + struct { + __u32 type; + } video_cap; }; }; struct drm_amdgpu_info_gds { @@ -549,6 +556,14 @@ struct drm_amdgpu_info_firmware { __u32 ver; __u32 feature; }; +struct drm_amdgpu_info_vbios { + __u8 name[64]; + __u8 vbios_pn[64]; + __u32 version; + __u32 pad; + __u8 vbios_ver_str[32]; + __u8 date[32]; +}; #define AMDGPU_VRAM_TYPE_UNKNOWN 0 #define AMDGPU_VRAM_TYPE_GDDR1 1 #define AMDGPU_VRAM_TYPE_DDR2 2 @@ -636,6 +651,26 @@ struct drm_amdgpu_info_vce_clock_table { __u32 num_valid_entries; __u32 pad; }; +#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2 0 +#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4 1 +#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1 2 +#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC 3 +#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC 4 +#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG 5 +#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9 6 +#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1 7 +#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_COUNT 8 +struct drm_amdgpu_info_video_codec_info { + __u32 valid; + __u32 max_width; + __u32 max_height; + __u32 max_pixels_per_frame; + __u32 max_level; + __u32 pad; +}; +struct drm_amdgpu_info_video_caps { + struct drm_amdgpu_info_video_codec_info codec_info[AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_COUNT]; +}; #define AMDGPU_FAMILY_UNKNOWN 0 #define AMDGPU_FAMILY_SI 110 #define AMDGPU_FAMILY_CI 120 @@ -646,6 +681,7 @@ struct drm_amdgpu_info_vce_clock_table { #define AMDGPU_FAMILY_RV 142 #define AMDGPU_FAMILY_NV 143 #define AMDGPU_FAMILY_VGH 144 +#define AMDGPU_FAMILY_YC 146 #ifdef __cplusplus } #endif |